For detailed information on CSRNG design features, please see the CSRNG HWIP technical specification.
CSRNG testbench has been constructed based on the CIP testbench architecture.
Top level testbench is located at hw/ip/csrng/dv/tb/tb.sv
. It instantiates the CSRNG DUT module hw/ip/csrng/rtl/csrng.sv
. In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db
:
pins_if
pins_if
pins_if
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
All common types and methods defined at the package level can be found in csrng_env_pkg
. Some of them in use are:
parameter uint NUM_HW_APPS = 2;
CSRNG testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into CSRNG device.
CSRNG testbench instantiates this push_pull_agent which models the ENTROPY_SRC module.
CSRNG testbench instantiates this agent which models the EDN module.
The CSRNG RAL model is created with the ralgen
FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking regtool
:
All test sequences reside in hw/ip/csrng/dv/env/seq_lib
. The csrng_base_vseq
virtual sequence is extended from cip_base_vseq
and serves as a starting point. All test sequences are extended from csrng_base_vseq
. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows:
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
hw/dv/sv/cip_lib/cip_base_env_cov.sv
: Cover interrupt value, interrupt enable, intr_test, interrupt pinThe csrng_scoreboard
is primarily used for end to end checking. It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
tb/csrng_bind.sv
binds the tlul_assert
assertions to the IP to ensure TileLink interface protocol compliance.We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here's how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/csrng/dv/csrng_sim_cfg.hjson -i csrng_smoke
{{< incGenFromIpDesc “../../data/csrng_testplan.hjson” “testplan” >}}