diff --git a/hw/ip/rv_dm/dv/rv_dm_sim.core b/hw/ip/rv_dm/dv/rv_dm_sim.core
index f9bc0aa..571fedd 100644
--- a/hw/ip/rv_dm/dv/rv_dm_sim.core
+++ b/hw/ip/rv_dm/dv/rv_dm_sim.core
@@ -8,13 +8,11 @@
   files_rtl:
     depend:
       - lowrisc:ip:rv_dm:0.1
-    files:
-      - tb/rv_dm_bind.sv
-    file_type: systemVerilogSource
 
   files_dv:
     depend:
       - lowrisc:dv:rv_dm_test
+      - lowrisc:dv:rv_dm_sva
     files:
       - tb/tb.sv
     file_type: systemVerilogSource
diff --git a/hw/ip/rv_dm/dv/tb/rv_dm_bind.sv b/hw/ip/rv_dm/dv/sva/rv_dm_bind.sv
similarity index 100%
rename from hw/ip/rv_dm/dv/tb/rv_dm_bind.sv
rename to hw/ip/rv_dm/dv/sva/rv_dm_bind.sv
diff --git a/hw/ip/rv_dm/dv/sva/rv_dm_sva.core b/hw/ip/rv_dm/dv/sva/rv_dm_sva.core
new file mode 100644
index 0000000..1823be3
--- /dev/null
+++ b/hw/ip/rv_dm/dv/sva/rv_dm_sva.core
@@ -0,0 +1,18 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:rv_dm_sva:0.1"
+description: "RV_DM assertion modules and bind file."
+filesets:
+  files_dv:
+    depend:
+      - lowrisc:tlul:headers
+    files:
+      - rv_dm_bind.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+      - files_dv