diff --git a/hw/ip/flash_ctrl/rtl/flash_phy.sv b/hw/ip/flash_ctrl/rtl/flash_phy.sv
index 9314f04..e8ccea0 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy.sv
@@ -81,7 +81,7 @@
   end
 
   // ready when prim_flash is ready and no ongoing host activity
-  assign host_req_rdy_o = host_req_rdy[host_bank_sel] & new_rd_rdy;
+  assign host_req_rdy_o = host_req_rdy[host_bank_sel] & new_rd_rdy & host_req_i;
   assign host_req_done_o = host_req_done[host_last_bank_sel];
   assign host_rdata_o = rd_data[host_last_bank_sel];
 
diff --git a/hw/ip/tlul/adapter_flash.core b/hw/ip/tlul/adapter_flash.core
deleted file mode 100644
index 26b1acd..0000000
--- a/hw/ip/tlul/adapter_flash.core
+++ /dev/null
@@ -1,21 +0,0 @@
-CAPI=2:
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:tlul:adapter_flash:0.1"
-description: "TL-UL to FLASH adapter (device)"
-
-filesets:
-  files_rtl:
-    depend:
-      - lowrisc:prim:all
-      - lowrisc:tlul:common
-    files:
-      - rtl/tlul_adapter_flash.sv
-    file_type: systemVerilogSource
-
-targets:
-  default: &default_target
-    filesets:
-      - files_rtl
-    toplevel: tlul_adapter_flash
diff --git a/hw/ip/tlul/rtl/tlul_adapter_flash.sv b/hw/ip/tlul/rtl/tlul_adapter_flash.sv
deleted file mode 100644
index 847ef23..0000000
--- a/hw/ip/tlul/rtl/tlul_adapter_flash.sv
+++ /dev/null
@@ -1,147 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-/**
- * Tile-Link UL adapter for flash-like devices
- *
- */
-module tlul_adapter_flash #(
-  parameter Outstanding = 1
-) (
-  input   clk_i,
-  input   rst_ni,
-
-  // TL-UL interface
-  input   tlul_pkg::tl_h2d_t  tl_i,
-  output  tlul_pkg::tl_d2h_t  tl_o,
-
-  // Flash interface
-  output logic          req_o,
-  input                 req_rdy_i,
-  input                 req_done_i,
-  output logic [top_pkg::FLASH_AW-1:0] addr_o,
-  input        [top_pkg::FLASH_DW-1:0] rdata_i
-);
-
-  localparam int DataBitWidth = $clog2(top_pkg::FLASH_BYTES_PER_WORD);
-  localparam int TotalBitWidth = DataBitWidth + top_pkg::FLASH_AW;
-
-  import tlul_pkg::*;
-
-  typedef struct packed {
-    tl_a_op_e                   req_op;
-    logic [top_pkg::TL_SZW-1:0] req_size;
-    logic [top_pkg::TL_AIW-1:0] req_source;
-  } txn_attr_t ;
-
-  typedef struct packed {
-    txn_attr_t                    req_attr;
-    logic [top_pkg::FLASH_AW-1:0] req_address;
-  } req_t ;
-
-  typedef struct packed {
-    logic [top_pkg::TL_DW-1:0]  rsp_data;
-    logic                       rsp_err;
-    logic [top_pkg::TL_SZW-1:0] rsp_size;
-    logic [top_pkg::TL_AIW-1:0] rsp_source;
-  } rsp_t ;
-
-  localparam int ReqFifoWidth = $bits(req_t) ;
-  localparam int RspFifoWidth = $bits(rsp_t) ;
-
-  req_t reqfifo_wdata, reqfifo_rdata;
-  rsp_t rspfifo_wdata, rspfifo_rdata;
-  logic reqfifo_rvalid;
-  logic rspfifo_wready;
-  txn_attr_t req_attr;
-
-  assign reqfifo_wdata.req_attr.req_op = tl_i.a_opcode;
-  assign reqfifo_wdata.req_attr.req_size = tl_i.a_size;
-  assign reqfifo_wdata.req_attr.req_source = tl_i.a_source;
-  assign reqfifo_wdata.req_address = tl_i.a_address[DataBitWidth +: top_pkg::FLASH_AW];
-
-
-  // REQ FIFO
-  prim_fifo_sync #(
-    .Width  (ReqFifoWidth),
-    .Pass   (1'b1),
-    .Depth  (Outstanding)
-  ) u_reqfifo (
-    .clk_i,
-    .rst_ni,
-    .wvalid (tl_i.a_valid),
-    .wready (tl_o.a_ready),
-    .wdata  (reqfifo_wdata),
-    .depth  (),
-    .rvalid (reqfifo_rvalid),
-    .rready (req_o & req_rdy_i),
-    .rdata  (reqfifo_rdata)
-  );
-
-  // The FIFO above immediately pushes to the next entry when request is accepted
-  // This is to ensure back to back reads can happen without a command gap.  So the
-  // request attributes need to be separately saved for the response path
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      req_attr.req_op <= Get;
-      req_attr.req_size <= {top_pkg::TL_SZW{1'b0}};
-      req_attr.req_source <= {top_pkg::TL_AIW{1'b0}};
-    end else if(req_o && req_rdy_i) begin
-      req_attr <= reqfifo_rdata.req_attr;
-    end
-  end
-
-  assign rspfifo_wdata.rsp_data = rdata_i;
-  assign rspfifo_wdata.rsp_err = req_attr.req_op != Get;
-  assign rspfifo_wdata.rsp_size = req_attr.req_size;
-  assign rspfifo_wdata.rsp_source = req_attr.req_source;
-
-  // RSP FIFO
-  prim_fifo_sync #(
-    .Width  (RspFifoWidth),
-    .Pass   (1'b1),
-    .Depth  (Outstanding)
-  ) u_rspfifo (
-    .clk_i,
-    .rst_ni,
-    .wvalid (req_done_i),
-    .wready (rspfifo_wready),
-    .wdata  (rspfifo_wdata),
-    .depth  (),
-    .rvalid (tl_o.d_valid),
-    .rready (tl_i.d_ready),
-    .rdata  (rspfifo_rdata)
-  );
-
-
-  // assignments to tlul interface
-  assign tl_o.d_opcode = AccessAckData;
-  assign tl_o.d_param  = '0;
-  assign tl_o.d_size   = rspfifo_rdata.rsp_size;
-  assign tl_o.d_source = rspfifo_rdata.rsp_source;
-  assign tl_o.d_sink   = 1'b0;
-  assign tl_o.d_data   = rspfifo_rdata.rsp_data;
-  assign tl_o.d_user   = '0;
-  assign tl_o.d_error  = rspfifo_rdata.rsp_err;
-
-  //assignments to flash interface
-  assign req_o = reqfifo_rvalid & rspfifo_wready;
-  assign addr_o = reqfifo_rdata.req_address;
-
-  //unused interface
-  logic [top_pkg::TL_DW-1:0] unused_data;
-  logic [top_pkg::TL_DBW-1:0] unused_mask;
-  logic [2:0] unused_param;
-  logic [top_pkg::TL_DUW-1:0] unused_user;
-  logic [DataBitWidth-1:0] unused_low_addr;
-  logic [top_pkg::TL_DW - TotalBitWidth - 1:0] unused_high_addr;
-
-  assign unused_data = tl_i.a_data;
-  assign unused_mask = tl_i.a_mask;
-  assign unused_param = tl_i.a_param;
-  assign unused_user = tl_i.a_user;
-  assign unused_low_addr = tl_i.a_address[DataBitWidth-1:0];
-  assign unused_high_addr = tl_i.a_address[top_pkg::TL_DW-1 : TotalBitWidth];
-
-endmodule
diff --git a/hw/ip/tlul/rtl/tlul_adapter_sram.sv b/hw/ip/tlul/rtl/tlul_adapter_sram.sv
index f8c622c..3a1b281 100644
--- a/hw/ip/tlul/rtl/tlul_adapter_sram.sv
+++ b/hw/ip/tlul/rtl/tlul_adapter_sram.sv
@@ -13,7 +13,8 @@
   parameter int SramAw      = 12,
   parameter int SramDw      = 32, // Current version supports TL-UL width only
   parameter int Outstanding = 1,  // Only one request is accepted
-  parameter bit ByteAccess  = 1   // 1: true, 0: false
+  parameter bit ByteAccess  = 1,  // 1: true, 0: false
+  parameter bit ErrOnWrite  = 0   // 1: Writes not allowed, automatically error
 ) (
   input   clk_i,
   input   rst_ni,
@@ -67,6 +68,8 @@
   rsp_t rspfifo_wdata,  rspfifo_rdata;
 
   logic wrsp_error;
+  logic wr_attr_error;
+  logic wr_vld_error;
 
   assign tl_o = '{
       d_valid  : reqfifo_rdata.op ? reqfifo_rvalid : rspfifo_rvalid ,
@@ -99,14 +102,21 @@
   end
 
   if (ByteAccess == 1) begin : gen_wrsp_byte
-    assign wrsp_error = (tl_i.a_opcode == PutFullData &&
+    assign wr_attr_error = (tl_i.a_opcode == PutFullData &&
                         (tl_i.a_mask != '1 || tl_i.a_size != 2'h2));
   end else begin : gen_wrsp_word
-    assign wrsp_error = (tl_i.a_mask != '1 || tl_i.a_size != 2'h2);
+    assign wr_attr_error = (tl_i.a_mask != '1 || tl_i.a_size != 2'h2);
   end
 
-  // TODO: handle rvalid
-  assign reqfifo_wvalid = req_o && gnt_i ;
+  if (ErrOnWrite == 1) begin : gen_no_writes
+    assign wr_vld_error = tl_i.a_opcode != Get;
+  end else begin : gen_writes_allowed
+    assign wr_vld_error = 1'b0;
+  end
+
+  assign wrsp_error = wr_attr_error | wr_vld_error;
+
+  assign reqfifo_wvalid = req_o & gnt_i ;
   assign reqfifo_wdata  = '{
     op: we_o,
     wrsp_error: wrsp_error,
diff --git a/hw/ip/tlul/tlul.core b/hw/ip/tlul/tlul.core
index 0cc42e0..ca3fd9d 100644
--- a/hw/ip/tlul/tlul.core
+++ b/hw/ip/tlul/tlul.core
@@ -12,7 +12,6 @@
       - lowrisc:tlul:socket_m1
       - lowrisc:tlul:adapter_sram
       - lowrisc:tlul:adapter_reg
-      - lowrisc:tlul:adapter_flash
       - lowrisc:tlul:sram2tlul
 
 targets:
diff --git a/hw/top_earlgrey/doc/top_earlgrey.tpl.sv b/hw/top_earlgrey/doc/top_earlgrey.tpl.sv
index bae971b..dc95882 100644
--- a/hw/top_earlgrey/doc/top_earlgrey.tpl.sv
+++ b/hw/top_earlgrey/doc/top_earlgrey.tpl.sv
@@ -244,7 +244,8 @@
   tlul_adapter_sram #(
     .SramAw(${addr_width}),
     .SramDw(${data_width}),
-    .Outstanding(1)
+    .Outstanding(1),
+    .ErrOnWrite(1)
   ) tl_adapter_${m["name"]} (
     .clk_i,
     .rst_ni   (ndmreset_n),
@@ -290,8 +291,12 @@
   logic [FLASH_DW-1:0] flash_host_rdata;
   logic [FLASH_AW-1:0] flash_host_addr;
 
-  tlul_adapter_flash #(
-    .Outstanding(1)
+  tlul_adapter_sram #(
+    .SramAw(FLASH_AW),
+    .SramDw(FLASH_DW),
+    .Outstanding(1),
+    .ByteAccess(0),
+    .ErrOnWrite(1)
   ) tl_adapter_${m["name"]} (
     .clk_i,
     .rst_ni     (ndmreset_n),
@@ -299,11 +304,15 @@
     .tl_i       (tl_${m["name"]}_d_h2d),
     .tl_o       (tl_${m["name"]}_d_d2h),
 
-    .req_o      (flash_host_req),
-    .req_rdy_i  (flash_host_req_rdy),
-    .addr_o     (flash_host_addr),
-    .req_done_i (flash_host_req_done),
-    .rdata_i    (flash_host_rdata)
+    .req_o    (flash_host_req),
+    .gnt_i    (flash_host_req_rdy),
+    .we_o     (),
+    .addr_o   (flash_host_addr),
+    .wdata_o  (),
+    .wmask_o  (),
+    .rdata_i  (flash_host_rdata),
+    .rvalid_i (flash_host_req_done),
+    .rerror_i (2'b00)
   );
 
   flash_phy #(
diff --git a/hw/top_earlgrey/dv/env/chip_reg_block.sv b/hw/top_earlgrey/dv/env/chip_reg_block.sv
index c63707f..176c267 100644
--- a/hw/top_earlgrey/dv/env/chip_reg_block.sv
+++ b/hw/top_earlgrey/dv/env/chip_reg_block.sv
@@ -6,6 +6,72 @@
 // Do Not Edit directly
 
 // Forward declare all register/memory/block classes
+typedef class spi_device_reg_intr_state;
+typedef class spi_device_reg_intr_enable;
+typedef class spi_device_reg_intr_test;
+typedef class spi_device_reg_control;
+typedef class spi_device_reg_cfg;
+typedef class spi_device_reg_fifo_level;
+typedef class spi_device_reg_async_fifo_level;
+typedef class spi_device_reg_status;
+typedef class spi_device_reg_rxf_ptr;
+typedef class spi_device_reg_txf_ptr;
+typedef class spi_device_reg_rxf_addr;
+typedef class spi_device_reg_txf_addr;
+typedef class spi_device_mem_buffer;
+typedef class spi_device_reg_block;
+
+typedef class flash_ctrl_reg_intr_state;
+typedef class flash_ctrl_reg_intr_enable;
+typedef class flash_ctrl_reg_intr_test;
+typedef class flash_ctrl_reg_control;
+typedef class flash_ctrl_reg_addr;
+typedef class flash_ctrl_reg_mp_region_cfg0;
+typedef class flash_ctrl_reg_mp_region_cfg1;
+typedef class flash_ctrl_reg_mp_region_cfg2;
+typedef class flash_ctrl_reg_mp_region_cfg3;
+typedef class flash_ctrl_reg_mp_region_cfg4;
+typedef class flash_ctrl_reg_mp_region_cfg5;
+typedef class flash_ctrl_reg_mp_region_cfg6;
+typedef class flash_ctrl_reg_mp_region_cfg7;
+typedef class flash_ctrl_reg_default_region;
+typedef class flash_ctrl_reg_mp_bank_cfg;
+typedef class flash_ctrl_reg_op_status;
+typedef class flash_ctrl_reg_status;
+typedef class flash_ctrl_reg_scratch;
+typedef class flash_ctrl_reg_fifo_lvl;
+typedef class flash_ctrl_mem_prog_fifo;
+typedef class flash_ctrl_mem_rd_fifo;
+typedef class flash_ctrl_reg_block;
+
+typedef class rv_timer_reg_ctrl;
+typedef class rv_timer_reg_cfg0;
+typedef class rv_timer_reg_timer_v_lower0;
+typedef class rv_timer_reg_timer_v_upper0;
+typedef class rv_timer_reg_compare_lower0_0;
+typedef class rv_timer_reg_compare_upper0_0;
+typedef class rv_timer_reg_intr_enable0;
+typedef class rv_timer_reg_intr_state0;
+typedef class rv_timer_reg_intr_test0;
+typedef class rv_timer_reg_block;
+
+typedef class gpio_reg_intr_state;
+typedef class gpio_reg_intr_enable;
+typedef class gpio_reg_intr_test;
+typedef class gpio_reg_data_in;
+typedef class gpio_reg_direct_out;
+typedef class gpio_reg_masked_out_lower;
+typedef class gpio_reg_masked_out_upper;
+typedef class gpio_reg_direct_oe;
+typedef class gpio_reg_masked_oe_lower;
+typedef class gpio_reg_masked_oe_upper;
+typedef class gpio_reg_intr_ctrl_en_rising;
+typedef class gpio_reg_intr_ctrl_en_falling;
+typedef class gpio_reg_intr_ctrl_en_lvlhigh;
+typedef class gpio_reg_intr_ctrl_en_lvllow;
+typedef class gpio_reg_ctrl_en_input_filter;
+typedef class gpio_reg_block;
+
 typedef class hmac_reg_intr_state;
 typedef class hmac_reg_intr_enable;
 typedef class hmac_reg_intr_test;
@@ -34,46 +100,6 @@
 typedef class hmac_mem_msg_fifo;
 typedef class hmac_reg_block;
 
-typedef class gpio_reg_intr_state;
-typedef class gpio_reg_intr_enable;
-typedef class gpio_reg_intr_test;
-typedef class gpio_reg_data_in;
-typedef class gpio_reg_direct_out;
-typedef class gpio_reg_masked_out_lower;
-typedef class gpio_reg_masked_out_upper;
-typedef class gpio_reg_direct_oe;
-typedef class gpio_reg_masked_oe_lower;
-typedef class gpio_reg_masked_oe_upper;
-typedef class gpio_reg_intr_ctrl_en_rising;
-typedef class gpio_reg_intr_ctrl_en_falling;
-typedef class gpio_reg_intr_ctrl_en_lvlhigh;
-typedef class gpio_reg_intr_ctrl_en_lvllow;
-typedef class gpio_reg_ctrl_en_input_filter;
-typedef class gpio_reg_block;
-
-typedef class flash_ctrl_reg_intr_state;
-typedef class flash_ctrl_reg_intr_enable;
-typedef class flash_ctrl_reg_intr_test;
-typedef class flash_ctrl_reg_control;
-typedef class flash_ctrl_reg_addr;
-typedef class flash_ctrl_reg_mp_region_cfg0;
-typedef class flash_ctrl_reg_mp_region_cfg1;
-typedef class flash_ctrl_reg_mp_region_cfg2;
-typedef class flash_ctrl_reg_mp_region_cfg3;
-typedef class flash_ctrl_reg_mp_region_cfg4;
-typedef class flash_ctrl_reg_mp_region_cfg5;
-typedef class flash_ctrl_reg_mp_region_cfg6;
-typedef class flash_ctrl_reg_mp_region_cfg7;
-typedef class flash_ctrl_reg_default_region;
-typedef class flash_ctrl_reg_mp_bank_cfg;
-typedef class flash_ctrl_reg_op_status;
-typedef class flash_ctrl_reg_status;
-typedef class flash_ctrl_reg_scratch;
-typedef class flash_ctrl_reg_fifo_lvl;
-typedef class flash_ctrl_mem_prog_fifo;
-typedef class flash_ctrl_mem_rd_fifo;
-typedef class flash_ctrl_reg_block;
-
 typedef class uart_reg_intr_state;
 typedef class uart_reg_intr_enable;
 typedef class uart_reg_intr_test;
@@ -88,32 +114,6 @@
 typedef class uart_reg_timeout_ctrl;
 typedef class uart_reg_block;
 
-typedef class spi_device_reg_intr_state;
-typedef class spi_device_reg_intr_enable;
-typedef class spi_device_reg_intr_test;
-typedef class spi_device_reg_control;
-typedef class spi_device_reg_cfg;
-typedef class spi_device_reg_fifo_level;
-typedef class spi_device_reg_async_fifo_level;
-typedef class spi_device_reg_status;
-typedef class spi_device_reg_rxf_ptr;
-typedef class spi_device_reg_txf_ptr;
-typedef class spi_device_reg_rxf_addr;
-typedef class spi_device_reg_txf_addr;
-typedef class spi_device_mem_buffer;
-typedef class spi_device_reg_block;
-
-typedef class rv_timer_reg_ctrl;
-typedef class rv_timer_reg_cfg0;
-typedef class rv_timer_reg_timer_v_lower0;
-typedef class rv_timer_reg_timer_v_upper0;
-typedef class rv_timer_reg_compare_lower0_0;
-typedef class rv_timer_reg_compare_upper0_0;
-typedef class rv_timer_reg_intr_enable0;
-typedef class rv_timer_reg_intr_state0;
-typedef class rv_timer_reg_intr_test0;
-typedef class rv_timer_reg_block;
-
 typedef class rv_plic_reg_ip0;
 typedef class rv_plic_reg_ip1;
 typedef class rv_plic_reg_le0;
@@ -182,16 +182,18 @@
 typedef class chip_mem_eflash;
 typedef class chip_reg_block;
 
-// Block: hmac
-// Class: hmac_reg_intr_state
-class hmac_reg_intr_state extends dv_base_reg;
+// Block: spi_device
+// Class: spi_device_reg_intr_state
+class spi_device_reg_intr_state extends dv_base_reg;
   // fields
-  rand dv_base_reg_field hmac_done;
-  rand dv_base_reg_field fifo_full;
+  rand dv_base_reg_field rxf;
+  rand dv_base_reg_field rxlvl;
+  rand dv_base_reg_field txlvl;
+  rand dv_base_reg_field rxerr;
 
-  `uvm_object_utils(hmac_reg_intr_state)
+  `uvm_object_utils(spi_device_reg_intr_state)
 
-  function new(string       name = "hmac_reg_intr_state",
+  function new(string       name = "spi_device_reg_intr_state",
                int unsigned n_bits = 32,
                int          has_coverage = UVM_NO_COVERAGE);
     super.new(name, n_bits, has_coverage);
@@ -199,8 +201,8 @@
 
   virtual function void build();
     // create fields
-    hmac_done = dv_base_reg_field::type_id::create("hmac_done");
-    hmac_done.configure(
+    rxf = dv_base_reg_field::type_id::create("rxf");
+    rxf.configure(
       .parent(this),
       .size(1),
       .lsb_pos(0),
@@ -210,8 +212,8 @@
       .has_reset(1),
       .is_rand(1),
       .individually_accessible(1));
-    fifo_full = dv_base_reg_field::type_id::create("fifo_full");
-    fifo_full.configure(
+    rxlvl = dv_base_reg_field::type_id::create("rxlvl");
+    rxlvl.configure(
       .parent(this),
       .size(1),
       .lsb_pos(1),
@@ -221,19 +223,43 @@
       .has_reset(1),
       .is_rand(1),
       .individually_accessible(1));
+    txlvl = dv_base_reg_field::type_id::create("txlvl");
+    txlvl.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(2),
+      .access("W1C"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    rxerr = dv_base_reg_field::type_id::create("rxerr");
+    rxerr.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(3),
+      .access("W1C"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
   endfunction : build
 
-endclass : hmac_reg_intr_state
+endclass : spi_device_reg_intr_state
 
-// Class: hmac_reg_intr_enable
-class hmac_reg_intr_enable extends dv_base_reg;
+// Class: spi_device_reg_intr_enable
+class spi_device_reg_intr_enable extends dv_base_reg;
   // fields
-  rand dv_base_reg_field hmac_done;
-  rand dv_base_reg_field fifo_full;
+  rand dv_base_reg_field rxf;
+  rand dv_base_reg_field rxlvl;
+  rand dv_base_reg_field txlvl;
+  rand dv_base_reg_field rxerr;
 
-  `uvm_object_utils(hmac_reg_intr_enable)
+  `uvm_object_utils(spi_device_reg_intr_enable)
 
-  function new(string       name = "hmac_reg_intr_enable",
+  function new(string       name = "spi_device_reg_intr_enable",
                int unsigned n_bits = 32,
                int          has_coverage = UVM_NO_COVERAGE);
     super.new(name, n_bits, has_coverage);
@@ -241,8 +267,8 @@
 
   virtual function void build();
     // create fields
-    hmac_done = dv_base_reg_field::type_id::create("hmac_done");
-    hmac_done.configure(
+    rxf = dv_base_reg_field::type_id::create("rxf");
+    rxf.configure(
       .parent(this),
       .size(1),
       .lsb_pos(0),
@@ -252,8 +278,8 @@
       .has_reset(1),
       .is_rand(1),
       .individually_accessible(1));
-    fifo_full = dv_base_reg_field::type_id::create("fifo_full");
-    fifo_full.configure(
+    rxlvl = dv_base_reg_field::type_id::create("rxlvl");
+    rxlvl.configure(
       .parent(this),
       .size(1),
       .lsb_pos(1),
@@ -263,105 +289,19 @@
       .has_reset(1),
       .is_rand(1),
       .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_intr_enable
-
-// Class: hmac_reg_intr_test
-class hmac_reg_intr_test extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field hmac_done;
-  rand dv_base_reg_field fifo_full;
-
-  `uvm_object_utils(hmac_reg_intr_test)
-
-  function new(string       name = "hmac_reg_intr_test",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    hmac_done = dv_base_reg_field::type_id::create("hmac_done");
-    hmac_done.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(0),
-      .access("WO"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    fifo_full = dv_base_reg_field::type_id::create("fifo_full");
-    fifo_full.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(1),
-      .access("WO"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_intr_test
-
-// Class: hmac_reg_cfg
-class hmac_reg_cfg extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field hmac_en;
-  rand dv_base_reg_field sha_en;
-  rand dv_base_reg_field endian_swap;
-  rand dv_base_reg_field digest_swap;
-
-  `uvm_object_utils(hmac_reg_cfg)
-
-  function new(string       name = "hmac_reg_cfg",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    hmac_en = dv_base_reg_field::type_id::create("hmac_en");
-    hmac_en.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    sha_en = dv_base_reg_field::type_id::create("sha_en");
-    sha_en.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(1),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    endian_swap = dv_base_reg_field::type_id::create("endian_swap");
-    endian_swap.configure(
+    txlvl = dv_base_reg_field::type_id::create("txlvl");
+    txlvl.configure(
       .parent(this),
       .size(1),
       .lsb_pos(2),
       .access("RW"),
       .volatile(0),
-      .reset(1),
+      .reset(0),
       .has_reset(1),
       .is_rand(1),
       .individually_accessible(1));
-    digest_swap = dv_base_reg_field::type_id::create("digest_swap");
-    digest_swap.configure(
+    rxerr = dv_base_reg_field::type_id::create("rxerr");
+    rxerr.configure(
       .parent(this),
       .size(1),
       .lsb_pos(3),
@@ -373,17 +313,19 @@
       .individually_accessible(1));
   endfunction : build
 
-endclass : hmac_reg_cfg
+endclass : spi_device_reg_intr_enable
 
-// Class: hmac_reg_cmd
-class hmac_reg_cmd extends dv_base_reg;
+// Class: spi_device_reg_intr_test
+class spi_device_reg_intr_test extends dv_base_reg;
   // fields
-  rand dv_base_reg_field hash_start;
-  rand dv_base_reg_field hash_process;
+  rand dv_base_reg_field rxf;
+  rand dv_base_reg_field rxlvl;
+  rand dv_base_reg_field txlvl;
+  rand dv_base_reg_field rxerr;
 
-  `uvm_object_utils(hmac_reg_cmd)
+  `uvm_object_utils(spi_device_reg_intr_test)
 
-  function new(string       name = "hmac_reg_cmd",
+  function new(string       name = "spi_device_reg_intr_test",
                int unsigned n_bits = 32,
                int          has_coverage = UVM_NO_COVERAGE);
     super.new(name, n_bits, has_coverage);
@@ -391,23 +333,45 @@
 
   virtual function void build();
     // create fields
-    hash_start = dv_base_reg_field::type_id::create("hash_start");
-    hash_start.configure(
+    rxf = dv_base_reg_field::type_id::create("rxf");
+    rxf.configure(
       .parent(this),
       .size(1),
       .lsb_pos(0),
-      .access("W1C"),
+      .access("WO"),
       .volatile(0),
       .reset(0),
       .has_reset(1),
       .is_rand(1),
       .individually_accessible(1));
-    hash_process = dv_base_reg_field::type_id::create("hash_process");
-    hash_process.configure(
+    rxlvl = dv_base_reg_field::type_id::create("rxlvl");
+    rxlvl.configure(
       .parent(this),
       .size(1),
       .lsb_pos(1),
-      .access("W1C"),
+      .access("WO"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    txlvl = dv_base_reg_field::type_id::create("txlvl");
+    txlvl.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(2),
+      .access("WO"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    rxerr = dv_base_reg_field::type_id::create("rxerr");
+    rxerr.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(3),
+      .access("WO"),
       .volatile(0),
       .reset(0),
       .has_reset(1),
@@ -415,18 +379,19 @@
       .individually_accessible(1));
   endfunction : build
 
-endclass : hmac_reg_cmd
+endclass : spi_device_reg_intr_test
 
-// Class: hmac_reg_status
-class hmac_reg_status extends dv_base_reg;
+// Class: spi_device_reg_control
+class spi_device_reg_control extends dv_base_reg;
   // fields
-  rand dv_base_reg_field fifo_empty;
-  rand dv_base_reg_field fifo_full;
-  rand dv_base_reg_field fifo_depth;
+  rand dv_base_reg_field abort;
+  rand dv_base_reg_field mode;
+  rand dv_base_reg_field rst_txfifo;
+  rand dv_base_reg_field rst_rxfifo;
 
-  `uvm_object_utils(hmac_reg_status)
+  `uvm_object_utils(spi_device_reg_control)
 
-  function new(string       name = "hmac_reg_status",
+  function new(string       name = "spi_device_reg_control",
                int unsigned n_bits = 32,
                int          has_coverage = UVM_NO_COVERAGE);
     super.new(name, n_bits, has_coverage);
@@ -434,8 +399,237 @@
 
   virtual function void build();
     // create fields
-    fifo_empty = dv_base_reg_field::type_id::create("fifo_empty");
-    fifo_empty.configure(
+    abort = dv_base_reg_field::type_id::create("abort");
+    abort.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    mode = dv_base_reg_field::type_id::create("mode");
+    mode.configure(
+      .parent(this),
+      .size(2),
+      .lsb_pos(4),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    rst_txfifo = dv_base_reg_field::type_id::create("rst_txfifo");
+    rst_txfifo.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(16),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    rst_rxfifo = dv_base_reg_field::type_id::create("rst_rxfifo");
+    rst_rxfifo.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(17),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : spi_device_reg_control
+
+// Class: spi_device_reg_cfg
+class spi_device_reg_cfg extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field cpol;
+  rand dv_base_reg_field cpha;
+  rand dv_base_reg_field tx_order;
+  rand dv_base_reg_field rx_order;
+  rand dv_base_reg_field timer_v;
+
+  `uvm_object_utils(spi_device_reg_cfg)
+
+  function new(string       name = "spi_device_reg_cfg",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    cpol = dv_base_reg_field::type_id::create("cpol");
+    cpol.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    cpha = dv_base_reg_field::type_id::create("cpha");
+    cpha.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(1),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    tx_order = dv_base_reg_field::type_id::create("tx_order");
+    tx_order.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(2),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    rx_order = dv_base_reg_field::type_id::create("rx_order");
+    rx_order.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(3),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    timer_v = dv_base_reg_field::type_id::create("timer_v");
+    timer_v.configure(
+      .parent(this),
+      .size(8),
+      .lsb_pos(8),
+      .access("RW"),
+      .volatile(0),
+      .reset(127),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : spi_device_reg_cfg
+
+// Class: spi_device_reg_fifo_level
+class spi_device_reg_fifo_level extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field rxlvl;
+  rand dv_base_reg_field txlvl;
+
+  `uvm_object_utils(spi_device_reg_fifo_level)
+
+  function new(string       name = "spi_device_reg_fifo_level",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    rxlvl = dv_base_reg_field::type_id::create("rxlvl");
+    rxlvl.configure(
+      .parent(this),
+      .size(16),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(128),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    txlvl = dv_base_reg_field::type_id::create("txlvl");
+    txlvl.configure(
+      .parent(this),
+      .size(16),
+      .lsb_pos(16),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : spi_device_reg_fifo_level
+
+// Class: spi_device_reg_async_fifo_level
+class spi_device_reg_async_fifo_level extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field rxlvl;
+  rand dv_base_reg_field txlvl;
+
+  `uvm_object_utils(spi_device_reg_async_fifo_level)
+
+  function new(string       name = "spi_device_reg_async_fifo_level",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    rxlvl = dv_base_reg_field::type_id::create("rxlvl");
+    rxlvl.configure(
+      .parent(this),
+      .size(8),
+      .lsb_pos(0),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    txlvl = dv_base_reg_field::type_id::create("txlvl");
+    txlvl.configure(
+      .parent(this),
+      .size(8),
+      .lsb_pos(16),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : spi_device_reg_async_fifo_level
+
+// Class: spi_device_reg_status
+class spi_device_reg_status extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field rxf_full;
+  rand dv_base_reg_field rxf_empty;
+  rand dv_base_reg_field txf_full;
+  rand dv_base_reg_field txf_empty;
+  rand dv_base_reg_field abort_done;
+
+  `uvm_object_utils(spi_device_reg_status)
+
+  function new(string       name = "spi_device_reg_status",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    rxf_full = dv_base_reg_field::type_id::create("rxf_full");
+    rxf_full.configure(
       .parent(this),
       .size(1),
       .lsb_pos(0),
@@ -445,40 +639,63 @@
       .has_reset(1),
       .is_rand(1),
       .individually_accessible(1));
-    fifo_full = dv_base_reg_field::type_id::create("fifo_full");
-    fifo_full.configure(
+    rxf_empty = dv_base_reg_field::type_id::create("rxf_empty");
+    rxf_empty.configure(
       .parent(this),
       .size(1),
       .lsb_pos(1),
       .access("RO"),
       .volatile(1),
+      .reset(1),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    txf_full = dv_base_reg_field::type_id::create("txf_full");
+    txf_full.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(2),
+      .access("RO"),
+      .volatile(1),
       .reset(0),
       .has_reset(1),
       .is_rand(1),
       .individually_accessible(1));
-    fifo_depth = dv_base_reg_field::type_id::create("fifo_depth");
-    fifo_depth.configure(
+    txf_empty = dv_base_reg_field::type_id::create("txf_empty");
+    txf_empty.configure(
       .parent(this),
-      .size(5),
+      .size(1),
+      .lsb_pos(3),
+      .access("RO"),
+      .volatile(1),
+      .reset(1),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    abort_done = dv_base_reg_field::type_id::create("abort_done");
+    abort_done.configure(
+      .parent(this),
+      .size(1),
       .lsb_pos(4),
       .access("RO"),
       .volatile(1),
-      .reset(0),
+      .reset(1),
       .has_reset(1),
       .is_rand(1),
       .individually_accessible(1));
   endfunction : build
 
-endclass : hmac_reg_status
+endclass : spi_device_reg_status
 
-// Class: hmac_reg_wipe_secret
-class hmac_reg_wipe_secret extends dv_base_reg;
+// Class: spi_device_reg_rxf_ptr
+class spi_device_reg_rxf_ptr extends dv_base_reg;
   // fields
-  rand dv_base_reg_field secret;
+  rand dv_base_reg_field rptr;
+  rand dv_base_reg_field wptr;
 
-  `uvm_object_utils(hmac_reg_wipe_secret)
+  `uvm_object_utils(spi_device_reg_rxf_ptr)
 
-  function new(string       name = "hmac_reg_wipe_secret",
+  function new(string       name = "spi_device_reg_rxf_ptr",
                int unsigned n_bits = 32,
                int          has_coverage = UVM_NO_COVERAGE);
     super.new(name, n_bits, has_coverage);
@@ -486,12 +703,65 @@
 
   virtual function void build();
     // create fields
-    secret = dv_base_reg_field::type_id::create("secret");
-    secret.configure(
+    rptr = dv_base_reg_field::type_id::create("rptr");
+    rptr.configure(
       .parent(this),
-      .size(32),
+      .size(16),
       .lsb_pos(0),
-      .access("WO"),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    wptr = dv_base_reg_field::type_id::create("wptr");
+    wptr.configure(
+      .parent(this),
+      .size(16),
+      .lsb_pos(16),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : spi_device_reg_rxf_ptr
+
+// Class: spi_device_reg_txf_ptr
+class spi_device_reg_txf_ptr extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field rptr;
+  rand dv_base_reg_field wptr;
+
+  `uvm_object_utils(spi_device_reg_txf_ptr)
+
+  function new(string       name = "spi_device_reg_txf_ptr",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    rptr = dv_base_reg_field::type_id::create("rptr");
+    rptr.configure(
+      .parent(this),
+      .size(16),
+      .lsb_pos(0),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    wptr = dv_base_reg_field::type_id::create("wptr");
+    wptr.configure(
+      .parent(this),
+      .size(16),
+      .lsb_pos(16),
+      .access("RW"),
       .volatile(0),
       .reset(0),
       .has_reset(1),
@@ -499,16 +769,17 @@
       .individually_accessible(1));
   endfunction : build
 
-endclass : hmac_reg_wipe_secret
+endclass : spi_device_reg_txf_ptr
 
-// Class: hmac_reg_key0
-class hmac_reg_key0 extends dv_base_reg;
+// Class: spi_device_reg_rxf_addr
+class spi_device_reg_rxf_addr extends dv_base_reg;
   // fields
-  rand dv_base_reg_field key0;
+  rand dv_base_reg_field base;
+  rand dv_base_reg_field limit;
 
-  `uvm_object_utils(hmac_reg_key0)
+  `uvm_object_utils(spi_device_reg_rxf_addr)
 
-  function new(string       name = "hmac_reg_key0",
+  function new(string       name = "spi_device_reg_rxf_addr",
                int unsigned n_bits = 32,
                int          has_coverage = UVM_NO_COVERAGE);
     super.new(name, n_bits, has_coverage);
@@ -516,29 +787,41 @@
 
   virtual function void build();
     // create fields
-    key0 = dv_base_reg_field::type_id::create("key0");
-    key0.configure(
+    base = dv_base_reg_field::type_id::create("base");
+    base.configure(
       .parent(this),
-      .size(32),
+      .size(16),
       .lsb_pos(0),
-      .access("WO"),
-      .volatile(1),
+      .access("RW"),
+      .volatile(0),
       .reset(0),
       .has_reset(1),
       .is_rand(1),
       .individually_accessible(1));
+    limit = dv_base_reg_field::type_id::create("limit");
+    limit.configure(
+      .parent(this),
+      .size(16),
+      .lsb_pos(16),
+      .access("RW"),
+      .volatile(0),
+      .reset(508),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
   endfunction : build
 
-endclass : hmac_reg_key0
+endclass : spi_device_reg_rxf_addr
 
-// Class: hmac_reg_key1
-class hmac_reg_key1 extends dv_base_reg;
+// Class: spi_device_reg_txf_addr
+class spi_device_reg_txf_addr extends dv_base_reg;
   // fields
-  rand dv_base_reg_field key1;
+  rand dv_base_reg_field base;
+  rand dv_base_reg_field limit;
 
-  `uvm_object_utils(hmac_reg_key1)
+  `uvm_object_utils(spi_device_reg_txf_addr)
 
-  function new(string       name = "hmac_reg_key1",
+  function new(string       name = "spi_device_reg_txf_addr",
                int unsigned n_bits = 32,
                int          has_coverage = UVM_NO_COVERAGE);
     super.new(name, n_bits, has_coverage);
@@ -546,550 +829,68 @@
 
   virtual function void build();
     // create fields
-    key1 = dv_base_reg_field::type_id::create("key1");
-    key1.configure(
+    base = dv_base_reg_field::type_id::create("base");
+    base.configure(
       .parent(this),
-      .size(32),
+      .size(16),
       .lsb_pos(0),
-      .access("WO"),
-      .volatile(1),
-      .reset(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(512),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    limit = dv_base_reg_field::type_id::create("limit");
+    limit.configure(
+      .parent(this),
+      .size(16),
+      .lsb_pos(16),
+      .access("RW"),
+      .volatile(0),
+      .reset(1020),
       .has_reset(1),
       .is_rand(1),
       .individually_accessible(1));
   endfunction : build
 
-endclass : hmac_reg_key1
+endclass : spi_device_reg_txf_addr
 
-// Class: hmac_reg_key2
-class hmac_reg_key2 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field key2;
+// Class: spi_device_mem_buffer
+class spi_device_mem_buffer extends dv_base_mem;
 
-  `uvm_object_utils(hmac_reg_key2)
+  `uvm_object_utils(spi_device_mem_buffer)
 
-  function new(string       name = "hmac_reg_key2",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    key2 = dv_base_reg_field::type_id::create("key2");
-    key2.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("WO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_key2
-
-// Class: hmac_reg_key3
-class hmac_reg_key3 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field key3;
-
-  `uvm_object_utils(hmac_reg_key3)
-
-  function new(string       name = "hmac_reg_key3",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    key3 = dv_base_reg_field::type_id::create("key3");
-    key3.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("WO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_key3
-
-// Class: hmac_reg_key4
-class hmac_reg_key4 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field key4;
-
-  `uvm_object_utils(hmac_reg_key4)
-
-  function new(string       name = "hmac_reg_key4",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    key4 = dv_base_reg_field::type_id::create("key4");
-    key4.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("WO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_key4
-
-// Class: hmac_reg_key5
-class hmac_reg_key5 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field key5;
-
-  `uvm_object_utils(hmac_reg_key5)
-
-  function new(string       name = "hmac_reg_key5",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    key5 = dv_base_reg_field::type_id::create("key5");
-    key5.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("WO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_key5
-
-// Class: hmac_reg_key6
-class hmac_reg_key6 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field key6;
-
-  `uvm_object_utils(hmac_reg_key6)
-
-  function new(string       name = "hmac_reg_key6",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    key6 = dv_base_reg_field::type_id::create("key6");
-    key6.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("WO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_key6
-
-// Class: hmac_reg_key7
-class hmac_reg_key7 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field key7;
-
-  `uvm_object_utils(hmac_reg_key7)
-
-  function new(string       name = "hmac_reg_key7",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    key7 = dv_base_reg_field::type_id::create("key7");
-    key7.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("WO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_key7
-
-// Class: hmac_reg_digest0
-class hmac_reg_digest0 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field digest0;
-
-  `uvm_object_utils(hmac_reg_digest0)
-
-  function new(string       name = "hmac_reg_digest0",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    digest0 = dv_base_reg_field::type_id::create("digest0");
-    digest0.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_digest0
-
-// Class: hmac_reg_digest1
-class hmac_reg_digest1 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field digest1;
-
-  `uvm_object_utils(hmac_reg_digest1)
-
-  function new(string       name = "hmac_reg_digest1",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    digest1 = dv_base_reg_field::type_id::create("digest1");
-    digest1.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_digest1
-
-// Class: hmac_reg_digest2
-class hmac_reg_digest2 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field digest2;
-
-  `uvm_object_utils(hmac_reg_digest2)
-
-  function new(string       name = "hmac_reg_digest2",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    digest2 = dv_base_reg_field::type_id::create("digest2");
-    digest2.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_digest2
-
-// Class: hmac_reg_digest3
-class hmac_reg_digest3 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field digest3;
-
-  `uvm_object_utils(hmac_reg_digest3)
-
-  function new(string       name = "hmac_reg_digest3",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    digest3 = dv_base_reg_field::type_id::create("digest3");
-    digest3.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_digest3
-
-// Class: hmac_reg_digest4
-class hmac_reg_digest4 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field digest4;
-
-  `uvm_object_utils(hmac_reg_digest4)
-
-  function new(string       name = "hmac_reg_digest4",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    digest4 = dv_base_reg_field::type_id::create("digest4");
-    digest4.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_digest4
-
-// Class: hmac_reg_digest5
-class hmac_reg_digest5 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field digest5;
-
-  `uvm_object_utils(hmac_reg_digest5)
-
-  function new(string       name = "hmac_reg_digest5",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    digest5 = dv_base_reg_field::type_id::create("digest5");
-    digest5.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_digest5
-
-// Class: hmac_reg_digest6
-class hmac_reg_digest6 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field digest6;
-
-  `uvm_object_utils(hmac_reg_digest6)
-
-  function new(string       name = "hmac_reg_digest6",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    digest6 = dv_base_reg_field::type_id::create("digest6");
-    digest6.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_digest6
-
-// Class: hmac_reg_digest7
-class hmac_reg_digest7 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field digest7;
-
-  `uvm_object_utils(hmac_reg_digest7)
-
-  function new(string       name = "hmac_reg_digest7",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    digest7 = dv_base_reg_field::type_id::create("digest7");
-    digest7.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_digest7
-
-// Class: hmac_reg_msg_length_lower
-class hmac_reg_msg_length_lower extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field v;
-
-  `uvm_object_utils(hmac_reg_msg_length_lower)
-
-  function new(string       name = "hmac_reg_msg_length_lower",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    v = dv_base_reg_field::type_id::create("v");
-    v.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_msg_length_lower
-
-// Class: hmac_reg_msg_length_upper
-class hmac_reg_msg_length_upper extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field v;
-
-  `uvm_object_utils(hmac_reg_msg_length_upper)
-
-  function new(string       name = "hmac_reg_msg_length_upper",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    v = dv_base_reg_field::type_id::create("v");
-    v.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : hmac_reg_msg_length_upper
-
-// Class: hmac_mem_msg_fifo
-class hmac_mem_msg_fifo extends dv_base_mem;
-
-  `uvm_object_utils(hmac_mem_msg_fifo)
-
-  function new(string           name = "hmac_mem_msg_fifo",
+  function new(string           name = "spi_device_mem_buffer",
                longint unsigned size = 512,
                int unsigned     n_bits = 32,
-               string           access = "RW"/* TODO:"WO"*/,
+               string           access = "RW"/* TODO:"RW"*/,
                int              has_coverage = UVM_NO_COVERAGE);
     super.new(name, size, n_bits, access, has_coverage);
   endfunction : new
 
-endclass : hmac_mem_msg_fifo
+endclass : spi_device_mem_buffer
 
-// Class: hmac_reg_block
-class hmac_reg_block extends dv_base_reg_block;
+// Class: spi_device_reg_block
+class spi_device_reg_block extends dv_base_reg_block;
   // registers
-  rand hmac_reg_intr_state intr_state;
-  rand hmac_reg_intr_enable intr_enable;
-  rand hmac_reg_intr_test intr_test;
-  rand hmac_reg_cfg cfg;
-  rand hmac_reg_cmd cmd;
-  rand hmac_reg_status status;
-  rand hmac_reg_wipe_secret wipe_secret;
-  rand hmac_reg_key0 key0;
-  rand hmac_reg_key1 key1;
-  rand hmac_reg_key2 key2;
-  rand hmac_reg_key3 key3;
-  rand hmac_reg_key4 key4;
-  rand hmac_reg_key5 key5;
-  rand hmac_reg_key6 key6;
-  rand hmac_reg_key7 key7;
-  rand hmac_reg_digest0 digest0;
-  rand hmac_reg_digest1 digest1;
-  rand hmac_reg_digest2 digest2;
-  rand hmac_reg_digest3 digest3;
-  rand hmac_reg_digest4 digest4;
-  rand hmac_reg_digest5 digest5;
-  rand hmac_reg_digest6 digest6;
-  rand hmac_reg_digest7 digest7;
-  rand hmac_reg_msg_length_lower msg_length_lower;
-  rand hmac_reg_msg_length_upper msg_length_upper;
+  rand spi_device_reg_intr_state intr_state;
+  rand spi_device_reg_intr_enable intr_enable;
+  rand spi_device_reg_intr_test intr_test;
+  rand spi_device_reg_control control;
+  rand spi_device_reg_cfg cfg;
+  rand spi_device_reg_fifo_level fifo_level;
+  rand spi_device_reg_async_fifo_level async_fifo_level;
+  rand spi_device_reg_status status;
+  rand spi_device_reg_rxf_ptr rxf_ptr;
+  rand spi_device_reg_txf_ptr txf_ptr;
+  rand spi_device_reg_rxf_addr rxf_addr;
+  rand spi_device_reg_txf_addr txf_addr;
   // memories
-  rand hmac_mem_msg_fifo msg_fifo;
+  rand spi_device_mem_buffer buffer;
 
-  `uvm_object_utils(hmac_reg_block)
+  `uvm_object_utils(spi_device_reg_block)
 
-  function new(string name = "hmac_reg_block",
+  function new(string name = "spi_device_reg_block",
                int    has_coverage = UVM_NO_COVERAGE);
     super.new(name, has_coverage);
   endfunction : new
@@ -1102,793 +903,88 @@
                                   .endian(UVM_LITTLE_ENDIAN));
 
     // create registers
-    intr_state = hmac_reg_intr_state::type_id::create("intr_state");
+    intr_state = spi_device_reg_intr_state::type_id::create("intr_state");
     intr_state.configure(.blk_parent(this));
     intr_state.build();
     default_map.add_reg(.rg(intr_state),
                         .offset(32'h0),
                         .rights("RW"));
-    intr_enable = hmac_reg_intr_enable::type_id::create("intr_enable");
+    intr_enable = spi_device_reg_intr_enable::type_id::create("intr_enable");
     intr_enable.configure(.blk_parent(this));
     intr_enable.build();
     default_map.add_reg(.rg(intr_enable),
                         .offset(32'h4),
                         .rights("RW"));
-    intr_test = hmac_reg_intr_test::type_id::create("intr_test");
+    intr_test = spi_device_reg_intr_test::type_id::create("intr_test");
     intr_test.configure(.blk_parent(this));
     intr_test.build();
     default_map.add_reg(.rg(intr_test),
                         .offset(32'h8),
                         .rights("WO"));
-    cfg = hmac_reg_cfg::type_id::create("cfg");
+    control = spi_device_reg_control::type_id::create("control");
+    control.configure(.blk_parent(this));
+    control.build();
+    default_map.add_reg(.rg(control),
+                        .offset(32'hc),
+                        .rights("RW"));
+    cfg = spi_device_reg_cfg::type_id::create("cfg");
     cfg.configure(.blk_parent(this));
     cfg.build();
     default_map.add_reg(.rg(cfg),
-                        .offset(32'hc),
-                        .rights("RW"));
-    cmd = hmac_reg_cmd::type_id::create("cmd");
-    cmd.configure(.blk_parent(this));
-    cmd.build();
-    default_map.add_reg(.rg(cmd),
                         .offset(32'h10),
                         .rights("RW"));
-    status = hmac_reg_status::type_id::create("status");
+    fifo_level = spi_device_reg_fifo_level::type_id::create("fifo_level");
+    fifo_level.configure(.blk_parent(this));
+    fifo_level.build();
+    default_map.add_reg(.rg(fifo_level),
+                        .offset(32'h14),
+                        .rights("RW"));
+    async_fifo_level = spi_device_reg_async_fifo_level::type_id::create("async_fifo_level");
+    async_fifo_level.configure(.blk_parent(this));
+    async_fifo_level.build();
+    default_map.add_reg(.rg(async_fifo_level),
+                        .offset(32'h18),
+                        .rights("RO"));
+    status = spi_device_reg_status::type_id::create("status");
     status.configure(.blk_parent(this));
     status.build();
     default_map.add_reg(.rg(status),
-                        .offset(32'h14),
-                        .rights("RO"));
-    wipe_secret = hmac_reg_wipe_secret::type_id::create("wipe_secret");
-    wipe_secret.configure(.blk_parent(this));
-    wipe_secret.build();
-    default_map.add_reg(.rg(wipe_secret),
-                        .offset(32'h18),
-                        .rights("WO"));
-    key0 = hmac_reg_key0::type_id::create("key0");
-    key0.configure(.blk_parent(this));
-    key0.build();
-    default_map.add_reg(.rg(key0),
                         .offset(32'h1c),
-                        .rights("WO"));
-    key1 = hmac_reg_key1::type_id::create("key1");
-    key1.configure(.blk_parent(this));
-    key1.build();
-    default_map.add_reg(.rg(key1),
+                        .rights("RO"));
+    rxf_ptr = spi_device_reg_rxf_ptr::type_id::create("rxf_ptr");
+    rxf_ptr.configure(.blk_parent(this));
+    rxf_ptr.build();
+    default_map.add_reg(.rg(rxf_ptr),
                         .offset(32'h20),
-                        .rights("WO"));
-    key2 = hmac_reg_key2::type_id::create("key2");
-    key2.configure(.blk_parent(this));
-    key2.build();
-    default_map.add_reg(.rg(key2),
+                        .rights("RW"));
+    txf_ptr = spi_device_reg_txf_ptr::type_id::create("txf_ptr");
+    txf_ptr.configure(.blk_parent(this));
+    txf_ptr.build();
+    default_map.add_reg(.rg(txf_ptr),
                         .offset(32'h24),
-                        .rights("WO"));
-    key3 = hmac_reg_key3::type_id::create("key3");
-    key3.configure(.blk_parent(this));
-    key3.build();
-    default_map.add_reg(.rg(key3),
+                        .rights("RW"));
+    rxf_addr = spi_device_reg_rxf_addr::type_id::create("rxf_addr");
+    rxf_addr.configure(.blk_parent(this));
+    rxf_addr.build();
+    default_map.add_reg(.rg(rxf_addr),
                         .offset(32'h28),
-                        .rights("WO"));
-    key4 = hmac_reg_key4::type_id::create("key4");
-    key4.configure(.blk_parent(this));
-    key4.build();
-    default_map.add_reg(.rg(key4),
+                        .rights("RW"));
+    txf_addr = spi_device_reg_txf_addr::type_id::create("txf_addr");
+    txf_addr.configure(.blk_parent(this));
+    txf_addr.build();
+    default_map.add_reg(.rg(txf_addr),
                         .offset(32'h2c),
-                        .rights("WO"));
-    key5 = hmac_reg_key5::type_id::create("key5");
-    key5.configure(.blk_parent(this));
-    key5.build();
-    default_map.add_reg(.rg(key5),
-                        .offset(32'h30),
-                        .rights("WO"));
-    key6 = hmac_reg_key6::type_id::create("key6");
-    key6.configure(.blk_parent(this));
-    key6.build();
-    default_map.add_reg(.rg(key6),
-                        .offset(32'h34),
-                        .rights("WO"));
-    key7 = hmac_reg_key7::type_id::create("key7");
-    key7.configure(.blk_parent(this));
-    key7.build();
-    default_map.add_reg(.rg(key7),
-                        .offset(32'h38),
-                        .rights("WO"));
-    digest0 = hmac_reg_digest0::type_id::create("digest0");
-    digest0.configure(.blk_parent(this));
-    digest0.build();
-    default_map.add_reg(.rg(digest0),
-                        .offset(32'h3c),
-                        .rights("RO"));
-    digest1 = hmac_reg_digest1::type_id::create("digest1");
-    digest1.configure(.blk_parent(this));
-    digest1.build();
-    default_map.add_reg(.rg(digest1),
-                        .offset(32'h40),
-                        .rights("RO"));
-    digest2 = hmac_reg_digest2::type_id::create("digest2");
-    digest2.configure(.blk_parent(this));
-    digest2.build();
-    default_map.add_reg(.rg(digest2),
-                        .offset(32'h44),
-                        .rights("RO"));
-    digest3 = hmac_reg_digest3::type_id::create("digest3");
-    digest3.configure(.blk_parent(this));
-    digest3.build();
-    default_map.add_reg(.rg(digest3),
-                        .offset(32'h48),
-                        .rights("RO"));
-    digest4 = hmac_reg_digest4::type_id::create("digest4");
-    digest4.configure(.blk_parent(this));
-    digest4.build();
-    default_map.add_reg(.rg(digest4),
-                        .offset(32'h4c),
-                        .rights("RO"));
-    digest5 = hmac_reg_digest5::type_id::create("digest5");
-    digest5.configure(.blk_parent(this));
-    digest5.build();
-    default_map.add_reg(.rg(digest5),
-                        .offset(32'h50),
-                        .rights("RO"));
-    digest6 = hmac_reg_digest6::type_id::create("digest6");
-    digest6.configure(.blk_parent(this));
-    digest6.build();
-    default_map.add_reg(.rg(digest6),
-                        .offset(32'h54),
-                        .rights("RO"));
-    digest7 = hmac_reg_digest7::type_id::create("digest7");
-    digest7.configure(.blk_parent(this));
-    digest7.build();
-    default_map.add_reg(.rg(digest7),
-                        .offset(32'h58),
-                        .rights("RO"));
-    msg_length_lower = hmac_reg_msg_length_lower::type_id::create("msg_length_lower");
-    msg_length_lower.configure(.blk_parent(this));
-    msg_length_lower.build();
-    default_map.add_reg(.rg(msg_length_lower),
-                        .offset(32'h5c),
-                        .rights("RO"));
-    msg_length_upper = hmac_reg_msg_length_upper::type_id::create("msg_length_upper");
-    msg_length_upper.configure(.blk_parent(this));
-    msg_length_upper.build();
-    default_map.add_reg(.rg(msg_length_upper),
-                        .offset(32'h60),
-                        .rights("RO"));
+                        .rights("RW"));
 
     // create memories
-    msg_fifo = hmac_mem_msg_fifo::type_id::create("msg_fifo");
-    msg_fifo.configure(.parent(this));
-    default_map.add_mem(.mem(msg_fifo),
+    buffer = spi_device_mem_buffer::type_id::create("buffer");
+    buffer.configure(.parent(this));
+    default_map.add_mem(.mem(buffer),
                         .offset(32'h800),
-                        .rights("WO"));
-  endfunction : build
-
-endclass : hmac_reg_block
-
-// Block: gpio
-// Class: gpio_reg_intr_state
-class gpio_reg_intr_state extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field gpio;
-
-  `uvm_object_utils(gpio_reg_intr_state)
-
-  function new(string       name = "gpio_reg_intr_state",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    gpio = dv_base_reg_field::type_id::create("gpio");
-    gpio.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("W1C"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : gpio_reg_intr_state
-
-// Class: gpio_reg_intr_enable
-class gpio_reg_intr_enable extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field gpio;
-
-  `uvm_object_utils(gpio_reg_intr_enable)
-
-  function new(string       name = "gpio_reg_intr_enable",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    gpio = dv_base_reg_field::type_id::create("gpio");
-    gpio.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : gpio_reg_intr_enable
-
-// Class: gpio_reg_intr_test
-class gpio_reg_intr_test extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field gpio;
-
-  `uvm_object_utils(gpio_reg_intr_test)
-
-  function new(string       name = "gpio_reg_intr_test",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    gpio = dv_base_reg_field::type_id::create("gpio");
-    gpio.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("WO"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : gpio_reg_intr_test
-
-// Class: gpio_reg_data_in
-class gpio_reg_data_in extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field data_in;
-
-  `uvm_object_utils(gpio_reg_data_in)
-
-  function new(string       name = "gpio_reg_data_in",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    data_in = dv_base_reg_field::type_id::create("data_in");
-    data_in.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : gpio_reg_data_in
-
-// Class: gpio_reg_direct_out
-class gpio_reg_direct_out extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field direct_out;
-
-  `uvm_object_utils(gpio_reg_direct_out)
-
-  function new(string       name = "gpio_reg_direct_out",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    direct_out = dv_base_reg_field::type_id::create("direct_out");
-    direct_out.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : gpio_reg_direct_out
-
-// Class: gpio_reg_masked_out_lower
-class gpio_reg_masked_out_lower extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field data;
-  rand dv_base_reg_field mask;
-
-  `uvm_object_utils(gpio_reg_masked_out_lower)
-
-  function new(string       name = "gpio_reg_masked_out_lower",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    data = dv_base_reg_field::type_id::create("data");
-    data.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    mask = dv_base_reg_field::type_id::create("mask");
-    mask.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(16),
-      .access("WO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : gpio_reg_masked_out_lower
-
-// Class: gpio_reg_masked_out_upper
-class gpio_reg_masked_out_upper extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field data;
-  rand dv_base_reg_field mask;
-
-  `uvm_object_utils(gpio_reg_masked_out_upper)
-
-  function new(string       name = "gpio_reg_masked_out_upper",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    data = dv_base_reg_field::type_id::create("data");
-    data.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    mask = dv_base_reg_field::type_id::create("mask");
-    mask.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(16),
-      .access("WO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : gpio_reg_masked_out_upper
-
-// Class: gpio_reg_direct_oe
-class gpio_reg_direct_oe extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field direct_oe;
-
-  `uvm_object_utils(gpio_reg_direct_oe)
-
-  function new(string       name = "gpio_reg_direct_oe",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    direct_oe = dv_base_reg_field::type_id::create("direct_oe");
-    direct_oe.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : gpio_reg_direct_oe
-
-// Class: gpio_reg_masked_oe_lower
-class gpio_reg_masked_oe_lower extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field data;
-  rand dv_base_reg_field mask;
-
-  `uvm_object_utils(gpio_reg_masked_oe_lower)
-
-  function new(string       name = "gpio_reg_masked_oe_lower",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    data = dv_base_reg_field::type_id::create("data");
-    data.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    mask = dv_base_reg_field::type_id::create("mask");
-    mask.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(16),
-      .access("RW"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : gpio_reg_masked_oe_lower
-
-// Class: gpio_reg_masked_oe_upper
-class gpio_reg_masked_oe_upper extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field data;
-  rand dv_base_reg_field mask;
-
-  `uvm_object_utils(gpio_reg_masked_oe_upper)
-
-  function new(string       name = "gpio_reg_masked_oe_upper",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    data = dv_base_reg_field::type_id::create("data");
-    data.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    mask = dv_base_reg_field::type_id::create("mask");
-    mask.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(16),
-      .access("RW"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : gpio_reg_masked_oe_upper
-
-// Class: gpio_reg_intr_ctrl_en_rising
-class gpio_reg_intr_ctrl_en_rising extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field intr_ctrl_en_rising;
-
-  `uvm_object_utils(gpio_reg_intr_ctrl_en_rising)
-
-  function new(string       name = "gpio_reg_intr_ctrl_en_rising",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    intr_ctrl_en_rising = dv_base_reg_field::type_id::create("intr_ctrl_en_rising");
-    intr_ctrl_en_rising.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : gpio_reg_intr_ctrl_en_rising
-
-// Class: gpio_reg_intr_ctrl_en_falling
-class gpio_reg_intr_ctrl_en_falling extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field intr_ctrl_en_falling;
-
-  `uvm_object_utils(gpio_reg_intr_ctrl_en_falling)
-
-  function new(string       name = "gpio_reg_intr_ctrl_en_falling",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    intr_ctrl_en_falling = dv_base_reg_field::type_id::create("intr_ctrl_en_falling");
-    intr_ctrl_en_falling.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : gpio_reg_intr_ctrl_en_falling
-
-// Class: gpio_reg_intr_ctrl_en_lvlhigh
-class gpio_reg_intr_ctrl_en_lvlhigh extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field intr_ctrl_en_lvlhigh;
-
-  `uvm_object_utils(gpio_reg_intr_ctrl_en_lvlhigh)
-
-  function new(string       name = "gpio_reg_intr_ctrl_en_lvlhigh",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    intr_ctrl_en_lvlhigh = dv_base_reg_field::type_id::create("intr_ctrl_en_lvlhigh");
-    intr_ctrl_en_lvlhigh.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : gpio_reg_intr_ctrl_en_lvlhigh
-
-// Class: gpio_reg_intr_ctrl_en_lvllow
-class gpio_reg_intr_ctrl_en_lvllow extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field intr_ctrl_en_lvllow;
-
-  `uvm_object_utils(gpio_reg_intr_ctrl_en_lvllow)
-
-  function new(string       name = "gpio_reg_intr_ctrl_en_lvllow",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    intr_ctrl_en_lvllow = dv_base_reg_field::type_id::create("intr_ctrl_en_lvllow");
-    intr_ctrl_en_lvllow.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : gpio_reg_intr_ctrl_en_lvllow
-
-// Class: gpio_reg_ctrl_en_input_filter
-class gpio_reg_ctrl_en_input_filter extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field ctrl_en_input_filter;
-
-  `uvm_object_utils(gpio_reg_ctrl_en_input_filter)
-
-  function new(string       name = "gpio_reg_ctrl_en_input_filter",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    ctrl_en_input_filter = dv_base_reg_field::type_id::create("ctrl_en_input_filter");
-    ctrl_en_input_filter.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : gpio_reg_ctrl_en_input_filter
-
-// Class: gpio_reg_block
-class gpio_reg_block extends dv_base_reg_block;
-  // registers
-  rand gpio_reg_intr_state intr_state;
-  rand gpio_reg_intr_enable intr_enable;
-  rand gpio_reg_intr_test intr_test;
-  rand gpio_reg_data_in data_in;
-  rand gpio_reg_direct_out direct_out;
-  rand gpio_reg_masked_out_lower masked_out_lower;
-  rand gpio_reg_masked_out_upper masked_out_upper;
-  rand gpio_reg_direct_oe direct_oe;
-  rand gpio_reg_masked_oe_lower masked_oe_lower;
-  rand gpio_reg_masked_oe_upper masked_oe_upper;
-  rand gpio_reg_intr_ctrl_en_rising intr_ctrl_en_rising;
-  rand gpio_reg_intr_ctrl_en_falling intr_ctrl_en_falling;
-  rand gpio_reg_intr_ctrl_en_lvlhigh intr_ctrl_en_lvlhigh;
-  rand gpio_reg_intr_ctrl_en_lvllow intr_ctrl_en_lvllow;
-  rand gpio_reg_ctrl_en_input_filter ctrl_en_input_filter;
-
-  `uvm_object_utils(gpio_reg_block)
-
-  function new(string name = "gpio_reg_block",
-               int    has_coverage = UVM_NO_COVERAGE);
-    super.new(name, has_coverage);
-  endfunction : new
-
-  virtual function void build(uvm_reg_addr_t base_addr);
-    // create default map
-    this.default_map = create_map(.name("default_map"),
-                                  .base_addr(base_addr),
-                                  .n_bytes(4),
-                                  .endian(UVM_LITTLE_ENDIAN));
-
-    // create registers
-    intr_state = gpio_reg_intr_state::type_id::create("intr_state");
-    intr_state.configure(.blk_parent(this));
-    intr_state.build();
-    default_map.add_reg(.rg(intr_state),
-                        .offset(32'h0),
-                        .rights("RW"));
-    intr_enable = gpio_reg_intr_enable::type_id::create("intr_enable");
-    intr_enable.configure(.blk_parent(this));
-    intr_enable.build();
-    default_map.add_reg(.rg(intr_enable),
-                        .offset(32'h4),
-                        .rights("RW"));
-    intr_test = gpio_reg_intr_test::type_id::create("intr_test");
-    intr_test.configure(.blk_parent(this));
-    intr_test.build();
-    default_map.add_reg(.rg(intr_test),
-                        .offset(32'h8),
-                        .rights("WO"));
-    data_in = gpio_reg_data_in::type_id::create("data_in");
-    data_in.configure(.blk_parent(this));
-    data_in.build();
-    default_map.add_reg(.rg(data_in),
-                        .offset(32'hc),
-                        .rights("RO"));
-    direct_out = gpio_reg_direct_out::type_id::create("direct_out");
-    direct_out.configure(.blk_parent(this));
-    direct_out.build();
-    default_map.add_reg(.rg(direct_out),
-                        .offset(32'h10),
-                        .rights("RW"));
-    masked_out_lower = gpio_reg_masked_out_lower::type_id::create("masked_out_lower");
-    masked_out_lower.configure(.blk_parent(this));
-    masked_out_lower.build();
-    default_map.add_reg(.rg(masked_out_lower),
-                        .offset(32'h14),
-                        .rights("RW"));
-    masked_out_upper = gpio_reg_masked_out_upper::type_id::create("masked_out_upper");
-    masked_out_upper.configure(.blk_parent(this));
-    masked_out_upper.build();
-    default_map.add_reg(.rg(masked_out_upper),
-                        .offset(32'h18),
-                        .rights("RW"));
-    direct_oe = gpio_reg_direct_oe::type_id::create("direct_oe");
-    direct_oe.configure(.blk_parent(this));
-    direct_oe.build();
-    default_map.add_reg(.rg(direct_oe),
-                        .offset(32'h1c),
-                        .rights("RW"));
-    masked_oe_lower = gpio_reg_masked_oe_lower::type_id::create("masked_oe_lower");
-    masked_oe_lower.configure(.blk_parent(this));
-    masked_oe_lower.build();
-    default_map.add_reg(.rg(masked_oe_lower),
-                        .offset(32'h20),
-                        .rights("RW"));
-    masked_oe_upper = gpio_reg_masked_oe_upper::type_id::create("masked_oe_upper");
-    masked_oe_upper.configure(.blk_parent(this));
-    masked_oe_upper.build();
-    default_map.add_reg(.rg(masked_oe_upper),
-                        .offset(32'h24),
-                        .rights("RW"));
-    intr_ctrl_en_rising = gpio_reg_intr_ctrl_en_rising::type_id::create("intr_ctrl_en_rising");
-    intr_ctrl_en_rising.configure(.blk_parent(this));
-    intr_ctrl_en_rising.build();
-    default_map.add_reg(.rg(intr_ctrl_en_rising),
-                        .offset(32'h28),
-                        .rights("RW"));
-    intr_ctrl_en_falling = gpio_reg_intr_ctrl_en_falling::type_id::create("intr_ctrl_en_falling");
-    intr_ctrl_en_falling.configure(.blk_parent(this));
-    intr_ctrl_en_falling.build();
-    default_map.add_reg(.rg(intr_ctrl_en_falling),
-                        .offset(32'h2c),
-                        .rights("RW"));
-    intr_ctrl_en_lvlhigh = gpio_reg_intr_ctrl_en_lvlhigh::type_id::create("intr_ctrl_en_lvlhigh");
-    intr_ctrl_en_lvlhigh.configure(.blk_parent(this));
-    intr_ctrl_en_lvlhigh.build();
-    default_map.add_reg(.rg(intr_ctrl_en_lvlhigh),
-                        .offset(32'h30),
-                        .rights("RW"));
-    intr_ctrl_en_lvllow = gpio_reg_intr_ctrl_en_lvllow::type_id::create("intr_ctrl_en_lvllow");
-    intr_ctrl_en_lvllow.configure(.blk_parent(this));
-    intr_ctrl_en_lvllow.build();
-    default_map.add_reg(.rg(intr_ctrl_en_lvllow),
-                        .offset(32'h34),
-                        .rights("RW"));
-    ctrl_en_input_filter = gpio_reg_ctrl_en_input_filter::type_id::create("ctrl_en_input_filter");
-    ctrl_en_input_filter.configure(.blk_parent(this));
-    ctrl_en_input_filter.build();
-    default_map.add_reg(.rg(ctrl_en_input_filter),
-                        .offset(32'h38),
                         .rights("RW"));
   endfunction : build
 
-endclass : gpio_reg_block
+endclass : spi_device_reg_block
 
 // Block: flash_ctrl
 // Class: flash_ctrl_reg_intr_state
@@ -3502,6 +2598,2083 @@
 
 endclass : flash_ctrl_reg_block
 
+// Block: rv_timer
+// Class: rv_timer_reg_ctrl
+class rv_timer_reg_ctrl extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field active0;
+
+  `uvm_object_utils(rv_timer_reg_ctrl)
+
+  function new(string       name = "rv_timer_reg_ctrl",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    active0 = dv_base_reg_field::type_id::create("active0");
+    active0.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : rv_timer_reg_ctrl
+
+// Class: rv_timer_reg_cfg0
+class rv_timer_reg_cfg0 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field prescale;
+  rand dv_base_reg_field step;
+
+  `uvm_object_utils(rv_timer_reg_cfg0)
+
+  function new(string       name = "rv_timer_reg_cfg0",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    prescale = dv_base_reg_field::type_id::create("prescale");
+    prescale.configure(
+      .parent(this),
+      .size(12),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    step = dv_base_reg_field::type_id::create("step");
+    step.configure(
+      .parent(this),
+      .size(8),
+      .lsb_pos(16),
+      .access("RW"),
+      .volatile(0),
+      .reset(1),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : rv_timer_reg_cfg0
+
+// Class: rv_timer_reg_timer_v_lower0
+class rv_timer_reg_timer_v_lower0 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field v;
+
+  `uvm_object_utils(rv_timer_reg_timer_v_lower0)
+
+  function new(string       name = "rv_timer_reg_timer_v_lower0",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    v = dv_base_reg_field::type_id::create("v");
+    v.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : rv_timer_reg_timer_v_lower0
+
+// Class: rv_timer_reg_timer_v_upper0
+class rv_timer_reg_timer_v_upper0 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field v;
+
+  `uvm_object_utils(rv_timer_reg_timer_v_upper0)
+
+  function new(string       name = "rv_timer_reg_timer_v_upper0",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    v = dv_base_reg_field::type_id::create("v");
+    v.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : rv_timer_reg_timer_v_upper0
+
+// Class: rv_timer_reg_compare_lower0_0
+class rv_timer_reg_compare_lower0_0 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field v;
+
+  `uvm_object_utils(rv_timer_reg_compare_lower0_0)
+
+  function new(string       name = "rv_timer_reg_compare_lower0_0",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    v = dv_base_reg_field::type_id::create("v");
+    v.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(4294967295),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : rv_timer_reg_compare_lower0_0
+
+// Class: rv_timer_reg_compare_upper0_0
+class rv_timer_reg_compare_upper0_0 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field v;
+
+  `uvm_object_utils(rv_timer_reg_compare_upper0_0)
+
+  function new(string       name = "rv_timer_reg_compare_upper0_0",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    v = dv_base_reg_field::type_id::create("v");
+    v.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(4294967295),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : rv_timer_reg_compare_upper0_0
+
+// Class: rv_timer_reg_intr_enable0
+class rv_timer_reg_intr_enable0 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field ie0;
+
+  `uvm_object_utils(rv_timer_reg_intr_enable0)
+
+  function new(string       name = "rv_timer_reg_intr_enable0",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    ie0 = dv_base_reg_field::type_id::create("ie0");
+    ie0.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : rv_timer_reg_intr_enable0
+
+// Class: rv_timer_reg_intr_state0
+class rv_timer_reg_intr_state0 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field is0;
+
+  `uvm_object_utils(rv_timer_reg_intr_state0)
+
+  function new(string       name = "rv_timer_reg_intr_state0",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    is0 = dv_base_reg_field::type_id::create("is0");
+    is0.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(0),
+      .access("W1C"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : rv_timer_reg_intr_state0
+
+// Class: rv_timer_reg_intr_test0
+class rv_timer_reg_intr_test0 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field t0;
+
+  `uvm_object_utils(rv_timer_reg_intr_test0)
+
+  function new(string       name = "rv_timer_reg_intr_test0",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    t0 = dv_base_reg_field::type_id::create("t0");
+    t0.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(0),
+      .access("WO"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : rv_timer_reg_intr_test0
+
+// Class: rv_timer_reg_block
+class rv_timer_reg_block extends dv_base_reg_block;
+  // registers
+  rand rv_timer_reg_ctrl ctrl;
+  rand rv_timer_reg_cfg0 cfg0;
+  rand rv_timer_reg_timer_v_lower0 timer_v_lower0;
+  rand rv_timer_reg_timer_v_upper0 timer_v_upper0;
+  rand rv_timer_reg_compare_lower0_0 compare_lower0_0;
+  rand rv_timer_reg_compare_upper0_0 compare_upper0_0;
+  rand rv_timer_reg_intr_enable0 intr_enable0;
+  rand rv_timer_reg_intr_state0 intr_state0;
+  rand rv_timer_reg_intr_test0 intr_test0;
+
+  `uvm_object_utils(rv_timer_reg_block)
+
+  function new(string name = "rv_timer_reg_block",
+               int    has_coverage = UVM_NO_COVERAGE);
+    super.new(name, has_coverage);
+  endfunction : new
+
+  virtual function void build(uvm_reg_addr_t base_addr);
+    // create default map
+    this.default_map = create_map(.name("default_map"),
+                                  .base_addr(base_addr),
+                                  .n_bytes(4),
+                                  .endian(UVM_LITTLE_ENDIAN));
+
+    // create registers
+    ctrl = rv_timer_reg_ctrl::type_id::create("ctrl");
+    ctrl.configure(.blk_parent(this));
+    ctrl.build();
+    default_map.add_reg(.rg(ctrl),
+                        .offset(32'h0),
+                        .rights("RW"));
+    cfg0 = rv_timer_reg_cfg0::type_id::create("cfg0");
+    cfg0.configure(.blk_parent(this));
+    cfg0.build();
+    default_map.add_reg(.rg(cfg0),
+                        .offset(32'h100),
+                        .rights("RW"));
+    timer_v_lower0 = rv_timer_reg_timer_v_lower0::type_id::create("timer_v_lower0");
+    timer_v_lower0.configure(.blk_parent(this));
+    timer_v_lower0.build();
+    default_map.add_reg(.rg(timer_v_lower0),
+                        .offset(32'h104),
+                        .rights("RW"));
+    timer_v_upper0 = rv_timer_reg_timer_v_upper0::type_id::create("timer_v_upper0");
+    timer_v_upper0.configure(.blk_parent(this));
+    timer_v_upper0.build();
+    default_map.add_reg(.rg(timer_v_upper0),
+                        .offset(32'h108),
+                        .rights("RW"));
+    compare_lower0_0 = rv_timer_reg_compare_lower0_0::type_id::create("compare_lower0_0");
+    compare_lower0_0.configure(.blk_parent(this));
+    compare_lower0_0.build();
+    default_map.add_reg(.rg(compare_lower0_0),
+                        .offset(32'h10c),
+                        .rights("RW"));
+    compare_upper0_0 = rv_timer_reg_compare_upper0_0::type_id::create("compare_upper0_0");
+    compare_upper0_0.configure(.blk_parent(this));
+    compare_upper0_0.build();
+    default_map.add_reg(.rg(compare_upper0_0),
+                        .offset(32'h110),
+                        .rights("RW"));
+    intr_enable0 = rv_timer_reg_intr_enable0::type_id::create("intr_enable0");
+    intr_enable0.configure(.blk_parent(this));
+    intr_enable0.build();
+    default_map.add_reg(.rg(intr_enable0),
+                        .offset(32'h114),
+                        .rights("RW"));
+    intr_state0 = rv_timer_reg_intr_state0::type_id::create("intr_state0");
+    intr_state0.configure(.blk_parent(this));
+    intr_state0.build();
+    default_map.add_reg(.rg(intr_state0),
+                        .offset(32'h118),
+                        .rights("RW"));
+    intr_test0 = rv_timer_reg_intr_test0::type_id::create("intr_test0");
+    intr_test0.configure(.blk_parent(this));
+    intr_test0.build();
+    default_map.add_reg(.rg(intr_test0),
+                        .offset(32'h11c),
+                        .rights("WO"));
+  endfunction : build
+
+endclass : rv_timer_reg_block
+
+// Block: gpio
+// Class: gpio_reg_intr_state
+class gpio_reg_intr_state extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field gpio;
+
+  `uvm_object_utils(gpio_reg_intr_state)
+
+  function new(string       name = "gpio_reg_intr_state",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    gpio = dv_base_reg_field::type_id::create("gpio");
+    gpio.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("W1C"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : gpio_reg_intr_state
+
+// Class: gpio_reg_intr_enable
+class gpio_reg_intr_enable extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field gpio;
+
+  `uvm_object_utils(gpio_reg_intr_enable)
+
+  function new(string       name = "gpio_reg_intr_enable",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    gpio = dv_base_reg_field::type_id::create("gpio");
+    gpio.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : gpio_reg_intr_enable
+
+// Class: gpio_reg_intr_test
+class gpio_reg_intr_test extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field gpio;
+
+  `uvm_object_utils(gpio_reg_intr_test)
+
+  function new(string       name = "gpio_reg_intr_test",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    gpio = dv_base_reg_field::type_id::create("gpio");
+    gpio.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("WO"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : gpio_reg_intr_test
+
+// Class: gpio_reg_data_in
+class gpio_reg_data_in extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field data_in;
+
+  `uvm_object_utils(gpio_reg_data_in)
+
+  function new(string       name = "gpio_reg_data_in",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    data_in = dv_base_reg_field::type_id::create("data_in");
+    data_in.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : gpio_reg_data_in
+
+// Class: gpio_reg_direct_out
+class gpio_reg_direct_out extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field direct_out;
+
+  `uvm_object_utils(gpio_reg_direct_out)
+
+  function new(string       name = "gpio_reg_direct_out",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    direct_out = dv_base_reg_field::type_id::create("direct_out");
+    direct_out.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : gpio_reg_direct_out
+
+// Class: gpio_reg_masked_out_lower
+class gpio_reg_masked_out_lower extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field data;
+  rand dv_base_reg_field mask;
+
+  `uvm_object_utils(gpio_reg_masked_out_lower)
+
+  function new(string       name = "gpio_reg_masked_out_lower",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    data = dv_base_reg_field::type_id::create("data");
+    data.configure(
+      .parent(this),
+      .size(16),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    mask = dv_base_reg_field::type_id::create("mask");
+    mask.configure(
+      .parent(this),
+      .size(16),
+      .lsb_pos(16),
+      .access("WO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : gpio_reg_masked_out_lower
+
+// Class: gpio_reg_masked_out_upper
+class gpio_reg_masked_out_upper extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field data;
+  rand dv_base_reg_field mask;
+
+  `uvm_object_utils(gpio_reg_masked_out_upper)
+
+  function new(string       name = "gpio_reg_masked_out_upper",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    data = dv_base_reg_field::type_id::create("data");
+    data.configure(
+      .parent(this),
+      .size(16),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    mask = dv_base_reg_field::type_id::create("mask");
+    mask.configure(
+      .parent(this),
+      .size(16),
+      .lsb_pos(16),
+      .access("WO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : gpio_reg_masked_out_upper
+
+// Class: gpio_reg_direct_oe
+class gpio_reg_direct_oe extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field direct_oe;
+
+  `uvm_object_utils(gpio_reg_direct_oe)
+
+  function new(string       name = "gpio_reg_direct_oe",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    direct_oe = dv_base_reg_field::type_id::create("direct_oe");
+    direct_oe.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : gpio_reg_direct_oe
+
+// Class: gpio_reg_masked_oe_lower
+class gpio_reg_masked_oe_lower extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field data;
+  rand dv_base_reg_field mask;
+
+  `uvm_object_utils(gpio_reg_masked_oe_lower)
+
+  function new(string       name = "gpio_reg_masked_oe_lower",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    data = dv_base_reg_field::type_id::create("data");
+    data.configure(
+      .parent(this),
+      .size(16),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    mask = dv_base_reg_field::type_id::create("mask");
+    mask.configure(
+      .parent(this),
+      .size(16),
+      .lsb_pos(16),
+      .access("RW"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : gpio_reg_masked_oe_lower
+
+// Class: gpio_reg_masked_oe_upper
+class gpio_reg_masked_oe_upper extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field data;
+  rand dv_base_reg_field mask;
+
+  `uvm_object_utils(gpio_reg_masked_oe_upper)
+
+  function new(string       name = "gpio_reg_masked_oe_upper",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    data = dv_base_reg_field::type_id::create("data");
+    data.configure(
+      .parent(this),
+      .size(16),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    mask = dv_base_reg_field::type_id::create("mask");
+    mask.configure(
+      .parent(this),
+      .size(16),
+      .lsb_pos(16),
+      .access("RW"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : gpio_reg_masked_oe_upper
+
+// Class: gpio_reg_intr_ctrl_en_rising
+class gpio_reg_intr_ctrl_en_rising extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field intr_ctrl_en_rising;
+
+  `uvm_object_utils(gpio_reg_intr_ctrl_en_rising)
+
+  function new(string       name = "gpio_reg_intr_ctrl_en_rising",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    intr_ctrl_en_rising = dv_base_reg_field::type_id::create("intr_ctrl_en_rising");
+    intr_ctrl_en_rising.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : gpio_reg_intr_ctrl_en_rising
+
+// Class: gpio_reg_intr_ctrl_en_falling
+class gpio_reg_intr_ctrl_en_falling extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field intr_ctrl_en_falling;
+
+  `uvm_object_utils(gpio_reg_intr_ctrl_en_falling)
+
+  function new(string       name = "gpio_reg_intr_ctrl_en_falling",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    intr_ctrl_en_falling = dv_base_reg_field::type_id::create("intr_ctrl_en_falling");
+    intr_ctrl_en_falling.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : gpio_reg_intr_ctrl_en_falling
+
+// Class: gpio_reg_intr_ctrl_en_lvlhigh
+class gpio_reg_intr_ctrl_en_lvlhigh extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field intr_ctrl_en_lvlhigh;
+
+  `uvm_object_utils(gpio_reg_intr_ctrl_en_lvlhigh)
+
+  function new(string       name = "gpio_reg_intr_ctrl_en_lvlhigh",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    intr_ctrl_en_lvlhigh = dv_base_reg_field::type_id::create("intr_ctrl_en_lvlhigh");
+    intr_ctrl_en_lvlhigh.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : gpio_reg_intr_ctrl_en_lvlhigh
+
+// Class: gpio_reg_intr_ctrl_en_lvllow
+class gpio_reg_intr_ctrl_en_lvllow extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field intr_ctrl_en_lvllow;
+
+  `uvm_object_utils(gpio_reg_intr_ctrl_en_lvllow)
+
+  function new(string       name = "gpio_reg_intr_ctrl_en_lvllow",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    intr_ctrl_en_lvllow = dv_base_reg_field::type_id::create("intr_ctrl_en_lvllow");
+    intr_ctrl_en_lvllow.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : gpio_reg_intr_ctrl_en_lvllow
+
+// Class: gpio_reg_ctrl_en_input_filter
+class gpio_reg_ctrl_en_input_filter extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field ctrl_en_input_filter;
+
+  `uvm_object_utils(gpio_reg_ctrl_en_input_filter)
+
+  function new(string       name = "gpio_reg_ctrl_en_input_filter",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    ctrl_en_input_filter = dv_base_reg_field::type_id::create("ctrl_en_input_filter");
+    ctrl_en_input_filter.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : gpio_reg_ctrl_en_input_filter
+
+// Class: gpio_reg_block
+class gpio_reg_block extends dv_base_reg_block;
+  // registers
+  rand gpio_reg_intr_state intr_state;
+  rand gpio_reg_intr_enable intr_enable;
+  rand gpio_reg_intr_test intr_test;
+  rand gpio_reg_data_in data_in;
+  rand gpio_reg_direct_out direct_out;
+  rand gpio_reg_masked_out_lower masked_out_lower;
+  rand gpio_reg_masked_out_upper masked_out_upper;
+  rand gpio_reg_direct_oe direct_oe;
+  rand gpio_reg_masked_oe_lower masked_oe_lower;
+  rand gpio_reg_masked_oe_upper masked_oe_upper;
+  rand gpio_reg_intr_ctrl_en_rising intr_ctrl_en_rising;
+  rand gpio_reg_intr_ctrl_en_falling intr_ctrl_en_falling;
+  rand gpio_reg_intr_ctrl_en_lvlhigh intr_ctrl_en_lvlhigh;
+  rand gpio_reg_intr_ctrl_en_lvllow intr_ctrl_en_lvllow;
+  rand gpio_reg_ctrl_en_input_filter ctrl_en_input_filter;
+
+  `uvm_object_utils(gpio_reg_block)
+
+  function new(string name = "gpio_reg_block",
+               int    has_coverage = UVM_NO_COVERAGE);
+    super.new(name, has_coverage);
+  endfunction : new
+
+  virtual function void build(uvm_reg_addr_t base_addr);
+    // create default map
+    this.default_map = create_map(.name("default_map"),
+                                  .base_addr(base_addr),
+                                  .n_bytes(4),
+                                  .endian(UVM_LITTLE_ENDIAN));
+
+    // create registers
+    intr_state = gpio_reg_intr_state::type_id::create("intr_state");
+    intr_state.configure(.blk_parent(this));
+    intr_state.build();
+    default_map.add_reg(.rg(intr_state),
+                        .offset(32'h0),
+                        .rights("RW"));
+    intr_enable = gpio_reg_intr_enable::type_id::create("intr_enable");
+    intr_enable.configure(.blk_parent(this));
+    intr_enable.build();
+    default_map.add_reg(.rg(intr_enable),
+                        .offset(32'h4),
+                        .rights("RW"));
+    intr_test = gpio_reg_intr_test::type_id::create("intr_test");
+    intr_test.configure(.blk_parent(this));
+    intr_test.build();
+    default_map.add_reg(.rg(intr_test),
+                        .offset(32'h8),
+                        .rights("WO"));
+    data_in = gpio_reg_data_in::type_id::create("data_in");
+    data_in.configure(.blk_parent(this));
+    data_in.build();
+    default_map.add_reg(.rg(data_in),
+                        .offset(32'hc),
+                        .rights("RO"));
+    direct_out = gpio_reg_direct_out::type_id::create("direct_out");
+    direct_out.configure(.blk_parent(this));
+    direct_out.build();
+    default_map.add_reg(.rg(direct_out),
+                        .offset(32'h10),
+                        .rights("RW"));
+    masked_out_lower = gpio_reg_masked_out_lower::type_id::create("masked_out_lower");
+    masked_out_lower.configure(.blk_parent(this));
+    masked_out_lower.build();
+    default_map.add_reg(.rg(masked_out_lower),
+                        .offset(32'h14),
+                        .rights("RW"));
+    masked_out_upper = gpio_reg_masked_out_upper::type_id::create("masked_out_upper");
+    masked_out_upper.configure(.blk_parent(this));
+    masked_out_upper.build();
+    default_map.add_reg(.rg(masked_out_upper),
+                        .offset(32'h18),
+                        .rights("RW"));
+    direct_oe = gpio_reg_direct_oe::type_id::create("direct_oe");
+    direct_oe.configure(.blk_parent(this));
+    direct_oe.build();
+    default_map.add_reg(.rg(direct_oe),
+                        .offset(32'h1c),
+                        .rights("RW"));
+    masked_oe_lower = gpio_reg_masked_oe_lower::type_id::create("masked_oe_lower");
+    masked_oe_lower.configure(.blk_parent(this));
+    masked_oe_lower.build();
+    default_map.add_reg(.rg(masked_oe_lower),
+                        .offset(32'h20),
+                        .rights("RW"));
+    masked_oe_upper = gpio_reg_masked_oe_upper::type_id::create("masked_oe_upper");
+    masked_oe_upper.configure(.blk_parent(this));
+    masked_oe_upper.build();
+    default_map.add_reg(.rg(masked_oe_upper),
+                        .offset(32'h24),
+                        .rights("RW"));
+    intr_ctrl_en_rising = gpio_reg_intr_ctrl_en_rising::type_id::create("intr_ctrl_en_rising");
+    intr_ctrl_en_rising.configure(.blk_parent(this));
+    intr_ctrl_en_rising.build();
+    default_map.add_reg(.rg(intr_ctrl_en_rising),
+                        .offset(32'h28),
+                        .rights("RW"));
+    intr_ctrl_en_falling = gpio_reg_intr_ctrl_en_falling::type_id::create("intr_ctrl_en_falling");
+    intr_ctrl_en_falling.configure(.blk_parent(this));
+    intr_ctrl_en_falling.build();
+    default_map.add_reg(.rg(intr_ctrl_en_falling),
+                        .offset(32'h2c),
+                        .rights("RW"));
+    intr_ctrl_en_lvlhigh = gpio_reg_intr_ctrl_en_lvlhigh::type_id::create("intr_ctrl_en_lvlhigh");
+    intr_ctrl_en_lvlhigh.configure(.blk_parent(this));
+    intr_ctrl_en_lvlhigh.build();
+    default_map.add_reg(.rg(intr_ctrl_en_lvlhigh),
+                        .offset(32'h30),
+                        .rights("RW"));
+    intr_ctrl_en_lvllow = gpio_reg_intr_ctrl_en_lvllow::type_id::create("intr_ctrl_en_lvllow");
+    intr_ctrl_en_lvllow.configure(.blk_parent(this));
+    intr_ctrl_en_lvllow.build();
+    default_map.add_reg(.rg(intr_ctrl_en_lvllow),
+                        .offset(32'h34),
+                        .rights("RW"));
+    ctrl_en_input_filter = gpio_reg_ctrl_en_input_filter::type_id::create("ctrl_en_input_filter");
+    ctrl_en_input_filter.configure(.blk_parent(this));
+    ctrl_en_input_filter.build();
+    default_map.add_reg(.rg(ctrl_en_input_filter),
+                        .offset(32'h38),
+                        .rights("RW"));
+  endfunction : build
+
+endclass : gpio_reg_block
+
+// Block: hmac
+// Class: hmac_reg_intr_state
+class hmac_reg_intr_state extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field hmac_done;
+  rand dv_base_reg_field fifo_full;
+
+  `uvm_object_utils(hmac_reg_intr_state)
+
+  function new(string       name = "hmac_reg_intr_state",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    hmac_done = dv_base_reg_field::type_id::create("hmac_done");
+    hmac_done.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(0),
+      .access("W1C"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    fifo_full = dv_base_reg_field::type_id::create("fifo_full");
+    fifo_full.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(1),
+      .access("W1C"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_intr_state
+
+// Class: hmac_reg_intr_enable
+class hmac_reg_intr_enable extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field hmac_done;
+  rand dv_base_reg_field fifo_full;
+
+  `uvm_object_utils(hmac_reg_intr_enable)
+
+  function new(string       name = "hmac_reg_intr_enable",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    hmac_done = dv_base_reg_field::type_id::create("hmac_done");
+    hmac_done.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    fifo_full = dv_base_reg_field::type_id::create("fifo_full");
+    fifo_full.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(1),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_intr_enable
+
+// Class: hmac_reg_intr_test
+class hmac_reg_intr_test extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field hmac_done;
+  rand dv_base_reg_field fifo_full;
+
+  `uvm_object_utils(hmac_reg_intr_test)
+
+  function new(string       name = "hmac_reg_intr_test",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    hmac_done = dv_base_reg_field::type_id::create("hmac_done");
+    hmac_done.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(0),
+      .access("WO"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    fifo_full = dv_base_reg_field::type_id::create("fifo_full");
+    fifo_full.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(1),
+      .access("WO"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_intr_test
+
+// Class: hmac_reg_cfg
+class hmac_reg_cfg extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field hmac_en;
+  rand dv_base_reg_field sha_en;
+  rand dv_base_reg_field endian_swap;
+  rand dv_base_reg_field digest_swap;
+
+  `uvm_object_utils(hmac_reg_cfg)
+
+  function new(string       name = "hmac_reg_cfg",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    hmac_en = dv_base_reg_field::type_id::create("hmac_en");
+    hmac_en.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(0),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    sha_en = dv_base_reg_field::type_id::create("sha_en");
+    sha_en.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(1),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    endian_swap = dv_base_reg_field::type_id::create("endian_swap");
+    endian_swap.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(2),
+      .access("RW"),
+      .volatile(0),
+      .reset(1),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    digest_swap = dv_base_reg_field::type_id::create("digest_swap");
+    digest_swap.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(3),
+      .access("RW"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_cfg
+
+// Class: hmac_reg_cmd
+class hmac_reg_cmd extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field hash_start;
+  rand dv_base_reg_field hash_process;
+
+  `uvm_object_utils(hmac_reg_cmd)
+
+  function new(string       name = "hmac_reg_cmd",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    hash_start = dv_base_reg_field::type_id::create("hash_start");
+    hash_start.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(0),
+      .access("W1C"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    hash_process = dv_base_reg_field::type_id::create("hash_process");
+    hash_process.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(1),
+      .access("W1C"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_cmd
+
+// Class: hmac_reg_status
+class hmac_reg_status extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field fifo_empty;
+  rand dv_base_reg_field fifo_full;
+  rand dv_base_reg_field fifo_depth;
+
+  `uvm_object_utils(hmac_reg_status)
+
+  function new(string       name = "hmac_reg_status",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    fifo_empty = dv_base_reg_field::type_id::create("fifo_empty");
+    fifo_empty.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(0),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    fifo_full = dv_base_reg_field::type_id::create("fifo_full");
+    fifo_full.configure(
+      .parent(this),
+      .size(1),
+      .lsb_pos(1),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+    fifo_depth = dv_base_reg_field::type_id::create("fifo_depth");
+    fifo_depth.configure(
+      .parent(this),
+      .size(5),
+      .lsb_pos(4),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_status
+
+// Class: hmac_reg_wipe_secret
+class hmac_reg_wipe_secret extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field secret;
+
+  `uvm_object_utils(hmac_reg_wipe_secret)
+
+  function new(string       name = "hmac_reg_wipe_secret",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    secret = dv_base_reg_field::type_id::create("secret");
+    secret.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("WO"),
+      .volatile(0),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_wipe_secret
+
+// Class: hmac_reg_key0
+class hmac_reg_key0 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field key0;
+
+  `uvm_object_utils(hmac_reg_key0)
+
+  function new(string       name = "hmac_reg_key0",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    key0 = dv_base_reg_field::type_id::create("key0");
+    key0.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("WO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_key0
+
+// Class: hmac_reg_key1
+class hmac_reg_key1 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field key1;
+
+  `uvm_object_utils(hmac_reg_key1)
+
+  function new(string       name = "hmac_reg_key1",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    key1 = dv_base_reg_field::type_id::create("key1");
+    key1.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("WO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_key1
+
+// Class: hmac_reg_key2
+class hmac_reg_key2 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field key2;
+
+  `uvm_object_utils(hmac_reg_key2)
+
+  function new(string       name = "hmac_reg_key2",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    key2 = dv_base_reg_field::type_id::create("key2");
+    key2.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("WO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_key2
+
+// Class: hmac_reg_key3
+class hmac_reg_key3 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field key3;
+
+  `uvm_object_utils(hmac_reg_key3)
+
+  function new(string       name = "hmac_reg_key3",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    key3 = dv_base_reg_field::type_id::create("key3");
+    key3.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("WO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_key3
+
+// Class: hmac_reg_key4
+class hmac_reg_key4 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field key4;
+
+  `uvm_object_utils(hmac_reg_key4)
+
+  function new(string       name = "hmac_reg_key4",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    key4 = dv_base_reg_field::type_id::create("key4");
+    key4.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("WO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_key4
+
+// Class: hmac_reg_key5
+class hmac_reg_key5 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field key5;
+
+  `uvm_object_utils(hmac_reg_key5)
+
+  function new(string       name = "hmac_reg_key5",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    key5 = dv_base_reg_field::type_id::create("key5");
+    key5.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("WO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_key5
+
+// Class: hmac_reg_key6
+class hmac_reg_key6 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field key6;
+
+  `uvm_object_utils(hmac_reg_key6)
+
+  function new(string       name = "hmac_reg_key6",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    key6 = dv_base_reg_field::type_id::create("key6");
+    key6.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("WO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_key6
+
+// Class: hmac_reg_key7
+class hmac_reg_key7 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field key7;
+
+  `uvm_object_utils(hmac_reg_key7)
+
+  function new(string       name = "hmac_reg_key7",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    key7 = dv_base_reg_field::type_id::create("key7");
+    key7.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("WO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_key7
+
+// Class: hmac_reg_digest0
+class hmac_reg_digest0 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field digest0;
+
+  `uvm_object_utils(hmac_reg_digest0)
+
+  function new(string       name = "hmac_reg_digest0",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    digest0 = dv_base_reg_field::type_id::create("digest0");
+    digest0.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_digest0
+
+// Class: hmac_reg_digest1
+class hmac_reg_digest1 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field digest1;
+
+  `uvm_object_utils(hmac_reg_digest1)
+
+  function new(string       name = "hmac_reg_digest1",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    digest1 = dv_base_reg_field::type_id::create("digest1");
+    digest1.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_digest1
+
+// Class: hmac_reg_digest2
+class hmac_reg_digest2 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field digest2;
+
+  `uvm_object_utils(hmac_reg_digest2)
+
+  function new(string       name = "hmac_reg_digest2",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    digest2 = dv_base_reg_field::type_id::create("digest2");
+    digest2.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_digest2
+
+// Class: hmac_reg_digest3
+class hmac_reg_digest3 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field digest3;
+
+  `uvm_object_utils(hmac_reg_digest3)
+
+  function new(string       name = "hmac_reg_digest3",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    digest3 = dv_base_reg_field::type_id::create("digest3");
+    digest3.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_digest3
+
+// Class: hmac_reg_digest4
+class hmac_reg_digest4 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field digest4;
+
+  `uvm_object_utils(hmac_reg_digest4)
+
+  function new(string       name = "hmac_reg_digest4",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    digest4 = dv_base_reg_field::type_id::create("digest4");
+    digest4.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_digest4
+
+// Class: hmac_reg_digest5
+class hmac_reg_digest5 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field digest5;
+
+  `uvm_object_utils(hmac_reg_digest5)
+
+  function new(string       name = "hmac_reg_digest5",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    digest5 = dv_base_reg_field::type_id::create("digest5");
+    digest5.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_digest5
+
+// Class: hmac_reg_digest6
+class hmac_reg_digest6 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field digest6;
+
+  `uvm_object_utils(hmac_reg_digest6)
+
+  function new(string       name = "hmac_reg_digest6",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    digest6 = dv_base_reg_field::type_id::create("digest6");
+    digest6.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_digest6
+
+// Class: hmac_reg_digest7
+class hmac_reg_digest7 extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field digest7;
+
+  `uvm_object_utils(hmac_reg_digest7)
+
+  function new(string       name = "hmac_reg_digest7",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    digest7 = dv_base_reg_field::type_id::create("digest7");
+    digest7.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_digest7
+
+// Class: hmac_reg_msg_length_lower
+class hmac_reg_msg_length_lower extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field v;
+
+  `uvm_object_utils(hmac_reg_msg_length_lower)
+
+  function new(string       name = "hmac_reg_msg_length_lower",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    v = dv_base_reg_field::type_id::create("v");
+    v.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_msg_length_lower
+
+// Class: hmac_reg_msg_length_upper
+class hmac_reg_msg_length_upper extends dv_base_reg;
+  // fields
+  rand dv_base_reg_field v;
+
+  `uvm_object_utils(hmac_reg_msg_length_upper)
+
+  function new(string       name = "hmac_reg_msg_length_upper",
+               int unsigned n_bits = 32,
+               int          has_coverage = UVM_NO_COVERAGE);
+    super.new(name, n_bits, has_coverage);
+  endfunction : new
+
+  virtual function void build();
+    // create fields
+    v = dv_base_reg_field::type_id::create("v");
+    v.configure(
+      .parent(this),
+      .size(32),
+      .lsb_pos(0),
+      .access("RO"),
+      .volatile(1),
+      .reset(0),
+      .has_reset(1),
+      .is_rand(1),
+      .individually_accessible(1));
+  endfunction : build
+
+endclass : hmac_reg_msg_length_upper
+
+// Class: hmac_mem_msg_fifo
+class hmac_mem_msg_fifo extends dv_base_mem;
+
+  `uvm_object_utils(hmac_mem_msg_fifo)
+
+  function new(string           name = "hmac_mem_msg_fifo",
+               longint unsigned size = 512,
+               int unsigned     n_bits = 32,
+               string           access = "RW"/* TODO:"WO"*/,
+               int              has_coverage = UVM_NO_COVERAGE);
+    super.new(name, size, n_bits, access, has_coverage);
+  endfunction : new
+
+endclass : hmac_mem_msg_fifo
+
+// Class: hmac_reg_block
+class hmac_reg_block extends dv_base_reg_block;
+  // registers
+  rand hmac_reg_intr_state intr_state;
+  rand hmac_reg_intr_enable intr_enable;
+  rand hmac_reg_intr_test intr_test;
+  rand hmac_reg_cfg cfg;
+  rand hmac_reg_cmd cmd;
+  rand hmac_reg_status status;
+  rand hmac_reg_wipe_secret wipe_secret;
+  rand hmac_reg_key0 key0;
+  rand hmac_reg_key1 key1;
+  rand hmac_reg_key2 key2;
+  rand hmac_reg_key3 key3;
+  rand hmac_reg_key4 key4;
+  rand hmac_reg_key5 key5;
+  rand hmac_reg_key6 key6;
+  rand hmac_reg_key7 key7;
+  rand hmac_reg_digest0 digest0;
+  rand hmac_reg_digest1 digest1;
+  rand hmac_reg_digest2 digest2;
+  rand hmac_reg_digest3 digest3;
+  rand hmac_reg_digest4 digest4;
+  rand hmac_reg_digest5 digest5;
+  rand hmac_reg_digest6 digest6;
+  rand hmac_reg_digest7 digest7;
+  rand hmac_reg_msg_length_lower msg_length_lower;
+  rand hmac_reg_msg_length_upper msg_length_upper;
+  // memories
+  rand hmac_mem_msg_fifo msg_fifo;
+
+  `uvm_object_utils(hmac_reg_block)
+
+  function new(string name = "hmac_reg_block",
+               int    has_coverage = UVM_NO_COVERAGE);
+    super.new(name, has_coverage);
+  endfunction : new
+
+  virtual function void build(uvm_reg_addr_t base_addr);
+    // create default map
+    this.default_map = create_map(.name("default_map"),
+                                  .base_addr(base_addr),
+                                  .n_bytes(4),
+                                  .endian(UVM_LITTLE_ENDIAN));
+
+    // create registers
+    intr_state = hmac_reg_intr_state::type_id::create("intr_state");
+    intr_state.configure(.blk_parent(this));
+    intr_state.build();
+    default_map.add_reg(.rg(intr_state),
+                        .offset(32'h0),
+                        .rights("RW"));
+    intr_enable = hmac_reg_intr_enable::type_id::create("intr_enable");
+    intr_enable.configure(.blk_parent(this));
+    intr_enable.build();
+    default_map.add_reg(.rg(intr_enable),
+                        .offset(32'h4),
+                        .rights("RW"));
+    intr_test = hmac_reg_intr_test::type_id::create("intr_test");
+    intr_test.configure(.blk_parent(this));
+    intr_test.build();
+    default_map.add_reg(.rg(intr_test),
+                        .offset(32'h8),
+                        .rights("WO"));
+    cfg = hmac_reg_cfg::type_id::create("cfg");
+    cfg.configure(.blk_parent(this));
+    cfg.build();
+    default_map.add_reg(.rg(cfg),
+                        .offset(32'hc),
+                        .rights("RW"));
+    cmd = hmac_reg_cmd::type_id::create("cmd");
+    cmd.configure(.blk_parent(this));
+    cmd.build();
+    default_map.add_reg(.rg(cmd),
+                        .offset(32'h10),
+                        .rights("RW"));
+    status = hmac_reg_status::type_id::create("status");
+    status.configure(.blk_parent(this));
+    status.build();
+    default_map.add_reg(.rg(status),
+                        .offset(32'h14),
+                        .rights("RO"));
+    wipe_secret = hmac_reg_wipe_secret::type_id::create("wipe_secret");
+    wipe_secret.configure(.blk_parent(this));
+    wipe_secret.build();
+    default_map.add_reg(.rg(wipe_secret),
+                        .offset(32'h18),
+                        .rights("WO"));
+    key0 = hmac_reg_key0::type_id::create("key0");
+    key0.configure(.blk_parent(this));
+    key0.build();
+    default_map.add_reg(.rg(key0),
+                        .offset(32'h1c),
+                        .rights("WO"));
+    key1 = hmac_reg_key1::type_id::create("key1");
+    key1.configure(.blk_parent(this));
+    key1.build();
+    default_map.add_reg(.rg(key1),
+                        .offset(32'h20),
+                        .rights("WO"));
+    key2 = hmac_reg_key2::type_id::create("key2");
+    key2.configure(.blk_parent(this));
+    key2.build();
+    default_map.add_reg(.rg(key2),
+                        .offset(32'h24),
+                        .rights("WO"));
+    key3 = hmac_reg_key3::type_id::create("key3");
+    key3.configure(.blk_parent(this));
+    key3.build();
+    default_map.add_reg(.rg(key3),
+                        .offset(32'h28),
+                        .rights("WO"));
+    key4 = hmac_reg_key4::type_id::create("key4");
+    key4.configure(.blk_parent(this));
+    key4.build();
+    default_map.add_reg(.rg(key4),
+                        .offset(32'h2c),
+                        .rights("WO"));
+    key5 = hmac_reg_key5::type_id::create("key5");
+    key5.configure(.blk_parent(this));
+    key5.build();
+    default_map.add_reg(.rg(key5),
+                        .offset(32'h30),
+                        .rights("WO"));
+    key6 = hmac_reg_key6::type_id::create("key6");
+    key6.configure(.blk_parent(this));
+    key6.build();
+    default_map.add_reg(.rg(key6),
+                        .offset(32'h34),
+                        .rights("WO"));
+    key7 = hmac_reg_key7::type_id::create("key7");
+    key7.configure(.blk_parent(this));
+    key7.build();
+    default_map.add_reg(.rg(key7),
+                        .offset(32'h38),
+                        .rights("WO"));
+    digest0 = hmac_reg_digest0::type_id::create("digest0");
+    digest0.configure(.blk_parent(this));
+    digest0.build();
+    default_map.add_reg(.rg(digest0),
+                        .offset(32'h3c),
+                        .rights("RO"));
+    digest1 = hmac_reg_digest1::type_id::create("digest1");
+    digest1.configure(.blk_parent(this));
+    digest1.build();
+    default_map.add_reg(.rg(digest1),
+                        .offset(32'h40),
+                        .rights("RO"));
+    digest2 = hmac_reg_digest2::type_id::create("digest2");
+    digest2.configure(.blk_parent(this));
+    digest2.build();
+    default_map.add_reg(.rg(digest2),
+                        .offset(32'h44),
+                        .rights("RO"));
+    digest3 = hmac_reg_digest3::type_id::create("digest3");
+    digest3.configure(.blk_parent(this));
+    digest3.build();
+    default_map.add_reg(.rg(digest3),
+                        .offset(32'h48),
+                        .rights("RO"));
+    digest4 = hmac_reg_digest4::type_id::create("digest4");
+    digest4.configure(.blk_parent(this));
+    digest4.build();
+    default_map.add_reg(.rg(digest4),
+                        .offset(32'h4c),
+                        .rights("RO"));
+    digest5 = hmac_reg_digest5::type_id::create("digest5");
+    digest5.configure(.blk_parent(this));
+    digest5.build();
+    default_map.add_reg(.rg(digest5),
+                        .offset(32'h50),
+                        .rights("RO"));
+    digest6 = hmac_reg_digest6::type_id::create("digest6");
+    digest6.configure(.blk_parent(this));
+    digest6.build();
+    default_map.add_reg(.rg(digest6),
+                        .offset(32'h54),
+                        .rights("RO"));
+    digest7 = hmac_reg_digest7::type_id::create("digest7");
+    digest7.configure(.blk_parent(this));
+    digest7.build();
+    default_map.add_reg(.rg(digest7),
+                        .offset(32'h58),
+                        .rights("RO"));
+    msg_length_lower = hmac_reg_msg_length_lower::type_id::create("msg_length_lower");
+    msg_length_lower.configure(.blk_parent(this));
+    msg_length_lower.build();
+    default_map.add_reg(.rg(msg_length_lower),
+                        .offset(32'h5c),
+                        .rights("RO"));
+    msg_length_upper = hmac_reg_msg_length_upper::type_id::create("msg_length_upper");
+    msg_length_upper.configure(.blk_parent(this));
+    msg_length_upper.build();
+    default_map.add_reg(.rg(msg_length_upper),
+                        .offset(32'h60),
+                        .rights("RO"));
+
+    // create memories
+    msg_fifo = hmac_mem_msg_fifo::type_id::create("msg_fifo");
+    msg_fifo.configure(.parent(this));
+    default_map.add_mem(.mem(msg_fifo),
+                        .offset(32'h800),
+                        .rights("WO"));
+  endfunction : build
+
+endclass : hmac_reg_block
+
 // Block: uart
 // Class: uart_reg_intr_state
 class uart_reg_intr_state extends dv_base_reg;
@@ -4450,1179 +5623,6 @@
 
 endclass : uart_reg_block
 
-// Block: spi_device
-// Class: spi_device_reg_intr_state
-class spi_device_reg_intr_state extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field rxf;
-  rand dv_base_reg_field rxlvl;
-  rand dv_base_reg_field txlvl;
-  rand dv_base_reg_field rxerr;
-
-  `uvm_object_utils(spi_device_reg_intr_state)
-
-  function new(string       name = "spi_device_reg_intr_state",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    rxf = dv_base_reg_field::type_id::create("rxf");
-    rxf.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(0),
-      .access("W1C"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    rxlvl = dv_base_reg_field::type_id::create("rxlvl");
-    rxlvl.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(1),
-      .access("W1C"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    txlvl = dv_base_reg_field::type_id::create("txlvl");
-    txlvl.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(2),
-      .access("W1C"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    rxerr = dv_base_reg_field::type_id::create("rxerr");
-    rxerr.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(3),
-      .access("W1C"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : spi_device_reg_intr_state
-
-// Class: spi_device_reg_intr_enable
-class spi_device_reg_intr_enable extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field rxf;
-  rand dv_base_reg_field rxlvl;
-  rand dv_base_reg_field txlvl;
-  rand dv_base_reg_field rxerr;
-
-  `uvm_object_utils(spi_device_reg_intr_enable)
-
-  function new(string       name = "spi_device_reg_intr_enable",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    rxf = dv_base_reg_field::type_id::create("rxf");
-    rxf.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    rxlvl = dv_base_reg_field::type_id::create("rxlvl");
-    rxlvl.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(1),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    txlvl = dv_base_reg_field::type_id::create("txlvl");
-    txlvl.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(2),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    rxerr = dv_base_reg_field::type_id::create("rxerr");
-    rxerr.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(3),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : spi_device_reg_intr_enable
-
-// Class: spi_device_reg_intr_test
-class spi_device_reg_intr_test extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field rxf;
-  rand dv_base_reg_field rxlvl;
-  rand dv_base_reg_field txlvl;
-  rand dv_base_reg_field rxerr;
-
-  `uvm_object_utils(spi_device_reg_intr_test)
-
-  function new(string       name = "spi_device_reg_intr_test",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    rxf = dv_base_reg_field::type_id::create("rxf");
-    rxf.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(0),
-      .access("WO"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    rxlvl = dv_base_reg_field::type_id::create("rxlvl");
-    rxlvl.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(1),
-      .access("WO"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    txlvl = dv_base_reg_field::type_id::create("txlvl");
-    txlvl.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(2),
-      .access("WO"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    rxerr = dv_base_reg_field::type_id::create("rxerr");
-    rxerr.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(3),
-      .access("WO"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : spi_device_reg_intr_test
-
-// Class: spi_device_reg_control
-class spi_device_reg_control extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field abort;
-  rand dv_base_reg_field mode;
-  rand dv_base_reg_field rst_txfifo;
-  rand dv_base_reg_field rst_rxfifo;
-
-  `uvm_object_utils(spi_device_reg_control)
-
-  function new(string       name = "spi_device_reg_control",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    abort = dv_base_reg_field::type_id::create("abort");
-    abort.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    mode = dv_base_reg_field::type_id::create("mode");
-    mode.configure(
-      .parent(this),
-      .size(2),
-      .lsb_pos(4),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    rst_txfifo = dv_base_reg_field::type_id::create("rst_txfifo");
-    rst_txfifo.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(16),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    rst_rxfifo = dv_base_reg_field::type_id::create("rst_rxfifo");
-    rst_rxfifo.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(17),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : spi_device_reg_control
-
-// Class: spi_device_reg_cfg
-class spi_device_reg_cfg extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field cpol;
-  rand dv_base_reg_field cpha;
-  rand dv_base_reg_field tx_order;
-  rand dv_base_reg_field rx_order;
-  rand dv_base_reg_field timer_v;
-
-  `uvm_object_utils(spi_device_reg_cfg)
-
-  function new(string       name = "spi_device_reg_cfg",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    cpol = dv_base_reg_field::type_id::create("cpol");
-    cpol.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    cpha = dv_base_reg_field::type_id::create("cpha");
-    cpha.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(1),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    tx_order = dv_base_reg_field::type_id::create("tx_order");
-    tx_order.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(2),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    rx_order = dv_base_reg_field::type_id::create("rx_order");
-    rx_order.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(3),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    timer_v = dv_base_reg_field::type_id::create("timer_v");
-    timer_v.configure(
-      .parent(this),
-      .size(8),
-      .lsb_pos(8),
-      .access("RW"),
-      .volatile(0),
-      .reset(127),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : spi_device_reg_cfg
-
-// Class: spi_device_reg_fifo_level
-class spi_device_reg_fifo_level extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field rxlvl;
-  rand dv_base_reg_field txlvl;
-
-  `uvm_object_utils(spi_device_reg_fifo_level)
-
-  function new(string       name = "spi_device_reg_fifo_level",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    rxlvl = dv_base_reg_field::type_id::create("rxlvl");
-    rxlvl.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(128),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    txlvl = dv_base_reg_field::type_id::create("txlvl");
-    txlvl.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(16),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : spi_device_reg_fifo_level
-
-// Class: spi_device_reg_async_fifo_level
-class spi_device_reg_async_fifo_level extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field rxlvl;
-  rand dv_base_reg_field txlvl;
-
-  `uvm_object_utils(spi_device_reg_async_fifo_level)
-
-  function new(string       name = "spi_device_reg_async_fifo_level",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    rxlvl = dv_base_reg_field::type_id::create("rxlvl");
-    rxlvl.configure(
-      .parent(this),
-      .size(8),
-      .lsb_pos(0),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    txlvl = dv_base_reg_field::type_id::create("txlvl");
-    txlvl.configure(
-      .parent(this),
-      .size(8),
-      .lsb_pos(16),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : spi_device_reg_async_fifo_level
-
-// Class: spi_device_reg_status
-class spi_device_reg_status extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field rxf_full;
-  rand dv_base_reg_field rxf_empty;
-  rand dv_base_reg_field txf_full;
-  rand dv_base_reg_field txf_empty;
-  rand dv_base_reg_field abort_done;
-
-  `uvm_object_utils(spi_device_reg_status)
-
-  function new(string       name = "spi_device_reg_status",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    rxf_full = dv_base_reg_field::type_id::create("rxf_full");
-    rxf_full.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(0),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    rxf_empty = dv_base_reg_field::type_id::create("rxf_empty");
-    rxf_empty.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(1),
-      .access("RO"),
-      .volatile(1),
-      .reset(1),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    txf_full = dv_base_reg_field::type_id::create("txf_full");
-    txf_full.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(2),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    txf_empty = dv_base_reg_field::type_id::create("txf_empty");
-    txf_empty.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(3),
-      .access("RO"),
-      .volatile(1),
-      .reset(1),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    abort_done = dv_base_reg_field::type_id::create("abort_done");
-    abort_done.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(4),
-      .access("RO"),
-      .volatile(1),
-      .reset(1),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : spi_device_reg_status
-
-// Class: spi_device_reg_rxf_ptr
-class spi_device_reg_rxf_ptr extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field rptr;
-  rand dv_base_reg_field wptr;
-
-  `uvm_object_utils(spi_device_reg_rxf_ptr)
-
-  function new(string       name = "spi_device_reg_rxf_ptr",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    rptr = dv_base_reg_field::type_id::create("rptr");
-    rptr.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    wptr = dv_base_reg_field::type_id::create("wptr");
-    wptr.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(16),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : spi_device_reg_rxf_ptr
-
-// Class: spi_device_reg_txf_ptr
-class spi_device_reg_txf_ptr extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field rptr;
-  rand dv_base_reg_field wptr;
-
-  `uvm_object_utils(spi_device_reg_txf_ptr)
-
-  function new(string       name = "spi_device_reg_txf_ptr",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    rptr = dv_base_reg_field::type_id::create("rptr");
-    rptr.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(0),
-      .access("RO"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    wptr = dv_base_reg_field::type_id::create("wptr");
-    wptr.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(16),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : spi_device_reg_txf_ptr
-
-// Class: spi_device_reg_rxf_addr
-class spi_device_reg_rxf_addr extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field base;
-  rand dv_base_reg_field limit;
-
-  `uvm_object_utils(spi_device_reg_rxf_addr)
-
-  function new(string       name = "spi_device_reg_rxf_addr",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    base = dv_base_reg_field::type_id::create("base");
-    base.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    limit = dv_base_reg_field::type_id::create("limit");
-    limit.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(16),
-      .access("RW"),
-      .volatile(0),
-      .reset(508),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : spi_device_reg_rxf_addr
-
-// Class: spi_device_reg_txf_addr
-class spi_device_reg_txf_addr extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field base;
-  rand dv_base_reg_field limit;
-
-  `uvm_object_utils(spi_device_reg_txf_addr)
-
-  function new(string       name = "spi_device_reg_txf_addr",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    base = dv_base_reg_field::type_id::create("base");
-    base.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(512),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    limit = dv_base_reg_field::type_id::create("limit");
-    limit.configure(
-      .parent(this),
-      .size(16),
-      .lsb_pos(16),
-      .access("RW"),
-      .volatile(0),
-      .reset(1020),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : spi_device_reg_txf_addr
-
-// Class: spi_device_mem_buffer
-class spi_device_mem_buffer extends dv_base_mem;
-
-  `uvm_object_utils(spi_device_mem_buffer)
-
-  function new(string           name = "spi_device_mem_buffer",
-               longint unsigned size = 512,
-               int unsigned     n_bits = 32,
-               string           access = "RW"/* TODO:"RW"*/,
-               int              has_coverage = UVM_NO_COVERAGE);
-    super.new(name, size, n_bits, access, has_coverage);
-  endfunction : new
-
-endclass : spi_device_mem_buffer
-
-// Class: spi_device_reg_block
-class spi_device_reg_block extends dv_base_reg_block;
-  // registers
-  rand spi_device_reg_intr_state intr_state;
-  rand spi_device_reg_intr_enable intr_enable;
-  rand spi_device_reg_intr_test intr_test;
-  rand spi_device_reg_control control;
-  rand spi_device_reg_cfg cfg;
-  rand spi_device_reg_fifo_level fifo_level;
-  rand spi_device_reg_async_fifo_level async_fifo_level;
-  rand spi_device_reg_status status;
-  rand spi_device_reg_rxf_ptr rxf_ptr;
-  rand spi_device_reg_txf_ptr txf_ptr;
-  rand spi_device_reg_rxf_addr rxf_addr;
-  rand spi_device_reg_txf_addr txf_addr;
-  // memories
-  rand spi_device_mem_buffer buffer;
-
-  `uvm_object_utils(spi_device_reg_block)
-
-  function new(string name = "spi_device_reg_block",
-               int    has_coverage = UVM_NO_COVERAGE);
-    super.new(name, has_coverage);
-  endfunction : new
-
-  virtual function void build(uvm_reg_addr_t base_addr);
-    // create default map
-    this.default_map = create_map(.name("default_map"),
-                                  .base_addr(base_addr),
-                                  .n_bytes(4),
-                                  .endian(UVM_LITTLE_ENDIAN));
-
-    // create registers
-    intr_state = spi_device_reg_intr_state::type_id::create("intr_state");
-    intr_state.configure(.blk_parent(this));
-    intr_state.build();
-    default_map.add_reg(.rg(intr_state),
-                        .offset(32'h0),
-                        .rights("RW"));
-    intr_enable = spi_device_reg_intr_enable::type_id::create("intr_enable");
-    intr_enable.configure(.blk_parent(this));
-    intr_enable.build();
-    default_map.add_reg(.rg(intr_enable),
-                        .offset(32'h4),
-                        .rights("RW"));
-    intr_test = spi_device_reg_intr_test::type_id::create("intr_test");
-    intr_test.configure(.blk_parent(this));
-    intr_test.build();
-    default_map.add_reg(.rg(intr_test),
-                        .offset(32'h8),
-                        .rights("WO"));
-    control = spi_device_reg_control::type_id::create("control");
-    control.configure(.blk_parent(this));
-    control.build();
-    default_map.add_reg(.rg(control),
-                        .offset(32'hc),
-                        .rights("RW"));
-    cfg = spi_device_reg_cfg::type_id::create("cfg");
-    cfg.configure(.blk_parent(this));
-    cfg.build();
-    default_map.add_reg(.rg(cfg),
-                        .offset(32'h10),
-                        .rights("RW"));
-    fifo_level = spi_device_reg_fifo_level::type_id::create("fifo_level");
-    fifo_level.configure(.blk_parent(this));
-    fifo_level.build();
-    default_map.add_reg(.rg(fifo_level),
-                        .offset(32'h14),
-                        .rights("RW"));
-    async_fifo_level = spi_device_reg_async_fifo_level::type_id::create("async_fifo_level");
-    async_fifo_level.configure(.blk_parent(this));
-    async_fifo_level.build();
-    default_map.add_reg(.rg(async_fifo_level),
-                        .offset(32'h18),
-                        .rights("RO"));
-    status = spi_device_reg_status::type_id::create("status");
-    status.configure(.blk_parent(this));
-    status.build();
-    default_map.add_reg(.rg(status),
-                        .offset(32'h1c),
-                        .rights("RO"));
-    rxf_ptr = spi_device_reg_rxf_ptr::type_id::create("rxf_ptr");
-    rxf_ptr.configure(.blk_parent(this));
-    rxf_ptr.build();
-    default_map.add_reg(.rg(rxf_ptr),
-                        .offset(32'h20),
-                        .rights("RW"));
-    txf_ptr = spi_device_reg_txf_ptr::type_id::create("txf_ptr");
-    txf_ptr.configure(.blk_parent(this));
-    txf_ptr.build();
-    default_map.add_reg(.rg(txf_ptr),
-                        .offset(32'h24),
-                        .rights("RW"));
-    rxf_addr = spi_device_reg_rxf_addr::type_id::create("rxf_addr");
-    rxf_addr.configure(.blk_parent(this));
-    rxf_addr.build();
-    default_map.add_reg(.rg(rxf_addr),
-                        .offset(32'h28),
-                        .rights("RW"));
-    txf_addr = spi_device_reg_txf_addr::type_id::create("txf_addr");
-    txf_addr.configure(.blk_parent(this));
-    txf_addr.build();
-    default_map.add_reg(.rg(txf_addr),
-                        .offset(32'h2c),
-                        .rights("RW"));
-
-    // create memories
-    buffer = spi_device_mem_buffer::type_id::create("buffer");
-    buffer.configure(.parent(this));
-    default_map.add_mem(.mem(buffer),
-                        .offset(32'h800),
-                        .rights("RW"));
-  endfunction : build
-
-endclass : spi_device_reg_block
-
-// Block: rv_timer
-// Class: rv_timer_reg_ctrl
-class rv_timer_reg_ctrl extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field active0;
-
-  `uvm_object_utils(rv_timer_reg_ctrl)
-
-  function new(string       name = "rv_timer_reg_ctrl",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    active0 = dv_base_reg_field::type_id::create("active0");
-    active0.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : rv_timer_reg_ctrl
-
-// Class: rv_timer_reg_cfg0
-class rv_timer_reg_cfg0 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field prescale;
-  rand dv_base_reg_field step;
-
-  `uvm_object_utils(rv_timer_reg_cfg0)
-
-  function new(string       name = "rv_timer_reg_cfg0",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    prescale = dv_base_reg_field::type_id::create("prescale");
-    prescale.configure(
-      .parent(this),
-      .size(12),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-    step = dv_base_reg_field::type_id::create("step");
-    step.configure(
-      .parent(this),
-      .size(8),
-      .lsb_pos(16),
-      .access("RW"),
-      .volatile(0),
-      .reset(1),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : rv_timer_reg_cfg0
-
-// Class: rv_timer_reg_timer_v_lower0
-class rv_timer_reg_timer_v_lower0 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field v;
-
-  `uvm_object_utils(rv_timer_reg_timer_v_lower0)
-
-  function new(string       name = "rv_timer_reg_timer_v_lower0",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    v = dv_base_reg_field::type_id::create("v");
-    v.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : rv_timer_reg_timer_v_lower0
-
-// Class: rv_timer_reg_timer_v_upper0
-class rv_timer_reg_timer_v_upper0 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field v;
-
-  `uvm_object_utils(rv_timer_reg_timer_v_upper0)
-
-  function new(string       name = "rv_timer_reg_timer_v_upper0",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    v = dv_base_reg_field::type_id::create("v");
-    v.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : rv_timer_reg_timer_v_upper0
-
-// Class: rv_timer_reg_compare_lower0_0
-class rv_timer_reg_compare_lower0_0 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field v;
-
-  `uvm_object_utils(rv_timer_reg_compare_lower0_0)
-
-  function new(string       name = "rv_timer_reg_compare_lower0_0",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    v = dv_base_reg_field::type_id::create("v");
-    v.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(4294967295),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : rv_timer_reg_compare_lower0_0
-
-// Class: rv_timer_reg_compare_upper0_0
-class rv_timer_reg_compare_upper0_0 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field v;
-
-  `uvm_object_utils(rv_timer_reg_compare_upper0_0)
-
-  function new(string       name = "rv_timer_reg_compare_upper0_0",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    v = dv_base_reg_field::type_id::create("v");
-    v.configure(
-      .parent(this),
-      .size(32),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(4294967295),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : rv_timer_reg_compare_upper0_0
-
-// Class: rv_timer_reg_intr_enable0
-class rv_timer_reg_intr_enable0 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field ie0;
-
-  `uvm_object_utils(rv_timer_reg_intr_enable0)
-
-  function new(string       name = "rv_timer_reg_intr_enable0",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    ie0 = dv_base_reg_field::type_id::create("ie0");
-    ie0.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(0),
-      .access("RW"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : rv_timer_reg_intr_enable0
-
-// Class: rv_timer_reg_intr_state0
-class rv_timer_reg_intr_state0 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field is0;
-
-  `uvm_object_utils(rv_timer_reg_intr_state0)
-
-  function new(string       name = "rv_timer_reg_intr_state0",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    is0 = dv_base_reg_field::type_id::create("is0");
-    is0.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(0),
-      .access("W1C"),
-      .volatile(1),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : rv_timer_reg_intr_state0
-
-// Class: rv_timer_reg_intr_test0
-class rv_timer_reg_intr_test0 extends dv_base_reg;
-  // fields
-  rand dv_base_reg_field t0;
-
-  `uvm_object_utils(rv_timer_reg_intr_test0)
-
-  function new(string       name = "rv_timer_reg_intr_test0",
-               int unsigned n_bits = 32,
-               int          has_coverage = UVM_NO_COVERAGE);
-    super.new(name, n_bits, has_coverage);
-  endfunction : new
-
-  virtual function void build();
-    // create fields
-    t0 = dv_base_reg_field::type_id::create("t0");
-    t0.configure(
-      .parent(this),
-      .size(1),
-      .lsb_pos(0),
-      .access("WO"),
-      .volatile(0),
-      .reset(0),
-      .has_reset(1),
-      .is_rand(1),
-      .individually_accessible(1));
-  endfunction : build
-
-endclass : rv_timer_reg_intr_test0
-
-// Class: rv_timer_reg_block
-class rv_timer_reg_block extends dv_base_reg_block;
-  // registers
-  rand rv_timer_reg_ctrl ctrl;
-  rand rv_timer_reg_cfg0 cfg0;
-  rand rv_timer_reg_timer_v_lower0 timer_v_lower0;
-  rand rv_timer_reg_timer_v_upper0 timer_v_upper0;
-  rand rv_timer_reg_compare_lower0_0 compare_lower0_0;
-  rand rv_timer_reg_compare_upper0_0 compare_upper0_0;
-  rand rv_timer_reg_intr_enable0 intr_enable0;
-  rand rv_timer_reg_intr_state0 intr_state0;
-  rand rv_timer_reg_intr_test0 intr_test0;
-
-  `uvm_object_utils(rv_timer_reg_block)
-
-  function new(string name = "rv_timer_reg_block",
-               int    has_coverage = UVM_NO_COVERAGE);
-    super.new(name, has_coverage);
-  endfunction : new
-
-  virtual function void build(uvm_reg_addr_t base_addr);
-    // create default map
-    this.default_map = create_map(.name("default_map"),
-                                  .base_addr(base_addr),
-                                  .n_bytes(4),
-                                  .endian(UVM_LITTLE_ENDIAN));
-
-    // create registers
-    ctrl = rv_timer_reg_ctrl::type_id::create("ctrl");
-    ctrl.configure(.blk_parent(this));
-    ctrl.build();
-    default_map.add_reg(.rg(ctrl),
-                        .offset(32'h0),
-                        .rights("RW"));
-    cfg0 = rv_timer_reg_cfg0::type_id::create("cfg0");
-    cfg0.configure(.blk_parent(this));
-    cfg0.build();
-    default_map.add_reg(.rg(cfg0),
-                        .offset(32'h100),
-                        .rights("RW"));
-    timer_v_lower0 = rv_timer_reg_timer_v_lower0::type_id::create("timer_v_lower0");
-    timer_v_lower0.configure(.blk_parent(this));
-    timer_v_lower0.build();
-    default_map.add_reg(.rg(timer_v_lower0),
-                        .offset(32'h104),
-                        .rights("RW"));
-    timer_v_upper0 = rv_timer_reg_timer_v_upper0::type_id::create("timer_v_upper0");
-    timer_v_upper0.configure(.blk_parent(this));
-    timer_v_upper0.build();
-    default_map.add_reg(.rg(timer_v_upper0),
-                        .offset(32'h108),
-                        .rights("RW"));
-    compare_lower0_0 = rv_timer_reg_compare_lower0_0::type_id::create("compare_lower0_0");
-    compare_lower0_0.configure(.blk_parent(this));
-    compare_lower0_0.build();
-    default_map.add_reg(.rg(compare_lower0_0),
-                        .offset(32'h10c),
-                        .rights("RW"));
-    compare_upper0_0 = rv_timer_reg_compare_upper0_0::type_id::create("compare_upper0_0");
-    compare_upper0_0.configure(.blk_parent(this));
-    compare_upper0_0.build();
-    default_map.add_reg(.rg(compare_upper0_0),
-                        .offset(32'h110),
-                        .rights("RW"));
-    intr_enable0 = rv_timer_reg_intr_enable0::type_id::create("intr_enable0");
-    intr_enable0.configure(.blk_parent(this));
-    intr_enable0.build();
-    default_map.add_reg(.rg(intr_enable0),
-                        .offset(32'h114),
-                        .rights("RW"));
-    intr_state0 = rv_timer_reg_intr_state0::type_id::create("intr_state0");
-    intr_state0.configure(.blk_parent(this));
-    intr_state0.build();
-    default_map.add_reg(.rg(intr_state0),
-                        .offset(32'h118),
-                        .rights("RW"));
-    intr_test0 = rv_timer_reg_intr_test0::type_id::create("intr_test0");
-    intr_test0.configure(.blk_parent(this));
-    intr_test0.build();
-    default_map.add_reg(.rg(intr_test0),
-                        .offset(32'h11c),
-                        .rights("WO"));
-  endfunction : build
-
-endclass : rv_timer_reg_block
-
 // Block: rv_plic
 // Class: rv_plic_reg_ip0
 class rv_plic_reg_ip0 extends dv_base_reg;
@@ -9753,12 +9753,12 @@
 // Class: chip_reg_block
 class chip_reg_block extends dv_base_reg_block;
   // sub blocks
-  rand hmac_reg_block hmac;
-  rand gpio_reg_block gpio;
-  rand flash_ctrl_reg_block flash_ctrl;
-  rand uart_reg_block uart;
   rand spi_device_reg_block spi_device;
+  rand flash_ctrl_reg_block flash_ctrl;
   rand rv_timer_reg_block rv_timer;
+  rand gpio_reg_block gpio;
+  rand hmac_reg_block hmac;
+  rand uart_reg_block uart;
   rand rv_plic_reg_block rv_plic;
   // memories
   rand chip_mem_rom rom;
@@ -9780,36 +9780,36 @@
                                   .endian(UVM_LITTLE_ENDIAN));
 
     // create sub blocks and add their maps
-    hmac = hmac_reg_block::type_id::create("hmac");
-    hmac.configure(.parent(this));
-    hmac.build(.base_addr(base_addr + 32'h40120000));
-    default_map.add_submap(.child_map(hmac.default_map),
-                           .offset(base_addr + 32'h40120000));
-    gpio = gpio_reg_block::type_id::create("gpio");
-    gpio.configure(.parent(this));
-    gpio.build(.base_addr(base_addr + 32'h40010000));
-    default_map.add_submap(.child_map(gpio.default_map),
-                           .offset(base_addr + 32'h40010000));
-    flash_ctrl = flash_ctrl_reg_block::type_id::create("flash_ctrl");
-    flash_ctrl.configure(.parent(this));
-    flash_ctrl.build(.base_addr(base_addr + 32'h40030000));
-    default_map.add_submap(.child_map(flash_ctrl.default_map),
-                           .offset(base_addr + 32'h40030000));
-    uart = uart_reg_block::type_id::create("uart");
-    uart.configure(.parent(this));
-    uart.build(.base_addr(base_addr + 32'h40000000));
-    default_map.add_submap(.child_map(uart.default_map),
-                           .offset(base_addr + 32'h40000000));
     spi_device = spi_device_reg_block::type_id::create("spi_device");
     spi_device.configure(.parent(this));
     spi_device.build(.base_addr(base_addr + 32'h40020000));
     default_map.add_submap(.child_map(spi_device.default_map),
                            .offset(base_addr + 32'h40020000));
+    flash_ctrl = flash_ctrl_reg_block::type_id::create("flash_ctrl");
+    flash_ctrl.configure(.parent(this));
+    flash_ctrl.build(.base_addr(base_addr + 32'h40030000));
+    default_map.add_submap(.child_map(flash_ctrl.default_map),
+                           .offset(base_addr + 32'h40030000));
     rv_timer = rv_timer_reg_block::type_id::create("rv_timer");
     rv_timer.configure(.parent(this));
     rv_timer.build(.base_addr(base_addr + 32'h40080000));
     default_map.add_submap(.child_map(rv_timer.default_map),
                            .offset(base_addr + 32'h40080000));
+    gpio = gpio_reg_block::type_id::create("gpio");
+    gpio.configure(.parent(this));
+    gpio.build(.base_addr(base_addr + 32'h40010000));
+    default_map.add_submap(.child_map(gpio.default_map),
+                           .offset(base_addr + 32'h40010000));
+    hmac = hmac_reg_block::type_id::create("hmac");
+    hmac.configure(.parent(this));
+    hmac.build(.base_addr(base_addr + 32'h40120000));
+    default_map.add_submap(.child_map(hmac.default_map),
+                           .offset(base_addr + 32'h40120000));
+    uart = uart_reg_block::type_id::create("uart");
+    uart.configure(.parent(this));
+    uart.build(.base_addr(base_addr + 32'h40000000));
+    default_map.add_submap(.child_map(uart.default_map),
+                           .offset(base_addr + 32'h40000000));
     rv_plic = rv_plic_reg_block::type_id::create("rv_plic");
     rv_plic.configure(.parent(this));
     rv_plic.build(.base_addr(base_addr + 32'h40090000));
diff --git a/hw/top_earlgrey/rtl/top_earlgrey.sv b/hw/top_earlgrey/rtl/top_earlgrey.sv
index b67b3b3..a3dbde1 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey.sv
@@ -287,8 +287,12 @@
   logic [FLASH_DW-1:0] flash_host_rdata;
   logic [FLASH_AW-1:0] flash_host_addr;
 
-  tlul_adapter_flash #(
-    .Outstanding(1)
+  tlul_adapter_sram #(
+    .SramAw(FLASH_AW),
+    .SramDw(FLASH_DW),
+    .Outstanding(1),
+    .ByteAccess(0),
+    .ErrOnWrite(1)
   ) tl_adapter_eflash (
     .clk_i,
     .rst_ni     (ndmreset_n),
@@ -296,11 +300,15 @@
     .tl_i       (tl_eflash_d_h2d),
     .tl_o       (tl_eflash_d_d2h),
 
-    .req_o      (flash_host_req),
-    .req_rdy_i  (flash_host_req_rdy),
-    .addr_o     (flash_host_addr),
-    .req_done_i (flash_host_req_done),
-    .rdata_i    (flash_host_rdata)
+    .req_o    (flash_host_req),
+    .gnt_i    (flash_host_req_rdy),
+    .we_o     (),
+    .addr_o   (flash_host_addr),
+    .wdata_o  (),
+    .wmask_o  (),
+    .rdata_i  (flash_host_rdata),
+    .rvalid_i (flash_host_req_done),
+    .rerror_i (2'b00)
   );
 
   flash_phy #(