hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core

CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:systems:chip_earlgrey_cw310_hyperdebug:0.1"
description: "Earl Grey toplevel for the ChipWhisperer CW310 board's hyperdebug variant"
filesets:
  files_rtl_cw310:
    depend:
      - lowrisc:systems:top_earlgrey:0.1
      - lowrisc:systems:top_earlgrey_pkg
      - lowrisc:systems:ast
      - lowrisc:systems:padring
    files:
      - rtl/clkgen_xil7series.sv
      - rtl/usr_access_xil7series.sv
      - rtl/autogen/chip_earlgrey_cw310.sv
    file_type: systemVerilogSource

  files_constraints:
    files:
      - data/clocks.xdc
      # Except for the constraints for the pin-out, this core is exactly the
      # same as lowrisc:systems:chip_earlgrey_cw310.
      - data/pins_cw310_hyperdebug.xdc
      - data/placement.xdc
    file_type: xdc

  files_tcl:
    files:
      - util/vivado_setup_hooks.tcl: { file_type: tclSource }
      # File copied by fusesoc into the workroot (the file containing the
      # .eda.yml file), and referenced from vivado_setup_hooks.tcl
      - util/vivado_hook_synth_design_pre.tcl: { file_type: user, copyto: vivado_hook_synth_design_pre.tcl }
      - util/vivado_hook_write_bitstream_pre.tcl: { file_type: user, copyto: vivado_hook_write_bitstream_pre.tcl }
      - util/vivado_hook_opt_design_post.tcl: { file_type: user, copyto: vivado_hook_opt_design_post.tcl }

  files_ascentlint_waiver:
    depend:
      # common waivers
      - lowrisc:lint:common
      - lowrisc:lint:comportable
    files:
      - lint/chip_earlgrey_cw310.waiver
    file_type: waiver

parameters:
  # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
  # directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
  # --BootRomInitFile=$PWD/build-bin/sw/device/lib/testing/test_rom/test_rom_fpga_cw310.scr.39.vmem
  # XXX: The VMEM file should be added to the sources of the Vivado project to
  # make the Vivado dependency tracking work. However this requires changes to
  # fusesoc first.
  BootRomInitFile:
    datatype: str
    description: Scrambled boot ROM initialization file in 40 bit vmem hex format
    default: "../../../../../build-bin/sw/device/lib/testing/test_rom/test_rom_fpga_cw310.scr.39.vmem"
    paramtype: vlogparam
  OtpCtrlMemInitFile:
    datatype: str
    description: OTP initialization file in vmem hex format
    default: "../../../../../build-bin/sw/device/otp_img/otp_img_fpga_cw310.vmem"
    paramtype: vlogparam
  # For value definition, please see ip/prim/rtl/prim_pkg.sv
  PRIM_DEFAULT_IMPL:
    datatype: str
    paramtype: vlogdefine
    description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
  AST_BYPASS_CLK:
    datatype: bool
    paramtype: vlogdefine
  IBEX_CUSTOM_PMP_RESET_VALUES:
    datatype: bool
    default: true
    paramtype: vlogdefine

targets:
  default: &default_target
    filesets:
      - files_rtl_cw310
      - files_ascentlint_waiver
    toplevel: chip_earlgrey_cw310
    parameters:
      - IBEX_CUSTOM_PMP_RESET_VALUES
      - AST_BYPASS_CLK=true

  synth:
    default_tool: vivado
    filesets:
      - files_rtl_cw310
      - files_constraints
      - files_tcl
    toplevel: chip_earlgrey_cw310
    parameters:
      - BootRomInitFile
      - OtpCtrlMemInitFile
      - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
      - IBEX_CUSTOM_PMP_RESET_VALUES
      - AST_BYPASS_CLK=true
    tools:
      vivado:
        part: "xc7k410tfbg676-1" # CW310 with K410T

  lint:
    <<: *default_target
    default_tool: verilator
    parameters:
      - SYNTHESIS=true
      - AST_BYPASS_CLK=true
    tools:
      verilator:
        mode: lint-only
        verilator_options:
          - "-Wall"