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opensecura / 3p / lowrisc / opentitan / 5a1c665a50f3c920862f9eb4aa4d2c8b8038ab52 / . / hw / ip / entropy_src / rtl / entropy_src_reg_top.sv
blob: a0a02b0a5fb5a178ab68a1e293af2610c8663de8 [file] [log] [blame]
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `reggen`
`include "prim_assert.sv"
module entropy_src_reg_top (
input clk_i,
input rst_ni,
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
// To HW
output entropy_src_reg_pkg::entropy_src_reg2hw_t reg2hw, // Write
input entropy_src_reg_pkg::entropy_src_hw2reg_t hw2reg, // Read
// Integrity check errors
output logic intg_err_o,
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
import entropy_src_reg_pkg::* ;
localparam int AW = 8;
localparam int DW = 32;
localparam int DBW = DW/8; // Byte Width
// register signals
logic reg_we;
logic reg_re;
logic [AW-1:0] reg_addr;
logic [DW-1:0] reg_wdata;
logic [DBW-1:0] reg_be;
logic [DW-1:0] reg_rdata;
logic reg_error;
logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
logic reg_busy;
tlul_pkg::tl_h2d_t tl_reg_h2d;
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
logic intg_err;
tlul_cmd_intg_chk u_chk (
.tl_i(tl_i),
.err_o(intg_err)
);
// also check for spurious write enables
logic reg_we_err;
logic [56:0] reg_we_check;
prim_reg_we_check #(
.OneHotWidth(57)
) u_prim_reg_we_check (
.clk_i(clk_i),
.rst_ni(rst_ni),
.oh_i (reg_we_check),
.en_i (reg_we && !addrmiss),
.err_o (reg_we_err)
);
logic err_q;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
err_q <= '0;
end else if (intg_err || reg_we_err) begin
err_q <= 1'b1;
end
end
// integrity error output is permanent and should be used for alert generation
// register errors are transactional
assign intg_err_o = err_q | intg_err | reg_we_err;
// outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
tlul_rsp_intg_gen #(
.EnableRspIntgGen(1),
.EnableDataIntgGen(1)
) u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o(tl_o)
);
assign tl_reg_h2d = tl_i;
assign tl_o_pre = tl_reg_d2h;
tlul_adapter_reg #(
.RegAw(AW),
.RegDw(DW),
.EnableDataIntgGen(0)
) u_reg_if (
.clk_i (clk_i),
.rst_ni (rst_ni),
.tl_i (tl_reg_h2d),
.tl_o (tl_reg_d2h),
.en_ifetch_i(prim_mubi_pkg::MuBi4False),
.intg_error_o(),
.we_o (reg_we),
.re_o (reg_re),
.addr_o (reg_addr),
.wdata_o (reg_wdata),
.be_o (reg_be),
.busy_i (reg_busy),
.rdata_i (reg_rdata),
.error_i (reg_error)
);
// cdc oversampling signals
assign reg_rdata = reg_rdata_next ;
assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
logic intr_state_we;
logic intr_state_es_entropy_valid_qs;
logic intr_state_es_entropy_valid_wd;
logic intr_state_es_health_test_failed_qs;
logic intr_state_es_health_test_failed_wd;
logic intr_state_es_observe_fifo_ready_qs;
logic intr_state_es_observe_fifo_ready_wd;
logic intr_state_es_fatal_err_qs;
logic intr_state_es_fatal_err_wd;
logic intr_enable_we;
logic intr_enable_es_entropy_valid_qs;
logic intr_enable_es_entropy_valid_wd;
logic intr_enable_es_health_test_failed_qs;
logic intr_enable_es_health_test_failed_wd;
logic intr_enable_es_observe_fifo_ready_qs;
logic intr_enable_es_observe_fifo_ready_wd;
logic intr_enable_es_fatal_err_qs;
logic intr_enable_es_fatal_err_wd;
logic intr_test_we;
logic intr_test_es_entropy_valid_wd;
logic intr_test_es_health_test_failed_wd;
logic intr_test_es_observe_fifo_ready_wd;
logic intr_test_es_fatal_err_wd;
logic alert_test_we;
logic alert_test_recov_alert_wd;
logic alert_test_fatal_alert_wd;
logic me_regwen_we;
logic me_regwen_qs;
logic me_regwen_wd;
logic sw_regupd_we;
logic sw_regupd_qs;
logic sw_regupd_wd;
logic regwen_qs;
logic [7:0] rev_abi_revision_qs;
logic [7:0] rev_hw_revision_qs;
logic [7:0] rev_chip_type_qs;
logic module_enable_we;
logic [3:0] module_enable_qs;
logic [3:0] module_enable_wd;
logic conf_we;
logic [3:0] conf_fips_enable_qs;
logic [3:0] conf_fips_enable_wd;
logic [3:0] conf_entropy_data_reg_enable_qs;
logic [3:0] conf_entropy_data_reg_enable_wd;
logic [3:0] conf_threshold_scope_qs;
logic [3:0] conf_threshold_scope_wd;
logic [3:0] conf_rng_bit_enable_qs;
logic [3:0] conf_rng_bit_enable_wd;
logic [1:0] conf_rng_bit_sel_qs;
logic [1:0] conf_rng_bit_sel_wd;
logic entropy_control_we;
logic [3:0] entropy_control_es_route_qs;
logic [3:0] entropy_control_es_route_wd;
logic [3:0] entropy_control_es_type_qs;
logic [3:0] entropy_control_es_type_wd;
logic entropy_data_re;
logic [31:0] entropy_data_qs;
logic health_test_windows_we;
logic [15:0] health_test_windows_fips_window_qs;
logic [15:0] health_test_windows_fips_window_wd;
logic [15:0] health_test_windows_bypass_window_qs;
logic [15:0] health_test_windows_bypass_window_wd;
logic repcnt_thresholds_re;
logic repcnt_thresholds_we;
logic [15:0] repcnt_thresholds_fips_thresh_qs;
logic [15:0] repcnt_thresholds_fips_thresh_wd;
logic [15:0] repcnt_thresholds_bypass_thresh_qs;
logic [15:0] repcnt_thresholds_bypass_thresh_wd;
logic repcnts_thresholds_re;
logic repcnts_thresholds_we;
logic [15:0] repcnts_thresholds_fips_thresh_qs;
logic [15:0] repcnts_thresholds_fips_thresh_wd;
logic [15:0] repcnts_thresholds_bypass_thresh_qs;
logic [15:0] repcnts_thresholds_bypass_thresh_wd;
logic adaptp_hi_thresholds_re;
logic adaptp_hi_thresholds_we;
logic [15:0] adaptp_hi_thresholds_fips_thresh_qs;
logic [15:0] adaptp_hi_thresholds_fips_thresh_wd;
logic [15:0] adaptp_hi_thresholds_bypass_thresh_qs;
logic [15:0] adaptp_hi_thresholds_bypass_thresh_wd;
logic adaptp_lo_thresholds_re;
logic adaptp_lo_thresholds_we;
logic [15:0] adaptp_lo_thresholds_fips_thresh_qs;
logic [15:0] adaptp_lo_thresholds_fips_thresh_wd;
logic [15:0] adaptp_lo_thresholds_bypass_thresh_qs;
logic [15:0] adaptp_lo_thresholds_bypass_thresh_wd;
logic bucket_thresholds_re;
logic bucket_thresholds_we;
logic [15:0] bucket_thresholds_fips_thresh_qs;
logic [15:0] bucket_thresholds_fips_thresh_wd;
logic [15:0] bucket_thresholds_bypass_thresh_qs;
logic [15:0] bucket_thresholds_bypass_thresh_wd;
logic markov_hi_thresholds_re;
logic markov_hi_thresholds_we;
logic [15:0] markov_hi_thresholds_fips_thresh_qs;
logic [15:0] markov_hi_thresholds_fips_thresh_wd;
logic [15:0] markov_hi_thresholds_bypass_thresh_qs;
logic [15:0] markov_hi_thresholds_bypass_thresh_wd;
logic markov_lo_thresholds_re;
logic markov_lo_thresholds_we;
logic [15:0] markov_lo_thresholds_fips_thresh_qs;
logic [15:0] markov_lo_thresholds_fips_thresh_wd;
logic [15:0] markov_lo_thresholds_bypass_thresh_qs;
logic [15:0] markov_lo_thresholds_bypass_thresh_wd;
logic extht_hi_thresholds_re;
logic extht_hi_thresholds_we;
logic [15:0] extht_hi_thresholds_fips_thresh_qs;
logic [15:0] extht_hi_thresholds_fips_thresh_wd;
logic [15:0] extht_hi_thresholds_bypass_thresh_qs;
logic [15:0] extht_hi_thresholds_bypass_thresh_wd;
logic extht_lo_thresholds_re;
logic extht_lo_thresholds_we;
logic [15:0] extht_lo_thresholds_fips_thresh_qs;
logic [15:0] extht_lo_thresholds_fips_thresh_wd;
logic [15:0] extht_lo_thresholds_bypass_thresh_qs;
logic [15:0] extht_lo_thresholds_bypass_thresh_wd;
logic repcnt_hi_watermarks_re;
logic [15:0] repcnt_hi_watermarks_fips_watermark_qs;
logic [15:0] repcnt_hi_watermarks_bypass_watermark_qs;
logic repcnts_hi_watermarks_re;
logic [15:0] repcnts_hi_watermarks_fips_watermark_qs;
logic [15:0] repcnts_hi_watermarks_bypass_watermark_qs;
logic adaptp_hi_watermarks_re;
logic [15:0] adaptp_hi_watermarks_fips_watermark_qs;
logic [15:0] adaptp_hi_watermarks_bypass_watermark_qs;
logic adaptp_lo_watermarks_re;
logic [15:0] adaptp_lo_watermarks_fips_watermark_qs;
logic [15:0] adaptp_lo_watermarks_bypass_watermark_qs;
logic extht_hi_watermarks_re;
logic [15:0] extht_hi_watermarks_fips_watermark_qs;
logic [15:0] extht_hi_watermarks_bypass_watermark_qs;
logic extht_lo_watermarks_re;
logic [15:0] extht_lo_watermarks_fips_watermark_qs;
logic [15:0] extht_lo_watermarks_bypass_watermark_qs;
logic bucket_hi_watermarks_re;
logic [15:0] bucket_hi_watermarks_fips_watermark_qs;
logic [15:0] bucket_hi_watermarks_bypass_watermark_qs;
logic markov_hi_watermarks_re;
logic [15:0] markov_hi_watermarks_fips_watermark_qs;
logic [15:0] markov_hi_watermarks_bypass_watermark_qs;
logic markov_lo_watermarks_re;
logic [15:0] markov_lo_watermarks_fips_watermark_qs;
logic [15:0] markov_lo_watermarks_bypass_watermark_qs;
logic repcnt_total_fails_re;
logic [31:0] repcnt_total_fails_qs;
logic repcnts_total_fails_re;
logic [31:0] repcnts_total_fails_qs;
logic adaptp_hi_total_fails_re;
logic [31:0] adaptp_hi_total_fails_qs;
logic adaptp_lo_total_fails_re;
logic [31:0] adaptp_lo_total_fails_qs;
logic bucket_total_fails_re;
logic [31:0] bucket_total_fails_qs;
logic markov_hi_total_fails_re;
logic [31:0] markov_hi_total_fails_qs;
logic markov_lo_total_fails_re;
logic [31:0] markov_lo_total_fails_qs;
logic extht_hi_total_fails_re;
logic [31:0] extht_hi_total_fails_qs;
logic extht_lo_total_fails_re;
logic [31:0] extht_lo_total_fails_qs;
logic alert_threshold_we;
logic [15:0] alert_threshold_alert_threshold_qs;
logic [15:0] alert_threshold_alert_threshold_wd;
logic [15:0] alert_threshold_alert_threshold_inv_qs;
logic [15:0] alert_threshold_alert_threshold_inv_wd;
logic alert_summary_fail_counts_re;
logic [15:0] alert_summary_fail_counts_qs;
logic alert_fail_counts_re;
logic [3:0] alert_fail_counts_repcnt_fail_count_qs;
logic [3:0] alert_fail_counts_adaptp_hi_fail_count_qs;
logic [3:0] alert_fail_counts_adaptp_lo_fail_count_qs;
logic [3:0] alert_fail_counts_bucket_fail_count_qs;
logic [3:0] alert_fail_counts_markov_hi_fail_count_qs;
logic [3:0] alert_fail_counts_markov_lo_fail_count_qs;
logic [3:0] alert_fail_counts_repcnts_fail_count_qs;
logic extht_fail_counts_re;
logic [3:0] extht_fail_counts_extht_hi_fail_count_qs;
logic [3:0] extht_fail_counts_extht_lo_fail_count_qs;
logic fw_ov_control_we;
logic [3:0] fw_ov_control_fw_ov_mode_qs;
logic [3:0] fw_ov_control_fw_ov_mode_wd;
logic [3:0] fw_ov_control_fw_ov_entropy_insert_qs;
logic [3:0] fw_ov_control_fw_ov_entropy_insert_wd;
logic fw_ov_sha3_start_we;
logic [3:0] fw_ov_sha3_start_qs;
logic [3:0] fw_ov_sha3_start_wd;
logic fw_ov_wr_fifo_full_re;
logic fw_ov_wr_fifo_full_qs;
logic fw_ov_rd_fifo_overflow_we;
logic fw_ov_rd_fifo_overflow_qs;
logic fw_ov_rd_fifo_overflow_wd;
logic fw_ov_rd_data_re;
logic [31:0] fw_ov_rd_data_qs;
logic fw_ov_wr_data_we;
logic [31:0] fw_ov_wr_data_wd;
logic observe_fifo_thresh_we;
logic [6:0] observe_fifo_thresh_qs;
logic [6:0] observe_fifo_thresh_wd;
logic observe_fifo_depth_re;
logic [6:0] observe_fifo_depth_qs;
logic debug_status_re;
logic [2:0] debug_status_entropy_fifo_depth_qs;
logic [2:0] debug_status_sha3_fsm_qs;
logic debug_status_sha3_block_pr_qs;
logic debug_status_sha3_squeezing_qs;
logic debug_status_sha3_absorbed_qs;
logic debug_status_sha3_err_qs;
logic debug_status_main_sm_idle_qs;
logic debug_status_main_sm_boot_done_qs;
logic recov_alert_sts_we;
logic recov_alert_sts_fips_enable_field_alert_qs;
logic recov_alert_sts_fips_enable_field_alert_wd;
logic recov_alert_sts_entropy_data_reg_en_field_alert_qs;
logic recov_alert_sts_entropy_data_reg_en_field_alert_wd;
logic recov_alert_sts_module_enable_field_alert_qs;
logic recov_alert_sts_module_enable_field_alert_wd;
logic recov_alert_sts_threshold_scope_field_alert_qs;
logic recov_alert_sts_threshold_scope_field_alert_wd;
logic recov_alert_sts_rng_bit_enable_field_alert_qs;
logic recov_alert_sts_rng_bit_enable_field_alert_wd;
logic recov_alert_sts_fw_ov_sha3_start_field_alert_qs;
logic recov_alert_sts_fw_ov_sha3_start_field_alert_wd;
logic recov_alert_sts_fw_ov_mode_field_alert_qs;
logic recov_alert_sts_fw_ov_mode_field_alert_wd;
logic recov_alert_sts_fw_ov_entropy_insert_field_alert_qs;
logic recov_alert_sts_fw_ov_entropy_insert_field_alert_wd;
logic recov_alert_sts_es_route_field_alert_qs;
logic recov_alert_sts_es_route_field_alert_wd;
logic recov_alert_sts_es_type_field_alert_qs;
logic recov_alert_sts_es_type_field_alert_wd;
logic recov_alert_sts_es_main_sm_alert_qs;
logic recov_alert_sts_es_main_sm_alert_wd;
logic recov_alert_sts_es_bus_cmp_alert_qs;
logic recov_alert_sts_es_bus_cmp_alert_wd;
logic recov_alert_sts_es_thresh_cfg_alert_qs;
logic recov_alert_sts_es_thresh_cfg_alert_wd;
logic recov_alert_sts_es_fw_ov_wr_alert_qs;
logic recov_alert_sts_es_fw_ov_wr_alert_wd;
logic recov_alert_sts_es_fw_ov_disable_alert_qs;
logic recov_alert_sts_es_fw_ov_disable_alert_wd;
logic err_code_sfifo_esrng_err_qs;
logic err_code_sfifo_observe_err_qs;
logic err_code_sfifo_esfinal_err_qs;
logic err_code_es_ack_sm_err_qs;
logic err_code_es_main_sm_err_qs;
logic err_code_es_cntr_err_qs;
logic err_code_sha3_state_err_qs;
logic err_code_sha3_rst_storage_err_qs;
logic err_code_fifo_write_err_qs;
logic err_code_fifo_read_err_qs;
logic err_code_fifo_state_err_qs;
logic err_code_test_we;
logic [4:0] err_code_test_qs;
logic [4:0] err_code_test_wd;
logic [8:0] main_sm_state_qs;
// Register instances
// R[intr_state]: V(False)
// F[es_entropy_valid]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_intr_state_es_entropy_valid (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
.wd (intr_state_es_entropy_valid_wd),
// from internal hardware
.de (hw2reg.intr_state.es_entropy_valid.de),
.d (hw2reg.intr_state.es_entropy_valid.d),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.es_entropy_valid.q),
.ds (),
// to register interface (read)
.qs (intr_state_es_entropy_valid_qs)
);
// F[es_health_test_failed]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_intr_state_es_health_test_failed (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
.wd (intr_state_es_health_test_failed_wd),
// from internal hardware
.de (hw2reg.intr_state.es_health_test_failed.de),
.d (hw2reg.intr_state.es_health_test_failed.d),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.es_health_test_failed.q),
.ds (),
// to register interface (read)
.qs (intr_state_es_health_test_failed_qs)
);
// F[es_observe_fifo_ready]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_intr_state_es_observe_fifo_ready (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
.wd (intr_state_es_observe_fifo_ready_wd),
// from internal hardware
.de (hw2reg.intr_state.es_observe_fifo_ready.de),
.d (hw2reg.intr_state.es_observe_fifo_ready.d),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.es_observe_fifo_ready.q),
.ds (),
// to register interface (read)
.qs (intr_state_es_observe_fifo_ready_qs)
);
// F[es_fatal_err]: 3:3
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_intr_state_es_fatal_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
.wd (intr_state_es_fatal_err_wd),
// from internal hardware
.de (hw2reg.intr_state.es_fatal_err.de),
.d (hw2reg.intr_state.es_fatal_err.d),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.es_fatal_err.q),
.ds (),
// to register interface (read)
.qs (intr_state_es_fatal_err_qs)
);
// R[intr_enable]: V(False)
// F[es_entropy_valid]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_intr_enable_es_entropy_valid (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
.wd (intr_enable_es_entropy_valid_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.es_entropy_valid.q),
.ds (),
// to register interface (read)
.qs (intr_enable_es_entropy_valid_qs)
);
// F[es_health_test_failed]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_intr_enable_es_health_test_failed (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
.wd (intr_enable_es_health_test_failed_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.es_health_test_failed.q),
.ds (),
// to register interface (read)
.qs (intr_enable_es_health_test_failed_qs)
);
// F[es_observe_fifo_ready]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_intr_enable_es_observe_fifo_ready (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
.wd (intr_enable_es_observe_fifo_ready_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.es_observe_fifo_ready.q),
.ds (),
// to register interface (read)
.qs (intr_enable_es_observe_fifo_ready_qs)
);
// F[es_fatal_err]: 3:3
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_intr_enable_es_fatal_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
.wd (intr_enable_es_fatal_err_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.es_fatal_err.q),
.ds (),
// to register interface (read)
.qs (intr_enable_es_fatal_err_qs)
);
// R[intr_test]: V(True)
logic intr_test_qe;
logic [3:0] intr_test_flds_we;
assign intr_test_qe = &intr_test_flds_we;
// F[es_entropy_valid]: 0:0
prim_subreg_ext #(
.DW (1)
) u_intr_test_es_entropy_valid (
.re (1'b0),
.we (intr_test_we),
.wd (intr_test_es_entropy_valid_wd),
.d ('0),
.qre (),
.qe (intr_test_flds_we[0]),
.q (reg2hw.intr_test.es_entropy_valid.q),
.ds (),
.qs ()
);
assign reg2hw.intr_test.es_entropy_valid.qe = intr_test_qe;
// F[es_health_test_failed]: 1:1
prim_subreg_ext #(
.DW (1)
) u_intr_test_es_health_test_failed (
.re (1'b0),
.we (intr_test_we),
.wd (intr_test_es_health_test_failed_wd),
.d ('0),
.qre (),
.qe (intr_test_flds_we[1]),
.q (reg2hw.intr_test.es_health_test_failed.q),
.ds (),
.qs ()
);
assign reg2hw.intr_test.es_health_test_failed.qe = intr_test_qe;
// F[es_observe_fifo_ready]: 2:2
prim_subreg_ext #(
.DW (1)
) u_intr_test_es_observe_fifo_ready (
.re (1'b0),
.we (intr_test_we),
.wd (intr_test_es_observe_fifo_ready_wd),
.d ('0),
.qre (),
.qe (intr_test_flds_we[2]),
.q (reg2hw.intr_test.es_observe_fifo_ready.q),
.ds (),
.qs ()
);
assign reg2hw.intr_test.es_observe_fifo_ready.qe = intr_test_qe;
// F[es_fatal_err]: 3:3
prim_subreg_ext #(
.DW (1)
) u_intr_test_es_fatal_err (
.re (1'b0),
.we (intr_test_we),
.wd (intr_test_es_fatal_err_wd),
.d ('0),
.qre (),
.qe (intr_test_flds_we[3]),
.q (reg2hw.intr_test.es_fatal_err.q),
.ds (),
.qs ()
);
assign reg2hw.intr_test.es_fatal_err.qe = intr_test_qe;
// R[alert_test]: V(True)
logic alert_test_qe;
logic [1:0] alert_test_flds_we;
assign alert_test_qe = &alert_test_flds_we;
// F[recov_alert]: 0:0
prim_subreg_ext #(
.DW (1)
) u_alert_test_recov_alert (
.re (1'b0),
.we (alert_test_we),
.wd (alert_test_recov_alert_wd),
.d ('0),
.qre (),
.qe (alert_test_flds_we[0]),
.q (reg2hw.alert_test.recov_alert.q),
.ds (),
.qs ()
);
assign reg2hw.alert_test.recov_alert.qe = alert_test_qe;
// F[fatal_alert]: 1:1
prim_subreg_ext #(
.DW (1)
) u_alert_test_fatal_alert (
.re (1'b0),
.we (alert_test_we),
.wd (alert_test_fatal_alert_wd),
.d ('0),
.qre (),
.qe (alert_test_flds_we[1]),
.q (reg2hw.alert_test.fatal_alert.q),
.ds (),
.qs ()
);
assign reg2hw.alert_test.fatal_alert.qe = alert_test_qe;
// R[me_regwen]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_me_regwen (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (me_regwen_we),
.wd (me_regwen_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (me_regwen_qs)
);
// R[sw_regupd]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_sw_regupd (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (sw_regupd_we),
.wd (sw_regupd_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.sw_regupd.q),
.ds (),
// to register interface (read)
.qs (sw_regupd_qs)
);
// R[regwen]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h1)
) u_regwen (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.regwen.de),
.d (hw2reg.regwen.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (regwen_qs)
);
// R[rev]: V(False)
// F[abi_revision]: 7:0
// constant-only read
assign rev_abi_revision_qs = 8'h3;
// F[hw_revision]: 15:8
// constant-only read
assign rev_hw_revision_qs = 8'h3;
// F[chip_type]: 23:16
// constant-only read
assign rev_chip_type_qs = 8'h1;
// R[module_enable]: V(False)
// Create REGWEN-gated WE signal
logic module_enable_gated_we;
assign module_enable_gated_we = module_enable_we & me_regwen_qs;
prim_subreg #(
.DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (4'h9)
) u_module_enable (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (module_enable_gated_we),
.wd (module_enable_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.module_enable.q),
.ds (),
// to register interface (read)
.qs (module_enable_qs)
);
// R[conf]: V(False)
// Create REGWEN-gated WE signal
logic conf_gated_we;
assign conf_gated_we = conf_we & regwen_qs;
// F[fips_enable]: 3:0
prim_subreg #(
.DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (4'h9)
) u_conf_fips_enable (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (conf_gated_we),
.wd (conf_fips_enable_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.conf.fips_enable.q),
.ds (),
// to register interface (read)
.qs (conf_fips_enable_qs)
);
// F[entropy_data_reg_enable]: 7:4
prim_subreg #(
.DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (4'h9)
) u_conf_entropy_data_reg_enable (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (conf_gated_we),
.wd (conf_entropy_data_reg_enable_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.conf.entropy_data_reg_enable.q),
.ds (),
// to register interface (read)
.qs (conf_entropy_data_reg_enable_qs)
);
// F[threshold_scope]: 15:12
prim_subreg #(
.DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (4'h9)
) u_conf_threshold_scope (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (conf_gated_we),
.wd (conf_threshold_scope_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.conf.threshold_scope.q),
.ds (),
// to register interface (read)
.qs (conf_threshold_scope_qs)
);
// F[rng_bit_enable]: 23:20
prim_subreg #(
.DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (4'h9)
) u_conf_rng_bit_enable (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (conf_gated_we),
.wd (conf_rng_bit_enable_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.conf.rng_bit_enable.q),
.ds (),
// to register interface (read)
.qs (conf_rng_bit_enable_qs)
);
// F[rng_bit_sel]: 25:24
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_conf_rng_bit_sel (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (conf_gated_we),
.wd (conf_rng_bit_sel_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.conf.rng_bit_sel.q),
.ds (),
// to register interface (read)
.qs (conf_rng_bit_sel_qs)
);
// R[entropy_control]: V(False)
// Create REGWEN-gated WE signal
logic entropy_control_gated_we;
assign entropy_control_gated_we = entropy_control_we & regwen_qs;
// F[es_route]: 3:0
prim_subreg #(
.DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (4'h9)
) u_entropy_control_es_route (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (entropy_control_gated_we),
.wd (entropy_control_es_route_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.entropy_control.es_route.q),
.ds (),
// to register interface (read)
.qs (entropy_control_es_route_qs)
);
// F[es_type]: 7:4
prim_subreg #(
.DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (4'h9)
) u_entropy_control_es_type (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (entropy_control_gated_we),
.wd (entropy_control_es_type_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.entropy_control.es_type.q),
.ds (),
// to register interface (read)
.qs (entropy_control_es_type_qs)
);
// R[entropy_data]: V(True)
prim_subreg_ext #(
.DW (32)
) u_entropy_data (
.re (entropy_data_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.entropy_data.d),
.qre (reg2hw.entropy_data.re),
.qe (),
.q (reg2hw.entropy_data.q),
.ds (),
.qs (entropy_data_qs)
);
// R[health_test_windows]: V(False)
// Create REGWEN-gated WE signal
logic health_test_windows_gated_we;
assign health_test_windows_gated_we = health_test_windows_we & regwen_qs;
// F[fips_window]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h200)
) u_health_test_windows_fips_window (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (health_test_windows_gated_we),
.wd (health_test_windows_fips_window_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.health_test_windows.fips_window.q),
.ds (),
// to register interface (read)
.qs (health_test_windows_fips_window_qs)
);
// F[bypass_window]: 31:16
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h60)
) u_health_test_windows_bypass_window (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (health_test_windows_gated_we),
.wd (health_test_windows_bypass_window_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.health_test_windows.bypass_window.q),
.ds (),
// to register interface (read)
.qs (health_test_windows_bypass_window_qs)
);
// R[repcnt_thresholds]: V(True)
logic repcnt_thresholds_qe;
logic [1:0] repcnt_thresholds_flds_we;
assign repcnt_thresholds_qe = &repcnt_thresholds_flds_we;
// Create REGWEN-gated WE signal
logic repcnt_thresholds_gated_we;
assign repcnt_thresholds_gated_we = repcnt_thresholds_we & regwen_qs;
// F[fips_thresh]: 15:0
prim_subreg_ext #(
.DW (16)
) u_repcnt_thresholds_fips_thresh (
.re (repcnt_thresholds_re),
.we (repcnt_thresholds_gated_we),
.wd (repcnt_thresholds_fips_thresh_wd),
.d (hw2reg.repcnt_thresholds.fips_thresh.d),
.qre (),
.qe (repcnt_thresholds_flds_we[0]),
.q (reg2hw.repcnt_thresholds.fips_thresh.q),
.ds (),
.qs (repcnt_thresholds_fips_thresh_qs)
);
assign reg2hw.repcnt_thresholds.fips_thresh.qe = repcnt_thresholds_qe;
// F[bypass_thresh]: 31:16
prim_subreg_ext #(
.DW (16)
) u_repcnt_thresholds_bypass_thresh (
.re (repcnt_thresholds_re),
.we (repcnt_thresholds_gated_we),
.wd (repcnt_thresholds_bypass_thresh_wd),
.d (hw2reg.repcnt_thresholds.bypass_thresh.d),
.qre (),
.qe (repcnt_thresholds_flds_we[1]),
.q (reg2hw.repcnt_thresholds.bypass_thresh.q),
.ds (),
.qs (repcnt_thresholds_bypass_thresh_qs)
);
assign reg2hw.repcnt_thresholds.bypass_thresh.qe = repcnt_thresholds_qe;
// R[repcnts_thresholds]: V(True)
logic repcnts_thresholds_qe;
logic [1:0] repcnts_thresholds_flds_we;
assign repcnts_thresholds_qe = &repcnts_thresholds_flds_we;
// Create REGWEN-gated WE signal
logic repcnts_thresholds_gated_we;
assign repcnts_thresholds_gated_we = repcnts_thresholds_we & regwen_qs;
// F[fips_thresh]: 15:0
prim_subreg_ext #(
.DW (16)
) u_repcnts_thresholds_fips_thresh (
.re (repcnts_thresholds_re),
.we (repcnts_thresholds_gated_we),
.wd (repcnts_thresholds_fips_thresh_wd),
.d (hw2reg.repcnts_thresholds.fips_thresh.d),
.qre (),
.qe (repcnts_thresholds_flds_we[0]),
.q (reg2hw.repcnts_thresholds.fips_thresh.q),
.ds (),
.qs (repcnts_thresholds_fips_thresh_qs)
);
assign reg2hw.repcnts_thresholds.fips_thresh.qe = repcnts_thresholds_qe;
// F[bypass_thresh]: 31:16
prim_subreg_ext #(
.DW (16)
) u_repcnts_thresholds_bypass_thresh (
.re (repcnts_thresholds_re),
.we (repcnts_thresholds_gated_we),
.wd (repcnts_thresholds_bypass_thresh_wd),
.d (hw2reg.repcnts_thresholds.bypass_thresh.d),
.qre (),
.qe (repcnts_thresholds_flds_we[1]),
.q (reg2hw.repcnts_thresholds.bypass_thresh.q),
.ds (),
.qs (repcnts_thresholds_bypass_thresh_qs)
);
assign reg2hw.repcnts_thresholds.bypass_thresh.qe = repcnts_thresholds_qe;
// R[adaptp_hi_thresholds]: V(True)
logic adaptp_hi_thresholds_qe;
logic [1:0] adaptp_hi_thresholds_flds_we;
assign adaptp_hi_thresholds_qe = &adaptp_hi_thresholds_flds_we;
// Create REGWEN-gated WE signal
logic adaptp_hi_thresholds_gated_we;
assign adaptp_hi_thresholds_gated_we = adaptp_hi_thresholds_we & regwen_qs;
// F[fips_thresh]: 15:0
prim_subreg_ext #(
.DW (16)
) u_adaptp_hi_thresholds_fips_thresh (
.re (adaptp_hi_thresholds_re),
.we (adaptp_hi_thresholds_gated_we),
.wd (adaptp_hi_thresholds_fips_thresh_wd),
.d (hw2reg.adaptp_hi_thresholds.fips_thresh.d),
.qre (),
.qe (adaptp_hi_thresholds_flds_we[0]),
.q (reg2hw.adaptp_hi_thresholds.fips_thresh.q),
.ds (),
.qs (adaptp_hi_thresholds_fips_thresh_qs)
);
assign reg2hw.adaptp_hi_thresholds.fips_thresh.qe = adaptp_hi_thresholds_qe;
// F[bypass_thresh]: 31:16
prim_subreg_ext #(
.DW (16)
) u_adaptp_hi_thresholds_bypass_thresh (
.re (adaptp_hi_thresholds_re),
.we (adaptp_hi_thresholds_gated_we),
.wd (adaptp_hi_thresholds_bypass_thresh_wd),
.d (hw2reg.adaptp_hi_thresholds.bypass_thresh.d),
.qre (),
.qe (adaptp_hi_thresholds_flds_we[1]),
.q (reg2hw.adaptp_hi_thresholds.bypass_thresh.q),
.ds (),
.qs (adaptp_hi_thresholds_bypass_thresh_qs)
);
assign reg2hw.adaptp_hi_thresholds.bypass_thresh.qe = adaptp_hi_thresholds_qe;
// R[adaptp_lo_thresholds]: V(True)
logic adaptp_lo_thresholds_qe;
logic [1:0] adaptp_lo_thresholds_flds_we;
assign adaptp_lo_thresholds_qe = &adaptp_lo_thresholds_flds_we;
// Create REGWEN-gated WE signal
logic adaptp_lo_thresholds_gated_we;
assign adaptp_lo_thresholds_gated_we = adaptp_lo_thresholds_we & regwen_qs;
// F[fips_thresh]: 15:0
prim_subreg_ext #(
.DW (16)
) u_adaptp_lo_thresholds_fips_thresh (
.re (adaptp_lo_thresholds_re),
.we (adaptp_lo_thresholds_gated_we),
.wd (adaptp_lo_thresholds_fips_thresh_wd),
.d (hw2reg.adaptp_lo_thresholds.fips_thresh.d),
.qre (),
.qe (adaptp_lo_thresholds_flds_we[0]),
.q (reg2hw.adaptp_lo_thresholds.fips_thresh.q),
.ds (),
.qs (adaptp_lo_thresholds_fips_thresh_qs)
);
assign reg2hw.adaptp_lo_thresholds.fips_thresh.qe = adaptp_lo_thresholds_qe;
// F[bypass_thresh]: 31:16
prim_subreg_ext #(
.DW (16)
) u_adaptp_lo_thresholds_bypass_thresh (
.re (adaptp_lo_thresholds_re),
.we (adaptp_lo_thresholds_gated_we),
.wd (adaptp_lo_thresholds_bypass_thresh_wd),
.d (hw2reg.adaptp_lo_thresholds.bypass_thresh.d),
.qre (),
.qe (adaptp_lo_thresholds_flds_we[1]),
.q (reg2hw.adaptp_lo_thresholds.bypass_thresh.q),
.ds (),
.qs (adaptp_lo_thresholds_bypass_thresh_qs)
);
assign reg2hw.adaptp_lo_thresholds.bypass_thresh.qe = adaptp_lo_thresholds_qe;
// R[bucket_thresholds]: V(True)
logic bucket_thresholds_qe;
logic [1:0] bucket_thresholds_flds_we;
assign bucket_thresholds_qe = &bucket_thresholds_flds_we;
// Create REGWEN-gated WE signal
logic bucket_thresholds_gated_we;
assign bucket_thresholds_gated_we = bucket_thresholds_we & regwen_qs;
// F[fips_thresh]: 15:0
prim_subreg_ext #(
.DW (16)
) u_bucket_thresholds_fips_thresh (
.re (bucket_thresholds_re),
.we (bucket_thresholds_gated_we),
.wd (bucket_thresholds_fips_thresh_wd),
.d (hw2reg.bucket_thresholds.fips_thresh.d),
.qre (),
.qe (bucket_thresholds_flds_we[0]),
.q (reg2hw.bucket_thresholds.fips_thresh.q),
.ds (),
.qs (bucket_thresholds_fips_thresh_qs)
);
assign reg2hw.bucket_thresholds.fips_thresh.qe = bucket_thresholds_qe;
// F[bypass_thresh]: 31:16
prim_subreg_ext #(
.DW (16)
) u_bucket_thresholds_bypass_thresh (
.re (bucket_thresholds_re),
.we (bucket_thresholds_gated_we),
.wd (bucket_thresholds_bypass_thresh_wd),
.d (hw2reg.bucket_thresholds.bypass_thresh.d),
.qre (),
.qe (bucket_thresholds_flds_we[1]),
.q (reg2hw.bucket_thresholds.bypass_thresh.q),
.ds (),
.qs (bucket_thresholds_bypass_thresh_qs)
);
assign reg2hw.bucket_thresholds.bypass_thresh.qe = bucket_thresholds_qe;
// R[markov_hi_thresholds]: V(True)
logic markov_hi_thresholds_qe;
logic [1:0] markov_hi_thresholds_flds_we;
assign markov_hi_thresholds_qe = &markov_hi_thresholds_flds_we;
// Create REGWEN-gated WE signal
logic markov_hi_thresholds_gated_we;
assign markov_hi_thresholds_gated_we = markov_hi_thresholds_we & regwen_qs;
// F[fips_thresh]: 15:0
prim_subreg_ext #(
.DW (16)
) u_markov_hi_thresholds_fips_thresh (
.re (markov_hi_thresholds_re),
.we (markov_hi_thresholds_gated_we),
.wd (markov_hi_thresholds_fips_thresh_wd),
.d (hw2reg.markov_hi_thresholds.fips_thresh.d),
.qre (),
.qe (markov_hi_thresholds_flds_we[0]),
.q (reg2hw.markov_hi_thresholds.fips_thresh.q),
.ds (),
.qs (markov_hi_thresholds_fips_thresh_qs)
);
assign reg2hw.markov_hi_thresholds.fips_thresh.qe = markov_hi_thresholds_qe;
// F[bypass_thresh]: 31:16
prim_subreg_ext #(
.DW (16)
) u_markov_hi_thresholds_bypass_thresh (
.re (markov_hi_thresholds_re),
.we (markov_hi_thresholds_gated_we),
.wd (markov_hi_thresholds_bypass_thresh_wd),
.d (hw2reg.markov_hi_thresholds.bypass_thresh.d),
.qre (),
.qe (markov_hi_thresholds_flds_we[1]),
.q (reg2hw.markov_hi_thresholds.bypass_thresh.q),
.ds (),
.qs (markov_hi_thresholds_bypass_thresh_qs)
);
assign reg2hw.markov_hi_thresholds.bypass_thresh.qe = markov_hi_thresholds_qe;
// R[markov_lo_thresholds]: V(True)
logic markov_lo_thresholds_qe;
logic [1:0] markov_lo_thresholds_flds_we;
assign markov_lo_thresholds_qe = &markov_lo_thresholds_flds_we;
// Create REGWEN-gated WE signal
logic markov_lo_thresholds_gated_we;
assign markov_lo_thresholds_gated_we = markov_lo_thresholds_we & regwen_qs;
// F[fips_thresh]: 15:0
prim_subreg_ext #(
.DW (16)
) u_markov_lo_thresholds_fips_thresh (
.re (markov_lo_thresholds_re),
.we (markov_lo_thresholds_gated_we),
.wd (markov_lo_thresholds_fips_thresh_wd),
.d (hw2reg.markov_lo_thresholds.fips_thresh.d),
.qre (),
.qe (markov_lo_thresholds_flds_we[0]),
.q (reg2hw.markov_lo_thresholds.fips_thresh.q),
.ds (),
.qs (markov_lo_thresholds_fips_thresh_qs)
);
assign reg2hw.markov_lo_thresholds.fips_thresh.qe = markov_lo_thresholds_qe;
// F[bypass_thresh]: 31:16
prim_subreg_ext #(
.DW (16)
) u_markov_lo_thresholds_bypass_thresh (
.re (markov_lo_thresholds_re),
.we (markov_lo_thresholds_gated_we),
.wd (markov_lo_thresholds_bypass_thresh_wd),
.d (hw2reg.markov_lo_thresholds.bypass_thresh.d),
.qre (),
.qe (markov_lo_thresholds_flds_we[1]),
.q (reg2hw.markov_lo_thresholds.bypass_thresh.q),
.ds (),
.qs (markov_lo_thresholds_bypass_thresh_qs)
);
assign reg2hw.markov_lo_thresholds.bypass_thresh.qe = markov_lo_thresholds_qe;
// R[extht_hi_thresholds]: V(True)
logic extht_hi_thresholds_qe;
logic [1:0] extht_hi_thresholds_flds_we;
assign extht_hi_thresholds_qe = &extht_hi_thresholds_flds_we;
// Create REGWEN-gated WE signal
logic extht_hi_thresholds_gated_we;
assign extht_hi_thresholds_gated_we = extht_hi_thresholds_we & regwen_qs;
// F[fips_thresh]: 15:0
prim_subreg_ext #(
.DW (16)
) u_extht_hi_thresholds_fips_thresh (
.re (extht_hi_thresholds_re),
.we (extht_hi_thresholds_gated_we),
.wd (extht_hi_thresholds_fips_thresh_wd),
.d (hw2reg.extht_hi_thresholds.fips_thresh.d),
.qre (),
.qe (extht_hi_thresholds_flds_we[0]),
.q (reg2hw.extht_hi_thresholds.fips_thresh.q),
.ds (),
.qs (extht_hi_thresholds_fips_thresh_qs)
);
assign reg2hw.extht_hi_thresholds.fips_thresh.qe = extht_hi_thresholds_qe;
// F[bypass_thresh]: 31:16
prim_subreg_ext #(
.DW (16)
) u_extht_hi_thresholds_bypass_thresh (
.re (extht_hi_thresholds_re),
.we (extht_hi_thresholds_gated_we),
.wd (extht_hi_thresholds_bypass_thresh_wd),
.d (hw2reg.extht_hi_thresholds.bypass_thresh.d),
.qre (),
.qe (extht_hi_thresholds_flds_we[1]),
.q (reg2hw.extht_hi_thresholds.bypass_thresh.q),
.ds (),
.qs (extht_hi_thresholds_bypass_thresh_qs)
);
assign reg2hw.extht_hi_thresholds.bypass_thresh.qe = extht_hi_thresholds_qe;
// R[extht_lo_thresholds]: V(True)
logic extht_lo_thresholds_qe;
logic [1:0] extht_lo_thresholds_flds_we;
assign extht_lo_thresholds_qe = &extht_lo_thresholds_flds_we;
// Create REGWEN-gated WE signal
logic extht_lo_thresholds_gated_we;
assign extht_lo_thresholds_gated_we = extht_lo_thresholds_we & regwen_qs;
// F[fips_thresh]: 15:0
prim_subreg_ext #(
.DW (16)
) u_extht_lo_thresholds_fips_thresh (
.re (extht_lo_thresholds_re),
.we (extht_lo_thresholds_gated_we),
.wd (extht_lo_thresholds_fips_thresh_wd),
.d (hw2reg.extht_lo_thresholds.fips_thresh.d),
.qre (),
.qe (extht_lo_thresholds_flds_we[0]),
.q (reg2hw.extht_lo_thresholds.fips_thresh.q),
.ds (),
.qs (extht_lo_thresholds_fips_thresh_qs)
);
assign reg2hw.extht_lo_thresholds.fips_thresh.qe = extht_lo_thresholds_qe;
// F[bypass_thresh]: 31:16
prim_subreg_ext #(
.DW (16)
) u_extht_lo_thresholds_bypass_thresh (
.re (extht_lo_thresholds_re),
.we (extht_lo_thresholds_gated_we),
.wd (extht_lo_thresholds_bypass_thresh_wd),
.d (hw2reg.extht_lo_thresholds.bypass_thresh.d),
.qre (),
.qe (extht_lo_thresholds_flds_we[1]),
.q (reg2hw.extht_lo_thresholds.bypass_thresh.q),
.ds (),
.qs (extht_lo_thresholds_bypass_thresh_qs)
);
assign reg2hw.extht_lo_thresholds.bypass_thresh.qe = extht_lo_thresholds_qe;
// R[repcnt_hi_watermarks]: V(True)
// F[fips_watermark]: 15:0
prim_subreg_ext #(
.DW (16)
) u_repcnt_hi_watermarks_fips_watermark (
.re (repcnt_hi_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.repcnt_hi_watermarks.fips_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (repcnt_hi_watermarks_fips_watermark_qs)
);
// F[bypass_watermark]: 31:16
prim_subreg_ext #(
.DW (16)
) u_repcnt_hi_watermarks_bypass_watermark (
.re (repcnt_hi_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.repcnt_hi_watermarks.bypass_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (repcnt_hi_watermarks_bypass_watermark_qs)
);
// R[repcnts_hi_watermarks]: V(True)
// F[fips_watermark]: 15:0
prim_subreg_ext #(
.DW (16)
) u_repcnts_hi_watermarks_fips_watermark (
.re (repcnts_hi_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.repcnts_hi_watermarks.fips_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (repcnts_hi_watermarks_fips_watermark_qs)
);
// F[bypass_watermark]: 31:16
prim_subreg_ext #(
.DW (16)
) u_repcnts_hi_watermarks_bypass_watermark (
.re (repcnts_hi_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.repcnts_hi_watermarks.bypass_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (repcnts_hi_watermarks_bypass_watermark_qs)
);
// R[adaptp_hi_watermarks]: V(True)
// F[fips_watermark]: 15:0
prim_subreg_ext #(
.DW (16)
) u_adaptp_hi_watermarks_fips_watermark (
.re (adaptp_hi_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.adaptp_hi_watermarks.fips_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (adaptp_hi_watermarks_fips_watermark_qs)
);
// F[bypass_watermark]: 31:16
prim_subreg_ext #(
.DW (16)
) u_adaptp_hi_watermarks_bypass_watermark (
.re (adaptp_hi_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.adaptp_hi_watermarks.bypass_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (adaptp_hi_watermarks_bypass_watermark_qs)
);
// R[adaptp_lo_watermarks]: V(True)
// F[fips_watermark]: 15:0
prim_subreg_ext #(
.DW (16)
) u_adaptp_lo_watermarks_fips_watermark (
.re (adaptp_lo_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.adaptp_lo_watermarks.fips_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (adaptp_lo_watermarks_fips_watermark_qs)
);
// F[bypass_watermark]: 31:16
prim_subreg_ext #(
.DW (16)
) u_adaptp_lo_watermarks_bypass_watermark (
.re (adaptp_lo_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.adaptp_lo_watermarks.bypass_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (adaptp_lo_watermarks_bypass_watermark_qs)
);
// R[extht_hi_watermarks]: V(True)
// F[fips_watermark]: 15:0
prim_subreg_ext #(
.DW (16)
) u_extht_hi_watermarks_fips_watermark (
.re (extht_hi_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.extht_hi_watermarks.fips_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (extht_hi_watermarks_fips_watermark_qs)
);
// F[bypass_watermark]: 31:16
prim_subreg_ext #(
.DW (16)
) u_extht_hi_watermarks_bypass_watermark (
.re (extht_hi_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.extht_hi_watermarks.bypass_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (extht_hi_watermarks_bypass_watermark_qs)
);
// R[extht_lo_watermarks]: V(True)
// F[fips_watermark]: 15:0
prim_subreg_ext #(
.DW (16)
) u_extht_lo_watermarks_fips_watermark (
.re (extht_lo_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.extht_lo_watermarks.fips_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (extht_lo_watermarks_fips_watermark_qs)
);
// F[bypass_watermark]: 31:16
prim_subreg_ext #(
.DW (16)
) u_extht_lo_watermarks_bypass_watermark (
.re (extht_lo_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.extht_lo_watermarks.bypass_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (extht_lo_watermarks_bypass_watermark_qs)
);
// R[bucket_hi_watermarks]: V(True)
// F[fips_watermark]: 15:0
prim_subreg_ext #(
.DW (16)
) u_bucket_hi_watermarks_fips_watermark (
.re (bucket_hi_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.bucket_hi_watermarks.fips_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (bucket_hi_watermarks_fips_watermark_qs)
);
// F[bypass_watermark]: 31:16
prim_subreg_ext #(
.DW (16)
) u_bucket_hi_watermarks_bypass_watermark (
.re (bucket_hi_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.bucket_hi_watermarks.bypass_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (bucket_hi_watermarks_bypass_watermark_qs)
);
// R[markov_hi_watermarks]: V(True)
// F[fips_watermark]: 15:0
prim_subreg_ext #(
.DW (16)
) u_markov_hi_watermarks_fips_watermark (
.re (markov_hi_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.markov_hi_watermarks.fips_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (markov_hi_watermarks_fips_watermark_qs)
);
// F[bypass_watermark]: 31:16
prim_subreg_ext #(
.DW (16)
) u_markov_hi_watermarks_bypass_watermark (
.re (markov_hi_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.markov_hi_watermarks.bypass_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (markov_hi_watermarks_bypass_watermark_qs)
);
// R[markov_lo_watermarks]: V(True)
// F[fips_watermark]: 15:0
prim_subreg_ext #(
.DW (16)
) u_markov_lo_watermarks_fips_watermark (
.re (markov_lo_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.markov_lo_watermarks.fips_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (markov_lo_watermarks_fips_watermark_qs)
);
// F[bypass_watermark]: 31:16
prim_subreg_ext #(
.DW (16)
) u_markov_lo_watermarks_bypass_watermark (
.re (markov_lo_watermarks_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.markov_lo_watermarks.bypass_watermark.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (markov_lo_watermarks_bypass_watermark_qs)
);
// R[repcnt_total_fails]: V(True)
prim_subreg_ext #(
.DW (32)
) u_repcnt_total_fails (
.re (repcnt_total_fails_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.repcnt_total_fails.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (repcnt_total_fails_qs)
);
// R[repcnts_total_fails]: V(True)
prim_subreg_ext #(
.DW (32)
) u_repcnts_total_fails (
.re (repcnts_total_fails_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.repcnts_total_fails.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (repcnts_total_fails_qs)
);
// R[adaptp_hi_total_fails]: V(True)
prim_subreg_ext #(
.DW (32)
) u_adaptp_hi_total_fails (
.re (adaptp_hi_total_fails_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.adaptp_hi_total_fails.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (adaptp_hi_total_fails_qs)
);
// R[adaptp_lo_total_fails]: V(True)
prim_subreg_ext #(
.DW (32)
) u_adaptp_lo_total_fails (
.re (adaptp_lo_total_fails_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.adaptp_lo_total_fails.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (adaptp_lo_total_fails_qs)
);
// R[bucket_total_fails]: V(True)
prim_subreg_ext #(
.DW (32)
) u_bucket_total_fails (
.re (bucket_total_fails_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.bucket_total_fails.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (bucket_total_fails_qs)
);
// R[markov_hi_total_fails]: V(True)
prim_subreg_ext #(
.DW (32)
) u_markov_hi_total_fails (
.re (markov_hi_total_fails_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.markov_hi_total_fails.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (markov_hi_total_fails_qs)
);
// R[markov_lo_total_fails]: V(True)
prim_subreg_ext #(
.DW (32)
) u_markov_lo_total_fails (
.re (markov_lo_total_fails_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.markov_lo_total_fails.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (markov_lo_total_fails_qs)
);
// R[extht_hi_total_fails]: V(True)
prim_subreg_ext #(
.DW (32)
) u_extht_hi_total_fails (
.re (extht_hi_total_fails_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.extht_hi_total_fails.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (extht_hi_total_fails_qs)
);
// R[extht_lo_total_fails]: V(True)
prim_subreg_ext #(
.DW (32)
) u_extht_lo_total_fails (
.re (extht_lo_total_fails_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.extht_lo_total_fails.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (extht_lo_total_fails_qs)
);
// R[alert_threshold]: V(False)
// Create REGWEN-gated WE signal
logic alert_threshold_gated_we;
assign alert_threshold_gated_we = alert_threshold_we & regwen_qs;
// F[alert_threshold]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h2)
) u_alert_threshold_alert_threshold (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (alert_threshold_gated_we),
.wd (alert_threshold_alert_threshold_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.alert_threshold.alert_threshold.q),
.ds (),
// to register interface (read)
.qs (alert_threshold_alert_threshold_qs)
);
// F[alert_threshold_inv]: 31:16
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'hfffd)
) u_alert_threshold_alert_threshold_inv (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (alert_threshold_gated_we),
.wd (alert_threshold_alert_threshold_inv_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.alert_threshold.alert_threshold_inv.q),
.ds (),
// to register interface (read)
.qs (alert_threshold_alert_threshold_inv_qs)
);
// R[alert_summary_fail_counts]: V(True)
prim_subreg_ext #(
.DW (16)
) u_alert_summary_fail_counts (
.re (alert_summary_fail_counts_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.alert_summary_fail_counts.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (alert_summary_fail_counts_qs)
);
// R[alert_fail_counts]: V(True)
// F[repcnt_fail_count]: 7:4
prim_subreg_ext #(
.DW (4)
) u_alert_fail_counts_repcnt_fail_count (
.re (alert_fail_counts_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.alert_fail_counts.repcnt_fail_count.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (alert_fail_counts_repcnt_fail_count_qs)
);
// F[adaptp_hi_fail_count]: 11:8
prim_subreg_ext #(
.DW (4)
) u_alert_fail_counts_adaptp_hi_fail_count (
.re (alert_fail_counts_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.alert_fail_counts.adaptp_hi_fail_count.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (alert_fail_counts_adaptp_hi_fail_count_qs)
);
// F[adaptp_lo_fail_count]: 15:12
prim_subreg_ext #(
.DW (4)
) u_alert_fail_counts_adaptp_lo_fail_count (
.re (alert_fail_counts_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.alert_fail_counts.adaptp_lo_fail_count.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (alert_fail_counts_adaptp_lo_fail_count_qs)
);
// F[bucket_fail_count]: 19:16
prim_subreg_ext #(
.DW (4)
) u_alert_fail_counts_bucket_fail_count (
.re (alert_fail_counts_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.alert_fail_counts.bucket_fail_count.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (alert_fail_counts_bucket_fail_count_qs)
);
// F[markov_hi_fail_count]: 23:20
prim_subreg_ext #(
.DW (4)
) u_alert_fail_counts_markov_hi_fail_count (
.re (alert_fail_counts_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.alert_fail_counts.markov_hi_fail_count.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (alert_fail_counts_markov_hi_fail_count_qs)
);
// F[markov_lo_fail_count]: 27:24
prim_subreg_ext #(
.DW (4)
) u_alert_fail_counts_markov_lo_fail_count (
.re (alert_fail_counts_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.alert_fail_counts.markov_lo_fail_count.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (alert_fail_counts_markov_lo_fail_count_qs)
);
// F[repcnts_fail_count]: 31:28
prim_subreg_ext #(
.DW (4)
) u_alert_fail_counts_repcnts_fail_count (
.re (alert_fail_counts_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.alert_fail_counts.repcnts_fail_count.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (alert_fail_counts_repcnts_fail_count_qs)
);
// R[extht_fail_counts]: V(True)
// F[extht_hi_fail_count]: 3:0
prim_subreg_ext #(
.DW (4)
) u_extht_fail_counts_extht_hi_fail_count (
.re (extht_fail_counts_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.extht_fail_counts.extht_hi_fail_count.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (extht_fail_counts_extht_hi_fail_count_qs)
);
// F[extht_lo_fail_count]: 7:4
prim_subreg_ext #(
.DW (4)
) u_extht_fail_counts_extht_lo_fail_count (
.re (extht_fail_counts_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.extht_fail_counts.extht_lo_fail_count.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (extht_fail_counts_extht_lo_fail_count_qs)
);
// R[fw_ov_control]: V(False)
// Create REGWEN-gated WE signal
logic fw_ov_control_gated_we;
assign fw_ov_control_gated_we = fw_ov_control_we & regwen_qs;
// F[fw_ov_mode]: 3:0
prim_subreg #(
.DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (4'h9)
) u_fw_ov_control_fw_ov_mode (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (fw_ov_control_gated_we),
.wd (fw_ov_control_fw_ov_mode_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.fw_ov_control.fw_ov_mode.q),
.ds (),
// to register interface (read)
.qs (fw_ov_control_fw_ov_mode_qs)
);
// F[fw_ov_entropy_insert]: 7:4
prim_subreg #(
.DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (4'h9)
) u_fw_ov_control_fw_ov_entropy_insert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (fw_ov_control_gated_we),
.wd (fw_ov_control_fw_ov_entropy_insert_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.fw_ov_control.fw_ov_entropy_insert.q),
.ds (),
// to register interface (read)
.qs (fw_ov_control_fw_ov_entropy_insert_qs)
);
// R[fw_ov_sha3_start]: V(False)
prim_subreg #(
.DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (4'h9)
) u_fw_ov_sha3_start (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (fw_ov_sha3_start_we),
.wd (fw_ov_sha3_start_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.fw_ov_sha3_start.q),
.ds (),
// to register interface (read)
.qs (fw_ov_sha3_start_qs)
);
// R[fw_ov_wr_fifo_full]: V(True)
prim_subreg_ext #(
.DW (1)
) u_fw_ov_wr_fifo_full (
.re (fw_ov_wr_fifo_full_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.fw_ov_wr_fifo_full.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (fw_ov_wr_fifo_full_qs)
);
// R[fw_ov_rd_fifo_overflow]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_fw_ov_rd_fifo_overflow (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (fw_ov_rd_fifo_overflow_we),
.wd (fw_ov_rd_fifo_overflow_wd),
// from internal hardware
.de (hw2reg.fw_ov_rd_fifo_overflow.de),
.d (hw2reg.fw_ov_rd_fifo_overflow.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (fw_ov_rd_fifo_overflow_qs)
);
// R[fw_ov_rd_data]: V(True)
prim_subreg_ext #(
.DW (32)
) u_fw_ov_rd_data (
.re (fw_ov_rd_data_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.fw_ov_rd_data.d),
.qre (reg2hw.fw_ov_rd_data.re),
.qe (),
.q (reg2hw.fw_ov_rd_data.q),
.ds (),
.qs (fw_ov_rd_data_qs)
);
// R[fw_ov_wr_data]: V(True)
logic fw_ov_wr_data_qe;
logic [0:0] fw_ov_wr_data_flds_we;
assign fw_ov_wr_data_qe = &fw_ov_wr_data_flds_we;
prim_subreg_ext #(
.DW (32)
) u_fw_ov_wr_data (
.re (1'b0),
.we (fw_ov_wr_data_we),
.wd (fw_ov_wr_data_wd),
.d ('0),
.qre (),
.qe (fw_ov_wr_data_flds_we[0]),
.q (reg2hw.fw_ov_wr_data.q),
.ds (),
.qs ()
);
assign reg2hw.fw_ov_wr_data.qe = fw_ov_wr_data_qe;
// R[observe_fifo_thresh]: V(False)
// Create REGWEN-gated WE signal
logic observe_fifo_thresh_gated_we;
assign observe_fifo_thresh_gated_we = observe_fifo_thresh_we & regwen_qs;
prim_subreg #(
.DW (7),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (7'h20)
) u_observe_fifo_thresh (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (observe_fifo_thresh_gated_we),
.wd (observe_fifo_thresh_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.observe_fifo_thresh.q),
.ds (),
// to register interface (read)
.qs (observe_fifo_thresh_qs)
);
// R[observe_fifo_depth]: V(True)
prim_subreg_ext #(
.DW (7)
) u_observe_fifo_depth (
.re (observe_fifo_depth_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.observe_fifo_depth.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (observe_fifo_depth_qs)
);
// R[debug_status]: V(True)
// F[entropy_fifo_depth]: 2:0
prim_subreg_ext #(
.DW (3)
) u_debug_status_entropy_fifo_depth (
.re (debug_status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.debug_status.entropy_fifo_depth.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (debug_status_entropy_fifo_depth_qs)
);
// F[sha3_fsm]: 5:3
prim_subreg_ext #(
.DW (3)
) u_debug_status_sha3_fsm (
.re (debug_status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.debug_status.sha3_fsm.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (debug_status_sha3_fsm_qs)
);
// F[sha3_block_pr]: 6:6
prim_subreg_ext #(
.DW (1)
) u_debug_status_sha3_block_pr (
.re (debug_status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.debug_status.sha3_block_pr.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (debug_status_sha3_block_pr_qs)
);
// F[sha3_squeezing]: 7:7
prim_subreg_ext #(
.DW (1)
) u_debug_status_sha3_squeezing (
.re (debug_status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.debug_status.sha3_squeezing.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (debug_status_sha3_squeezing_qs)
);
// F[sha3_absorbed]: 8:8
prim_subreg_ext #(
.DW (1)
) u_debug_status_sha3_absorbed (
.re (debug_status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.debug_status.sha3_absorbed.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (debug_status_sha3_absorbed_qs)
);
// F[sha3_err]: 9:9
prim_subreg_ext #(
.DW (1)
) u_debug_status_sha3_err (
.re (debug_status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.debug_status.sha3_err.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (debug_status_sha3_err_qs)
);
// F[main_sm_idle]: 16:16
prim_subreg_ext #(
.DW (1)
) u_debug_status_main_sm_idle (
.re (debug_status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.debug_status.main_sm_idle.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (debug_status_main_sm_idle_qs)
);
// F[main_sm_boot_done]: 17:17
prim_subreg_ext #(
.DW (1)
) u_debug_status_main_sm_boot_done (
.re (debug_status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.debug_status.main_sm_boot_done.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (debug_status_main_sm_boot_done_qs)
);
// R[recov_alert_sts]: V(False)
// F[fips_enable_field_alert]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_recov_alert_sts_fips_enable_field_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
.wd (recov_alert_sts_fips_enable_field_alert_wd),
// from internal hardware
.de (hw2reg.recov_alert_sts.fips_enable_field_alert.de),
.d (hw2reg.recov_alert_sts.fips_enable_field_alert.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (recov_alert_sts_fips_enable_field_alert_qs)
);
// F[entropy_data_reg_en_field_alert]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_recov_alert_sts_entropy_data_reg_en_field_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
.wd (recov_alert_sts_entropy_data_reg_en_field_alert_wd),
// from internal hardware
.de (hw2reg.recov_alert_sts.entropy_data_reg_en_field_alert.de),
.d (hw2reg.recov_alert_sts.entropy_data_reg_en_field_alert.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (recov_alert_sts_entropy_data_reg_en_field_alert_qs)
);
// F[module_enable_field_alert]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_recov_alert_sts_module_enable_field_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
.wd (recov_alert_sts_module_enable_field_alert_wd),
// from internal hardware
.de (hw2reg.recov_alert_sts.module_enable_field_alert.de),
.d (hw2reg.recov_alert_sts.module_enable_field_alert.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (recov_alert_sts_module_enable_field_alert_qs)
);
// F[threshold_scope_field_alert]: 3:3
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_recov_alert_sts_threshold_scope_field_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
.wd (recov_alert_sts_threshold_scope_field_alert_wd),
// from internal hardware
.de (hw2reg.recov_alert_sts.threshold_scope_field_alert.de),
.d (hw2reg.recov_alert_sts.threshold_scope_field_alert.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (recov_alert_sts_threshold_scope_field_alert_qs)
);
// F[rng_bit_enable_field_alert]: 5:5
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_recov_alert_sts_rng_bit_enable_field_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
.wd (recov_alert_sts_rng_bit_enable_field_alert_wd),
// from internal hardware
.de (hw2reg.recov_alert_sts.rng_bit_enable_field_alert.de),
.d (hw2reg.recov_alert_sts.rng_bit_enable_field_alert.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (recov_alert_sts_rng_bit_enable_field_alert_qs)
);
// F[fw_ov_sha3_start_field_alert]: 7:7
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_recov_alert_sts_fw_ov_sha3_start_field_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
.wd (recov_alert_sts_fw_ov_sha3_start_field_alert_wd),
// from internal hardware
.de (hw2reg.recov_alert_sts.fw_ov_sha3_start_field_alert.de),
.d (hw2reg.recov_alert_sts.fw_ov_sha3_start_field_alert.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (recov_alert_sts_fw_ov_sha3_start_field_alert_qs)
);
// F[fw_ov_mode_field_alert]: 8:8
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_recov_alert_sts_fw_ov_mode_field_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
.wd (recov_alert_sts_fw_ov_mode_field_alert_wd),
// from internal hardware
.de (hw2reg.recov_alert_sts.fw_ov_mode_field_alert.de),
.d (hw2reg.recov_alert_sts.fw_ov_mode_field_alert.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (recov_alert_sts_fw_ov_mode_field_alert_qs)
);
// F[fw_ov_entropy_insert_field_alert]: 9:9
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_recov_alert_sts_fw_ov_entropy_insert_field_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
.wd (recov_alert_sts_fw_ov_entropy_insert_field_alert_wd),
// from internal hardware
.de (hw2reg.recov_alert_sts.fw_ov_entropy_insert_field_alert.de),
.d (hw2reg.recov_alert_sts.fw_ov_entropy_insert_field_alert.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (recov_alert_sts_fw_ov_entropy_insert_field_alert_qs)
);
// F[es_route_field_alert]: 10:10
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_recov_alert_sts_es_route_field_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
.wd (recov_alert_sts_es_route_field_alert_wd),
// from internal hardware
.de (hw2reg.recov_alert_sts.es_route_field_alert.de),
.d (hw2reg.recov_alert_sts.es_route_field_alert.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (recov_alert_sts_es_route_field_alert_qs)
);
// F[es_type_field_alert]: 11:11
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_recov_alert_sts_es_type_field_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
.wd (recov_alert_sts_es_type_field_alert_wd),
// from internal hardware
.de (hw2reg.recov_alert_sts.es_type_field_alert.de),
.d (hw2reg.recov_alert_sts.es_type_field_alert.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (recov_alert_sts_es_type_field_alert_qs)
);
// F[es_main_sm_alert]: 12:12
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_recov_alert_sts_es_main_sm_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
.wd (recov_alert_sts_es_main_sm_alert_wd),
// from internal hardware
.de (hw2reg.recov_alert_sts.es_main_sm_alert.de),
.d (hw2reg.recov_alert_sts.es_main_sm_alert.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (recov_alert_sts_es_main_sm_alert_qs)
);
// F[es_bus_cmp_alert]: 13:13
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_recov_alert_sts_es_bus_cmp_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
.wd (recov_alert_sts_es_bus_cmp_alert_wd),
// from internal hardware
.de (hw2reg.recov_alert_sts.es_bus_cmp_alert.de),
.d (hw2reg.recov_alert_sts.es_bus_cmp_alert.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (recov_alert_sts_es_bus_cmp_alert_qs)
);
// F[es_thresh_cfg_alert]: 14:14
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_recov_alert_sts_es_thresh_cfg_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
.wd (recov_alert_sts_es_thresh_cfg_alert_wd),
// from internal hardware
.de (hw2reg.recov_alert_sts.es_thresh_cfg_alert.de),
.d (hw2reg.recov_alert_sts.es_thresh_cfg_alert.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (recov_alert_sts_es_thresh_cfg_alert_qs)
);
// F[es_fw_ov_wr_alert]: 15:15
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_recov_alert_sts_es_fw_ov_wr_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
.wd (recov_alert_sts_es_fw_ov_wr_alert_wd),
// from internal hardware
.de (hw2reg.recov_alert_sts.es_fw_ov_wr_alert.de),
.d (hw2reg.recov_alert_sts.es_fw_ov_wr_alert.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (recov_alert_sts_es_fw_ov_wr_alert_qs)
);
// F[es_fw_ov_disable_alert]: 16:16
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h0)
) u_recov_alert_sts_es_fw_ov_disable_alert (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (recov_alert_sts_we),
.wd (recov_alert_sts_es_fw_ov_disable_alert_wd),
// from internal hardware
.de (hw2reg.recov_alert_sts.es_fw_ov_disable_alert.de),
.d (hw2reg.recov_alert_sts.es_fw_ov_disable_alert.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (recov_alert_sts_es_fw_ov_disable_alert_qs)
);
// R[err_code]: V(False)
// F[sfifo_esrng_err]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_err_code_sfifo_esrng_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_esrng_err.de),
.d (hw2reg.err_code.sfifo_esrng_err.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (err_code_sfifo_esrng_err_qs)
);
// F[sfifo_observe_err]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_err_code_sfifo_observe_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_observe_err.de),
.d (hw2reg.err_code.sfifo_observe_err.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (err_code_sfifo_observe_err_qs)
);
// F[sfifo_esfinal_err]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_err_code_sfifo_esfinal_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_esfinal_err.de),
.d (hw2reg.err_code.sfifo_esfinal_err.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (err_code_sfifo_esfinal_err_qs)
);
// F[es_ack_sm_err]: 20:20
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_err_code_es_ack_sm_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.err_code.es_ack_sm_err.de),
.d (hw2reg.err_code.es_ack_sm_err.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (err_code_es_ack_sm_err_qs)
);
// F[es_main_sm_err]: 21:21
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_err_code_es_main_sm_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.err_code.es_main_sm_err.de),
.d (hw2reg.err_code.es_main_sm_err.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (err_code_es_main_sm_err_qs)
);
// F[es_cntr_err]: 22:22
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_err_code_es_cntr_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.err_code.es_cntr_err.de),
.d (hw2reg.err_code.es_cntr_err.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (err_code_es_cntr_err_qs)
);
// F[sha3_state_err]: 23:23
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_err_code_sha3_state_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.err_code.sha3_state_err.de),
.d (hw2reg.err_code.sha3_state_err.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (err_code_sha3_state_err_qs)
);
// F[sha3_rst_storage_err]: 24:24
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_err_code_sha3_rst_storage_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.err_code.sha3_rst_storage_err.de),
.d (hw2reg.err_code.sha3_rst_storage_err.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (err_code_sha3_rst_storage_err_qs)
);
// F[fifo_write_err]: 28:28
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_err_code_fifo_write_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.err_code.fifo_write_err.de),
.d (hw2reg.err_code.fifo_write_err.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (err_code_fifo_write_err_qs)
);
// F[fifo_read_err]: 29:29
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_err_code_fifo_read_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.err_code.fifo_read_err.de),
.d (hw2reg.err_code.fifo_read_err.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (err_code_fifo_read_err_qs)
);
// F[fifo_state_err]: 30:30
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
) u_err_code_fifo_state_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.err_code.fifo_state_err.de),
.d (hw2reg.err_code.fifo_state_err.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (err_code_fifo_state_err_qs)
);
// R[err_code_test]: V(False)
logic err_code_test_qe;
logic [0:0] err_code_test_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_err_code_test0_qe (
.clk_i(clk_i),
.rst_ni(rst_ni),
.d_i(&err_code_test_flds_we),
.q_o(err_code_test_qe)
);
prim_subreg #(
.DW (5),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (5'h0)
) u_err_code_test (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (err_code_test_we),
.wd (err_code_test_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (err_code_test_flds_we[0]),
.q (reg2hw.err_code_test.q),
.ds (),
// to register interface (read)
.qs (err_code_test_qs)
);
assign reg2hw.err_code_test.qe = err_code_test_qe;
// R[main_sm_state]: V(False)
prim_subreg #(
.DW (9),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (9'hf5)
) u_main_sm_state (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.main_sm_state.de),
.d (hw2reg.main_sm_state.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (main_sm_state_qs)
);
logic [56:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == ENTROPY_SRC_INTR_STATE_OFFSET);
addr_hit[ 1] = (reg_addr == ENTROPY_SRC_INTR_ENABLE_OFFSET);
addr_hit[ 2] = (reg_addr == ENTROPY_SRC_INTR_TEST_OFFSET);
addr_hit[ 3] = (reg_addr == ENTROPY_SRC_ALERT_TEST_OFFSET);
addr_hit[ 4] = (reg_addr == ENTROPY_SRC_ME_REGWEN_OFFSET);
addr_hit[ 5] = (reg_addr == ENTROPY_SRC_SW_REGUPD_OFFSET);
addr_hit[ 6] = (reg_addr == ENTROPY_SRC_REGWEN_OFFSET);
addr_hit[ 7] = (reg_addr == ENTROPY_SRC_REV_OFFSET);
addr_hit[ 8] = (reg_addr == ENTROPY_SRC_MODULE_ENABLE_OFFSET);
addr_hit[ 9] = (reg_addr == ENTROPY_SRC_CONF_OFFSET);
addr_hit[10] = (reg_addr == ENTROPY_SRC_ENTROPY_CONTROL_OFFSET);
addr_hit[11] = (reg_addr == ENTROPY_SRC_ENTROPY_DATA_OFFSET);
addr_hit[12] = (reg_addr == ENTROPY_SRC_HEALTH_TEST_WINDOWS_OFFSET);
addr_hit[13] = (reg_addr == ENTROPY_SRC_REPCNT_THRESHOLDS_OFFSET);
addr_hit[14] = (reg_addr == ENTROPY_SRC_REPCNTS_THRESHOLDS_OFFSET);
addr_hit[15] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_OFFSET);
addr_hit[16] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_OFFSET);
addr_hit[17] = (reg_addr == ENTROPY_SRC_BUCKET_THRESHOLDS_OFFSET);
addr_hit[18] = (reg_addr == ENTROPY_SRC_MARKOV_HI_THRESHOLDS_OFFSET);
addr_hit[19] = (reg_addr == ENTROPY_SRC_MARKOV_LO_THRESHOLDS_OFFSET);
addr_hit[20] = (reg_addr == ENTROPY_SRC_EXTHT_HI_THRESHOLDS_OFFSET);
addr_hit[21] = (reg_addr == ENTROPY_SRC_EXTHT_LO_THRESHOLDS_OFFSET);
addr_hit[22] = (reg_addr == ENTROPY_SRC_REPCNT_HI_WATERMARKS_OFFSET);
addr_hit[23] = (reg_addr == ENTROPY_SRC_REPCNTS_HI_WATERMARKS_OFFSET);
addr_hit[24] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_WATERMARKS_OFFSET);
addr_hit[25] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_WATERMARKS_OFFSET);
addr_hit[26] = (reg_addr == ENTROPY_SRC_EXTHT_HI_WATERMARKS_OFFSET);
addr_hit[27] = (reg_addr == ENTROPY_SRC_EXTHT_LO_WATERMARKS_OFFSET);
addr_hit[28] = (reg_addr == ENTROPY_SRC_BUCKET_HI_WATERMARKS_OFFSET);
addr_hit[29] = (reg_addr == ENTROPY_SRC_MARKOV_HI_WATERMARKS_OFFSET);
addr_hit[30] = (reg_addr == ENTROPY_SRC_MARKOV_LO_WATERMARKS_OFFSET);
addr_hit[31] = (reg_addr == ENTROPY_SRC_REPCNT_TOTAL_FAILS_OFFSET);
addr_hit[32] = (reg_addr == ENTROPY_SRC_REPCNTS_TOTAL_FAILS_OFFSET);
addr_hit[33] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_OFFSET);
addr_hit[34] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_OFFSET);
addr_hit[35] = (reg_addr == ENTROPY_SRC_BUCKET_TOTAL_FAILS_OFFSET);
addr_hit[36] = (reg_addr == ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS_OFFSET);
addr_hit[37] = (reg_addr == ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS_OFFSET);
addr_hit[38] = (reg_addr == ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_OFFSET);
addr_hit[39] = (reg_addr == ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_OFFSET);
addr_hit[40] = (reg_addr == ENTROPY_SRC_ALERT_THRESHOLD_OFFSET);
addr_hit[41] = (reg_addr == ENTROPY_SRC_ALERT_SUMMARY_FAIL_COUNTS_OFFSET);
addr_hit[42] = (reg_addr == ENTROPY_SRC_ALERT_FAIL_COUNTS_OFFSET);
addr_hit[43] = (reg_addr == ENTROPY_SRC_EXTHT_FAIL_COUNTS_OFFSET);
addr_hit[44] = (reg_addr == ENTROPY_SRC_FW_OV_CONTROL_OFFSET);
addr_hit[45] = (reg_addr == ENTROPY_SRC_FW_OV_SHA3_START_OFFSET);
addr_hit[46] = (reg_addr == ENTROPY_SRC_FW_OV_WR_FIFO_FULL_OFFSET);
addr_hit[47] = (reg_addr == ENTROPY_SRC_FW_OV_RD_FIFO_OVERFLOW_OFFSET);
addr_hit[48] = (reg_addr == ENTROPY_SRC_FW_OV_RD_DATA_OFFSET);
addr_hit[49] = (reg_addr == ENTROPY_SRC_FW_OV_WR_DATA_OFFSET);
addr_hit[50] = (reg_addr == ENTROPY_SRC_OBSERVE_FIFO_THRESH_OFFSET);
addr_hit[51] = (reg_addr == ENTROPY_SRC_OBSERVE_FIFO_DEPTH_OFFSET);
addr_hit[52] = (reg_addr == ENTROPY_SRC_DEBUG_STATUS_OFFSET);
addr_hit[53] = (reg_addr == ENTROPY_SRC_RECOV_ALERT_STS_OFFSET);
addr_hit[54] = (reg_addr == ENTROPY_SRC_ERR_CODE_OFFSET);
addr_hit[55] = (reg_addr == ENTROPY_SRC_ERR_CODE_TEST_OFFSET);
addr_hit[56] = (reg_addr == ENTROPY_SRC_MAIN_SM_STATE_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
// Check sub-word write is permitted
always_comb begin
wr_err = (reg_we &
((addr_hit[ 0] & (|(ENTROPY_SRC_PERMIT[ 0] & ~reg_be))) |
(addr_hit[ 1] & (|(ENTROPY_SRC_PERMIT[ 1] & ~reg_be))) |
(addr_hit[ 2] & (|(ENTROPY_SRC_PERMIT[ 2] & ~reg_be))) |
(addr_hit[ 3] & (|(ENTROPY_SRC_PERMIT[ 3] & ~reg_be))) |
(addr_hit[ 4] & (|(ENTROPY_SRC_PERMIT[ 4] & ~reg_be))) |
(addr_hit[ 5] & (|(ENTROPY_SRC_PERMIT[ 5] & ~reg_be))) |
(addr_hit[ 6] & (|(ENTROPY_SRC_PERMIT[ 6] & ~reg_be))) |
(addr_hit[ 7] & (|(ENTROPY_SRC_PERMIT[ 7] & ~reg_be))) |
(addr_hit[ 8] & (|(ENTROPY_SRC_PERMIT[ 8] & ~reg_be))) |
(addr_hit[ 9] & (|(ENTROPY_SRC_PERMIT[ 9] & ~reg_be))) |
(addr_hit[10] & (|(ENTROPY_SRC_PERMIT[10] & ~reg_be))) |
(addr_hit[11] & (|(ENTROPY_SRC_PERMIT[11] & ~reg_be))) |
(addr_hit[12] & (|(ENTROPY_SRC_PERMIT[12] & ~reg_be))) |
(addr_hit[13] & (|(ENTROPY_SRC_PERMIT[13] & ~reg_be))) |
(addr_hit[14] & (|(ENTROPY_SRC_PERMIT[14] & ~reg_be))) |
(addr_hit[15] & (|(ENTROPY_SRC_PERMIT[15] & ~reg_be))) |
(addr_hit[16] & (|(ENTROPY_SRC_PERMIT[16] & ~reg_be))) |
(addr_hit[17] & (|(ENTROPY_SRC_PERMIT[17] & ~reg_be))) |
(addr_hit[18] & (|(ENTROPY_SRC_PERMIT[18] & ~reg_be))) |
(addr_hit[19] & (|(ENTROPY_SRC_PERMIT[19] & ~reg_be))) |
(addr_hit[20] & (|(ENTROPY_SRC_PERMIT[20] & ~reg_be))) |
(addr_hit[21] & (|(ENTROPY_SRC_PERMIT[21] & ~reg_be))) |
(addr_hit[22] & (|(ENTROPY_SRC_PERMIT[22] & ~reg_be))) |
(addr_hit[23] & (|(ENTROPY_SRC_PERMIT[23] & ~reg_be))) |
(addr_hit[24] & (|(ENTROPY_SRC_PERMIT[24] & ~reg_be))) |
(addr_hit[25] & (|(ENTROPY_SRC_PERMIT[25] & ~reg_be))) |
(addr_hit[26] & (|(ENTROPY_SRC_PERMIT[26] & ~reg_be))) |
(addr_hit[27] & (|(ENTROPY_SRC_PERMIT[27] & ~reg_be))) |
(addr_hit[28] & (|(ENTROPY_SRC_PERMIT[28] & ~reg_be))) |
(addr_hit[29] & (|(ENTROPY_SRC_PERMIT[29] & ~reg_be))) |
(addr_hit[30] & (|(ENTROPY_SRC_PERMIT[30] & ~reg_be))) |
(addr_hit[31] & (|(ENTROPY_SRC_PERMIT[31] & ~reg_be))) |
(addr_hit[32] & (|(ENTROPY_SRC_PERMIT[32] & ~reg_be))) |
(addr_hit[33] & (|(ENTROPY_SRC_PERMIT[33] & ~reg_be))) |
(addr_hit[34] & (|(ENTROPY_SRC_PERMIT[34] & ~reg_be))) |
(addr_hit[35] & (|(ENTROPY_SRC_PERMIT[35] & ~reg_be))) |
(addr_hit[36] & (|(ENTROPY_SRC_PERMIT[36] & ~reg_be))) |
(addr_hit[37] & (|(ENTROPY_SRC_PERMIT[37] & ~reg_be))) |
(addr_hit[38] & (|(ENTROPY_SRC_PERMIT[38] & ~reg_be))) |
(addr_hit[39] & (|(ENTROPY_SRC_PERMIT[39] & ~reg_be))) |
(addr_hit[40] & (|(ENTROPY_SRC_PERMIT[40] & ~reg_be))) |
(addr_hit[41] & (|(ENTROPY_SRC_PERMIT[41] & ~reg_be))) |
(addr_hit[42] & (|(ENTROPY_SRC_PERMIT[42] & ~reg_be))) |
(addr_hit[43] & (|(ENTROPY_SRC_PERMIT[43] & ~reg_be))) |
(addr_hit[44] & (|(ENTROPY_SRC_PERMIT[44] & ~reg_be))) |
(addr_hit[45] & (|(ENTROPY_SRC_PERMIT[45] & ~reg_be))) |
(addr_hit[46] & (|(ENTROPY_SRC_PERMIT[46] & ~reg_be))) |
(addr_hit[47] & (|(ENTROPY_SRC_PERMIT[47] & ~reg_be))) |
(addr_hit[48] & (|(ENTROPY_SRC_PERMIT[48] & ~reg_be))) |
(addr_hit[49] & (|(ENTROPY_SRC_PERMIT[49] & ~reg_be))) |
(addr_hit[50] & (|(ENTROPY_SRC_PERMIT[50] & ~reg_be))) |
(addr_hit[51] & (|(ENTROPY_SRC_PERMIT[51] & ~reg_be))) |
(addr_hit[52] & (|(ENTROPY_SRC_PERMIT[52] & ~reg_be))) |
(addr_hit[53] & (|(ENTROPY_SRC_PERMIT[53] & ~reg_be))) |
(addr_hit[54] & (|(ENTROPY_SRC_PERMIT[54] & ~reg_be))) |
(addr_hit[55] & (|(ENTROPY_SRC_PERMIT[55] & ~reg_be))) |
(addr_hit[56] & (|(ENTROPY_SRC_PERMIT[56] & ~reg_be)))));
end
// Generate write-enables
assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
assign intr_state_es_entropy_valid_wd = reg_wdata[0];
assign intr_state_es_health_test_failed_wd = reg_wdata[1];
assign intr_state_es_observe_fifo_ready_wd = reg_wdata[2];
assign intr_state_es_fatal_err_wd = reg_wdata[3];
assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
assign intr_enable_es_entropy_valid_wd = reg_wdata[0];
assign intr_enable_es_health_test_failed_wd = reg_wdata[1];
assign intr_enable_es_observe_fifo_ready_wd = reg_wdata[2];
assign intr_enable_es_fatal_err_wd = reg_wdata[3];
assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
assign intr_test_es_entropy_valid_wd = reg_wdata[0];
assign intr_test_es_health_test_failed_wd = reg_wdata[1];
assign intr_test_es_observe_fifo_ready_wd = reg_wdata[2];
assign intr_test_es_fatal_err_wd = reg_wdata[3];
assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
assign alert_test_recov_alert_wd = reg_wdata[0];
assign alert_test_fatal_alert_wd = reg_wdata[1];
assign me_regwen_we = addr_hit[4] & reg_we & !reg_error;
assign me_regwen_wd = reg_wdata[0];
assign sw_regupd_we = addr_hit[5] & reg_we & !reg_error;
assign sw_regupd_wd = reg_wdata[0];
assign module_enable_we = addr_hit[8] & reg_we & !reg_error;
assign module_enable_wd = reg_wdata[3:0];
assign conf_we = addr_hit[9] & reg_we & !reg_error;
assign conf_fips_enable_wd = reg_wdata[3:0];
assign conf_entropy_data_reg_enable_wd = reg_wdata[7:4];
assign conf_threshold_scope_wd = reg_wdata[15:12];
assign conf_rng_bit_enable_wd = reg_wdata[23:20];
assign conf_rng_bit_sel_wd = reg_wdata[25:24];
assign entropy_control_we = addr_hit[10] & reg_we & !reg_error;
assign entropy_control_es_route_wd = reg_wdata[3:0];
assign entropy_control_es_type_wd = reg_wdata[7:4];
assign entropy_data_re = addr_hit[11] & reg_re & !reg_error;
assign health_test_windows_we = addr_hit[12] & reg_we & !reg_error;
assign health_test_windows_fips_window_wd = reg_wdata[15:0];
assign health_test_windows_bypass_window_wd = reg_wdata[31:16];
assign repcnt_thresholds_re = addr_hit[13] & reg_re & !reg_error;
assign repcnt_thresholds_we = addr_hit[13] & reg_we & !reg_error;
assign repcnt_thresholds_fips_thresh_wd = reg_wdata[15:0];
assign repcnt_thresholds_bypass_thresh_wd = reg_wdata[31:16];
assign repcnts_thresholds_re = addr_hit[14] & reg_re & !reg_error;
assign repcnts_thresholds_we = addr_hit[14] & reg_we & !reg_error;
assign repcnts_thresholds_fips_thresh_wd = reg_wdata[15:0];
assign repcnts_thresholds_bypass_thresh_wd = reg_wdata[31:16];
assign adaptp_hi_thresholds_re = addr_hit[15] & reg_re & !reg_error;
assign adaptp_hi_thresholds_we = addr_hit[15] & reg_we & !reg_error;
assign adaptp_hi_thresholds_fips_thresh_wd = reg_wdata[15:0];
assign adaptp_hi_thresholds_bypass_thresh_wd = reg_wdata[31:16];
assign adaptp_lo_thresholds_re = addr_hit[16] & reg_re & !reg_error;
assign adaptp_lo_thresholds_we = addr_hit[16] & reg_we & !reg_error;
assign adaptp_lo_thresholds_fips_thresh_wd = reg_wdata[15:0];
assign adaptp_lo_thresholds_bypass_thresh_wd = reg_wdata[31:16];
assign bucket_thresholds_re = addr_hit[17] & reg_re & !reg_error;
assign bucket_thresholds_we = addr_hit[17] & reg_we & !reg_error;
assign bucket_thresholds_fips_thresh_wd = reg_wdata[15:0];
assign bucket_thresholds_bypass_thresh_wd = reg_wdata[31:16];
assign markov_hi_thresholds_re = addr_hit[18] & reg_re & !reg_error;
assign markov_hi_thresholds_we = addr_hit[18] & reg_we & !reg_error;
assign markov_hi_thresholds_fips_thresh_wd = reg_wdata[15:0];
assign markov_hi_thresholds_bypass_thresh_wd = reg_wdata[31:16];
assign markov_lo_thresholds_re = addr_hit[19] & reg_re & !reg_error;
assign markov_lo_thresholds_we = addr_hit[19] & reg_we & !reg_error;
assign markov_lo_thresholds_fips_thresh_wd = reg_wdata[15:0];
assign markov_lo_thresholds_bypass_thresh_wd = reg_wdata[31:16];
assign extht_hi_thresholds_re = addr_hit[20] & reg_re & !reg_error;
assign extht_hi_thresholds_we = addr_hit[20] & reg_we & !reg_error;
assign extht_hi_thresholds_fips_thresh_wd = reg_wdata[15:0];
assign extht_hi_thresholds_bypass_thresh_wd = reg_wdata[31:16];
assign extht_lo_thresholds_re = addr_hit[21] & reg_re & !reg_error;
assign extht_lo_thresholds_we = addr_hit[21] & reg_we & !reg_error;
assign extht_lo_thresholds_fips_thresh_wd = reg_wdata[15:0];
assign extht_lo_thresholds_bypass_thresh_wd = reg_wdata[31:16];
assign repcnt_hi_watermarks_re = addr_hit[22] & reg_re & !reg_error;
assign repcnts_hi_watermarks_re = addr_hit[23] & reg_re & !reg_error;
assign adaptp_hi_watermarks_re = addr_hit[24] & reg_re & !reg_error;
assign adaptp_lo_watermarks_re = addr_hit[25] & reg_re & !reg_error;
assign extht_hi_watermarks_re = addr_hit[26] & reg_re & !reg_error;
assign extht_lo_watermarks_re = addr_hit[27] & reg_re & !reg_error;
assign bucket_hi_watermarks_re = addr_hit[28] & reg_re & !reg_error;
assign markov_hi_watermarks_re = addr_hit[29] & reg_re & !reg_error;
assign markov_lo_watermarks_re = addr_hit[30] & reg_re & !reg_error;
assign repcnt_total_fails_re = addr_hit[31] & reg_re & !reg_error;
assign repcnts_total_fails_re = addr_hit[32] & reg_re & !reg_error;
assign adaptp_hi_total_fails_re = addr_hit[33] & reg_re & !reg_error;
assign adaptp_lo_total_fails_re = addr_hit[34] & reg_re & !reg_error;
assign bucket_total_fails_re = addr_hit[35] & reg_re & !reg_error;
assign markov_hi_total_fails_re = addr_hit[36] & reg_re & !reg_error;
assign markov_lo_total_fails_re = addr_hit[37] & reg_re & !reg_error;
assign extht_hi_total_fails_re = addr_hit[38] & reg_re & !reg_error;
assign extht_lo_total_fails_re = addr_hit[39] & reg_re & !reg_error;
assign alert_threshold_we = addr_hit[40] & reg_we & !reg_error;
assign alert_threshold_alert_threshold_wd = reg_wdata[15:0];
assign alert_threshold_alert_threshold_inv_wd = reg_wdata[31:16];
assign alert_summary_fail_counts_re = addr_hit[41] & reg_re & !reg_error;
assign alert_fail_counts_re = addr_hit[42] & reg_re & !reg_error;
assign extht_fail_counts_re = addr_hit[43] & reg_re & !reg_error;
assign fw_ov_control_we = addr_hit[44] & reg_we & !reg_error;
assign fw_ov_control_fw_ov_mode_wd = reg_wdata[3:0];
assign fw_ov_control_fw_ov_entropy_insert_wd = reg_wdata[7:4];
assign fw_ov_sha3_start_we = addr_hit[45] & reg_we & !reg_error;
assign fw_ov_sha3_start_wd = reg_wdata[3:0];
assign fw_ov_wr_fifo_full_re = addr_hit[46] & reg_re & !reg_error;
assign fw_ov_rd_fifo_overflow_we = addr_hit[47] & reg_we & !reg_error;
assign fw_ov_rd_fifo_overflow_wd = reg_wdata[0];
assign fw_ov_rd_data_re = addr_hit[48] & reg_re & !reg_error;
assign fw_ov_wr_data_we = addr_hit[49] & reg_we & !reg_error;
assign fw_ov_wr_data_wd = reg_wdata[31:0];
assign observe_fifo_thresh_we = addr_hit[50] & reg_we & !reg_error;
assign observe_fifo_thresh_wd = reg_wdata[6:0];
assign observe_fifo_depth_re = addr_hit[51] & reg_re & !reg_error;
assign debug_status_re = addr_hit[52] & reg_re & !reg_error;
assign recov_alert_sts_we = addr_hit[53] & reg_we & !reg_error;
assign recov_alert_sts_fips_enable_field_alert_wd = reg_wdata[0];
assign recov_alert_sts_entropy_data_reg_en_field_alert_wd = reg_wdata[1];
assign recov_alert_sts_module_enable_field_alert_wd = reg_wdata[2];
assign recov_alert_sts_threshold_scope_field_alert_wd = reg_wdata[3];
assign recov_alert_sts_rng_bit_enable_field_alert_wd = reg_wdata[5];
assign recov_alert_sts_fw_ov_sha3_start_field_alert_wd = reg_wdata[7];
assign recov_alert_sts_fw_ov_mode_field_alert_wd = reg_wdata[8];
assign recov_alert_sts_fw_ov_entropy_insert_field_alert_wd = reg_wdata[9];
assign recov_alert_sts_es_route_field_alert_wd = reg_wdata[10];
assign recov_alert_sts_es_type_field_alert_wd = reg_wdata[11];
assign recov_alert_sts_es_main_sm_alert_wd = reg_wdata[12];
assign recov_alert_sts_es_bus_cmp_alert_wd = reg_wdata[13];
assign recov_alert_sts_es_thresh_cfg_alert_wd = reg_wdata[14];
assign recov_alert_sts_es_fw_ov_wr_alert_wd = reg_wdata[15];
assign recov_alert_sts_es_fw_ov_disable_alert_wd = reg_wdata[16];
assign err_code_test_we = addr_hit[55] & reg_we & !reg_error;
assign err_code_test_wd = reg_wdata[4:0];
// Assign write-enables to checker logic vector.
always_comb begin
reg_we_check = '0;
reg_we_check[0] = intr_state_we;
reg_we_check[1] = intr_enable_we;
reg_we_check[2] = intr_test_we;
reg_we_check[3] = alert_test_we;
reg_we_check[4] = me_regwen_we;
reg_we_check[5] = sw_regupd_we;
reg_we_check[6] = 1'b0;
reg_we_check[7] = 1'b0;
reg_we_check[8] = module_enable_gated_we;
reg_we_check[9] = conf_gated_we;
reg_we_check[10] = entropy_control_gated_we;
reg_we_check[11] = 1'b0;
reg_we_check[12] = health_test_windows_gated_we;
reg_we_check[13] = repcnt_thresholds_gated_we;
reg_we_check[14] = repcnts_thresholds_gated_we;
reg_we_check[15] = adaptp_hi_thresholds_gated_we;
reg_we_check[16] = adaptp_lo_thresholds_gated_we;
reg_we_check[17] = bucket_thresholds_gated_we;
reg_we_check[18] = markov_hi_thresholds_gated_we;
reg_we_check[19] = markov_lo_thresholds_gated_we;
reg_we_check[20] = extht_hi_thresholds_gated_we;
reg_we_check[21] = extht_lo_thresholds_gated_we;
reg_we_check[22] = 1'b0;
reg_we_check[23] = 1'b0;
reg_we_check[24] = 1'b0;
reg_we_check[25] = 1'b0;
reg_we_check[26] = 1'b0;
reg_we_check[27] = 1'b0;
reg_we_check[28] = 1'b0;
reg_we_check[29] = 1'b0;
reg_we_check[30] = 1'b0;
reg_we_check[31] = 1'b0;
reg_we_check[32] = 1'b0;
reg_we_check[33] = 1'b0;
reg_we_check[34] = 1'b0;
reg_we_check[35] = 1'b0;
reg_we_check[36] = 1'b0;
reg_we_check[37] = 1'b0;
reg_we_check[38] = 1'b0;
reg_we_check[39] = 1'b0;
reg_we_check[40] = alert_threshold_gated_we;
reg_we_check[41] = 1'b0;
reg_we_check[42] = 1'b0;
reg_we_check[43] = 1'b0;
reg_we_check[44] = fw_ov_control_gated_we;
reg_we_check[45] = fw_ov_sha3_start_we;
reg_we_check[46] = 1'b0;
reg_we_check[47] = fw_ov_rd_fifo_overflow_we;
reg_we_check[48] = 1'b0;
reg_we_check[49] = fw_ov_wr_data_we;
reg_we_check[50] = observe_fifo_thresh_gated_we;
reg_we_check[51] = 1'b0;
reg_we_check[52] = 1'b0;
reg_we_check[53] = recov_alert_sts_we;
reg_we_check[54] = 1'b0;
reg_we_check[55] = err_code_test_we;
reg_we_check[56] = 1'b0;
end
// Read data return
always_comb begin
reg_rdata_next = '0;
unique case (1'b1)
addr_hit[0]: begin
reg_rdata_next[0] = intr_state_es_entropy_valid_qs;
reg_rdata_next[1] = intr_state_es_health_test_failed_qs;
reg_rdata_next[2] = intr_state_es_observe_fifo_ready_qs;
reg_rdata_next[3] = intr_state_es_fatal_err_qs;
end
addr_hit[1]: begin
reg_rdata_next[0] = intr_enable_es_entropy_valid_qs;
reg_rdata_next[1] = intr_enable_es_health_test_failed_qs;
reg_rdata_next[2] = intr_enable_es_observe_fifo_ready_qs;
reg_rdata_next[3] = intr_enable_es_fatal_err_qs;
end
addr_hit[2]: begin
reg_rdata_next[0] = '0;
reg_rdata_next[1] = '0;
reg_rdata_next[2] = '0;
reg_rdata_next[3] = '0;
end
addr_hit[3]: begin
reg_rdata_next[0] = '0;
reg_rdata_next[1] = '0;
end
addr_hit[4]: begin
reg_rdata_next[0] = me_regwen_qs;
end
addr_hit[5]: begin
reg_rdata_next[0] = sw_regupd_qs;
end
addr_hit[6]: begin
reg_rdata_next[0] = regwen_qs;
end
addr_hit[7]: begin
reg_rdata_next[7:0] = rev_abi_revision_qs;
reg_rdata_next[15:8] = rev_hw_revision_qs;
reg_rdata_next[23:16] = rev_chip_type_qs;
end
addr_hit[8]: begin
reg_rdata_next[3:0] = module_enable_qs;
end
addr_hit[9]: begin
reg_rdata_next[3:0] = conf_fips_enable_qs;
reg_rdata_next[7:4] = conf_entropy_data_reg_enable_qs;
reg_rdata_next[15:12] = conf_threshold_scope_qs;
reg_rdata_next[23:20] = conf_rng_bit_enable_qs;
reg_rdata_next[25:24] = conf_rng_bit_sel_qs;
end
addr_hit[10]: begin
reg_rdata_next[3:0] = entropy_control_es_route_qs;
reg_rdata_next[7:4] = entropy_control_es_type_qs;
end
addr_hit[11]: begin
reg_rdata_next[31:0] = entropy_data_qs;
end
addr_hit[12]: begin
reg_rdata_next[15:0] = health_test_windows_fips_window_qs;
reg_rdata_next[31:16] = health_test_windows_bypass_window_qs;
end
addr_hit[13]: begin
reg_rdata_next[15:0] = repcnt_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = repcnt_thresholds_bypass_thresh_qs;
end
addr_hit[14]: begin
reg_rdata_next[15:0] = repcnts_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = repcnts_thresholds_bypass_thresh_qs;
end
addr_hit[15]: begin
reg_rdata_next[15:0] = adaptp_hi_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = adaptp_hi_thresholds_bypass_thresh_qs;
end
addr_hit[16]: begin
reg_rdata_next[15:0] = adaptp_lo_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = adaptp_lo_thresholds_bypass_thresh_qs;
end
addr_hit[17]: begin
reg_rdata_next[15:0] = bucket_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = bucket_thresholds_bypass_thresh_qs;
end
addr_hit[18]: begin
reg_rdata_next[15:0] = markov_hi_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = markov_hi_thresholds_bypass_thresh_qs;
end
addr_hit[19]: begin
reg_rdata_next[15:0] = markov_lo_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = markov_lo_thresholds_bypass_thresh_qs;
end
addr_hit[20]: begin
reg_rdata_next[15:0] = extht_hi_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = extht_hi_thresholds_bypass_thresh_qs;
end
addr_hit[21]: begin
reg_rdata_next[15:0] = extht_lo_thresholds_fips_thresh_qs;
reg_rdata_next[31:16] = extht_lo_thresholds_bypass_thresh_qs;
end
addr_hit[22]: begin
reg_rdata_next[15:0] = repcnt_hi_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = repcnt_hi_watermarks_bypass_watermark_qs;
end
addr_hit[23]: begin
reg_rdata_next[15:0] = repcnts_hi_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = repcnts_hi_watermarks_bypass_watermark_qs;
end
addr_hit[24]: begin
reg_rdata_next[15:0] = adaptp_hi_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = adaptp_hi_watermarks_bypass_watermark_qs;
end
addr_hit[25]: begin
reg_rdata_next[15:0] = adaptp_lo_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = adaptp_lo_watermarks_bypass_watermark_qs;
end
addr_hit[26]: begin
reg_rdata_next[15:0] = extht_hi_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = extht_hi_watermarks_bypass_watermark_qs;
end
addr_hit[27]: begin
reg_rdata_next[15:0] = extht_lo_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = extht_lo_watermarks_bypass_watermark_qs;
end
addr_hit[28]: begin
reg_rdata_next[15:0] = bucket_hi_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = bucket_hi_watermarks_bypass_watermark_qs;
end
addr_hit[29]: begin
reg_rdata_next[15:0] = markov_hi_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = markov_hi_watermarks_bypass_watermark_qs;
end
addr_hit[30]: begin
reg_rdata_next[15:0] = markov_lo_watermarks_fips_watermark_qs;
reg_rdata_next[31:16] = markov_lo_watermarks_bypass_watermark_qs;
end
addr_hit[31]: begin
reg_rdata_next[31:0] = repcnt_total_fails_qs;
end
addr_hit[32]: begin
reg_rdata_next[31:0] = repcnts_total_fails_qs;
end
addr_hit[33]: begin
reg_rdata_next[31:0] = adaptp_hi_total_fails_qs;
end
addr_hit[34]: begin
reg_rdata_next[31:0] = adaptp_lo_total_fails_qs;
end
addr_hit[35]: begin
reg_rdata_next[31:0] = bucket_total_fails_qs;
end
addr_hit[36]: begin
reg_rdata_next[31:0] = markov_hi_total_fails_qs;
end
addr_hit[37]: begin
reg_rdata_next[31:0] = markov_lo_total_fails_qs;
end
addr_hit[38]: begin
reg_rdata_next[31:0] = extht_hi_total_fails_qs;
end
addr_hit[39]: begin
reg_rdata_next[31:0] = extht_lo_total_fails_qs;
end
addr_hit[40]: begin
reg_rdata_next[15:0] = alert_threshold_alert_threshold_qs;
reg_rdata_next[31:16] = alert_threshold_alert_threshold_inv_qs;
end
addr_hit[41]: begin
reg_rdata_next[15:0] = alert_summary_fail_counts_qs;
end
addr_hit[42]: begin
reg_rdata_next[7:4] = alert_fail_counts_repcnt_fail_count_qs;
reg_rdata_next[11:8] = alert_fail_counts_adaptp_hi_fail_count_qs;
reg_rdata_next[15:12] = alert_fail_counts_adaptp_lo_fail_count_qs;
reg_rdata_next[19:16] = alert_fail_counts_bucket_fail_count_qs;
reg_rdata_next[23:20] = alert_fail_counts_markov_hi_fail_count_qs;
reg_rdata_next[27:24] = alert_fail_counts_markov_lo_fail_count_qs;
reg_rdata_next[31:28] = alert_fail_counts_repcnts_fail_count_qs;
end
addr_hit[43]: begin
reg_rdata_next[3:0] = extht_fail_counts_extht_hi_fail_count_qs;
reg_rdata_next[7:4] = extht_fail_counts_extht_lo_fail_count_qs;
end
addr_hit[44]: begin
reg_rdata_next[3:0] = fw_ov_control_fw_ov_mode_qs;
reg_rdata_next[7:4] = fw_ov_control_fw_ov_entropy_insert_qs;
end
addr_hit[45]: begin
reg_rdata_next[3:0] = fw_ov_sha3_start_qs;
end
addr_hit[46]: begin
reg_rdata_next[0] = fw_ov_wr_fifo_full_qs;
end
addr_hit[47]: begin
reg_rdata_next[0] = fw_ov_rd_fifo_overflow_qs;
end
addr_hit[48]: begin
reg_rdata_next[31:0] = fw_ov_rd_data_qs;
end
addr_hit[49]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[50]: begin
reg_rdata_next[6:0] = observe_fifo_thresh_qs;
end
addr_hit[51]: begin
reg_rdata_next[6:0] = observe_fifo_depth_qs;
end
addr_hit[52]: begin
reg_rdata_next[2:0] = debug_status_entropy_fifo_depth_qs;
reg_rdata_next[5:3] = debug_status_sha3_fsm_qs;
reg_rdata_next[6] = debug_status_sha3_block_pr_qs;
reg_rdata_next[7] = debug_status_sha3_squeezing_qs;
reg_rdata_next[8] = debug_status_sha3_absorbed_qs;
reg_rdata_next[9] = debug_status_sha3_err_qs;
reg_rdata_next[16] = debug_status_main_sm_idle_qs;
reg_rdata_next[17] = debug_status_main_sm_boot_done_qs;
end
addr_hit[53]: begin
reg_rdata_next[0] = recov_alert_sts_fips_enable_field_alert_qs;
reg_rdata_next[1] = recov_alert_sts_entropy_data_reg_en_field_alert_qs;
reg_rdata_next[2] = recov_alert_sts_module_enable_field_alert_qs;
reg_rdata_next[3] = recov_alert_sts_threshold_scope_field_alert_qs;
reg_rdata_next[5] = recov_alert_sts_rng_bit_enable_field_alert_qs;
reg_rdata_next[7] = recov_alert_sts_fw_ov_sha3_start_field_alert_qs;
reg_rdata_next[8] = recov_alert_sts_fw_ov_mode_field_alert_qs;
reg_rdata_next[9] = recov_alert_sts_fw_ov_entropy_insert_field_alert_qs;
reg_rdata_next[10] = recov_alert_sts_es_route_field_alert_qs;
reg_rdata_next[11] = recov_alert_sts_es_type_field_alert_qs;
reg_rdata_next[12] = recov_alert_sts_es_main_sm_alert_qs;
reg_rdata_next[13] = recov_alert_sts_es_bus_cmp_alert_qs;
reg_rdata_next[14] = recov_alert_sts_es_thresh_cfg_alert_qs;
reg_rdata_next[15] = recov_alert_sts_es_fw_ov_wr_alert_qs;
reg_rdata_next[16] = recov_alert_sts_es_fw_ov_disable_alert_qs;
end
addr_hit[54]: begin
reg_rdata_next[0] = err_code_sfifo_esrng_err_qs;
reg_rdata_next[1] = err_code_sfifo_observe_err_qs;
reg_rdata_next[2] = err_code_sfifo_esfinal_err_qs;
reg_rdata_next[20] = err_code_es_ack_sm_err_qs;
reg_rdata_next[21] = err_code_es_main_sm_err_qs;
reg_rdata_next[22] = err_code_es_cntr_err_qs;
reg_rdata_next[23] = err_code_sha3_state_err_qs;
reg_rdata_next[24] = err_code_sha3_rst_storage_err_qs;
reg_rdata_next[28] = err_code_fifo_write_err_qs;
reg_rdata_next[29] = err_code_fifo_read_err_qs;
reg_rdata_next[30] = err_code_fifo_state_err_qs;
end
addr_hit[55]: begin
reg_rdata_next[4:0] = err_code_test_qs;
end
addr_hit[56]: begin
reg_rdata_next[8:0] = main_sm_state_qs;
end
default: begin
reg_rdata_next = '1;
end
endcase
end
// shadow busy
logic shadow_busy;
assign shadow_busy = 1'b0;
// register busy
assign reg_busy = shadow_busy;
// Unused signal tieoff
// wdata / byte enable are not always fully used
// add a blanket unused statement to handle lint waivers
logic unused_wdata;
logic unused_be;
assign unused_wdata = ^reg_wdata;
assign unused_be = ^reg_be;
// Assertions for Register Interface
`ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
`ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
`ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
`ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
// this is formulated as an assumption such that the FPV testbenches do disprove this
// property by mistake
//`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
endmodule