blob: 84f1c582c8c75675ab5311356d8bacb8362b07f4 [file] [log] [blame]
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
// Name of the sim cfg - typically same as the name of the DUT.
name: entropy_src
// Top level dut name (sv module).
dut: entropy_src
// Top level testbench name (sv module).
tb: tb
// Simulator used to sign off this block
tool: xcelium
// Fusesoc core file used for building the file list.
fusesoc_core: lowrisc:dv:entropy_src_sim:0.1
// Testplan hjson file.
testplan: "{proj_root}/hw/ip/entropy_src/data/entropy_src_testplan.hjson"
// RAL spec - used to generate the RAL model.
ral_spec: "{proj_root}/hw/ip/entropy_src/data/entropy_src.hjson"
// Import additional common sim cfg files.
// TODO: remove imported cfgs that do not apply.
import_cfgs: [// Project wide common sim cfg file
"{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
// Common CIP test lists
"{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
// TODO: import `stress_tests.hjson` once hanging issue is resolved.
"{proj_root}/hw/dv/tools/dvsim/tests/stress_all_test.hjson"]
// Add additional tops for simulation.
sim_tops: ["entropy_src_bind", "entropy_src_cov_bind", "sec_cm_prim_onehot_check_bind"]
// Default iterations for all tests - each test entry can override this.
reseed: 50
xcelium_cov_refine_files: [
// TODO(V3): Finalize coverage on ExtHT ports & remove the following exclusion file
"{proj_root}/hw/ip/entropy_src/dv/cov/entropy_src_extht_exclusions.vRefine"
// Leave the following as a separate refinement, to support potential DV enhancements.
// (See the comments within the file for more detail)
"{proj_root}/hw/ip/entropy_src/dv/cov/entropy_src_cnt_err_excl.vRefine",
// Waive toggle coverage for the prim_count outputs. (MoreSB's not exercised)
"{proj_root}/hw/ip/entropy_src/dv/cov/entropy_src_cnt_out_excl.vRefine",
// Output of --cov-unr, with `prim_count` error exclusions removed.
"{proj_root}/hw/ip/entropy_src/dv/cov/entropy_src_UNR.vRefine",
]
// Default UVM test and seq class name.
uvm_test: entropy_src_base_test
uvm_test_seq: entropy_src_base_vseq
// List of test specifications.
tests: [
{
name: entropy_src_smoke
uvm_test: entropy_src_smoke_test
uvm_test_seq: entropy_src_smoke_vseq
}
{
name: entropy_src_rng
reseed: 300
uvm_test: entropy_src_rng_test
uvm_test_seq: entropy_src_rng_vseq
}
{
name: entropy_src_stress_all
uvm_test: entropy_src_stress_all_test
uvm_test_seq: entropy_src_stress_all_vseq
}
{
name: entropy_src_fw_ov
reseed: 300
uvm_test: entropy_src_fw_ov_test
uvm_test_seq: entropy_src_rng_vseq
}
// Entropy_src_intr_test currently requires some maintenance (failing tests, no support
// for scoreboarding/coverage). It is however currently not needed for meeting testpoints
// /coverage goals. All CSR-driven interrupt coverpoints are met by the common interrupt
// tests, and the functional stimulus-driven tests are supported by the entopy_src_rng.
// So this has been disabled for V2.
//{
// name: entropy_src_intr
// uvm_test: entropy_src_intr_test
// uvm_test_seq: entropy_src_intr_vseq
//}
{
name: entropy_src_functional_alerts
uvm_test: entropy_src_alert_test
uvm_test_seq: entropy_src_alert_vseq
}
{
name: entropy_src_cfg_regwen
uvm_test: entropy_src_cfg_regwen_test
uvm_test_seq: entropy_src_cfg_regwen_vseq
}
{
name: entropy_src_functional_errors
reseed: 1000
uvm_test: entropy_src_functional_errors_test
uvm_test_seq: entropy_src_err_vseq
}
// TODO: add more tests here
]
// List of regressions.
regressions: [
{
name: smoke
tests: ["entropy_src_smoke"]
}
{
name: live
tests: ["entropy_src_rng", "entropy_src_fw_ov"]
}
]
component_a: "uvm_test_top.env.scoreboard"
id_a : _ALL_
verbosity_a: UVM_FULL
phase_a: run
component_b: "uvm_test_top.env.virtual_sequencer"
id_b : _ALL_
verbosity_b: UVM_FULL
phase_b: run
run_modes: [
{
name: set_verbosity_comp_a_uvm_debug
run_opts: ["+uvm_set_verbosity={component_a},{id_a},{verbosity_a},{phase_a}"]
}
{
name: set_verbosity_comp_b_uvm_debug
run_opts: ["+uvm_set_verbosity={component_b},{id_b},{verbosity_b},{phase_b}"]
}
{
name: short_run
run_opts: ["+test_timeout_ns=40_000_000"]
}
]
}