// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// TOP Earlgrey configuration
{ name: "earlgrey",
  type: "top",

  datawidth: "32",  # 32-bit datawidth

  // This is the clock data strcture of the design.
  // The hier path refers to the clock reference path (struct / port)
  //   - The top/ext desgination follows the same scheme as inter-module
  // The src key indicates the raw clock sources in the design
  // The groups key indicates the various clock groupings in the design
  clocks: {

    hier_paths: {
      top: "clkmgr_clocks.", // top level is a struct
      ext: "",               // ext is a port of the clock name
    },

    // Clock Source attributes
    // name: Name of group.
    // aon:  Whether the clock is free running all the time.
    //       If it is, the clock is not hanlded by clkmgr.
    // freq: Absolute frequency of clk in Hz
    srcs: [
      { name: "main", aon: "no",  freq: "100000000" }
      { name: "io",   aon: "no",  freq: "100000000" }
      { name: "usb",  aon: "no",  freq: "48000000" }
      { name: "aon",  aon: "yes", freq: "200000" }
    ],

    // Derived clock source attributes
    // name: Name of group.
    // aon:  Whether the clock is free running all the time.
    //       If it is, the clock is not hanlded by clkmgr.
    // freq: Absolute frequency of clk in Hz
    // src:  From which clock source is the clock derived
    // div:  Ratio between derived clock and source clock
    derived_srcs: [
      { name: "io_div2", aon: "no", div: 2, src: "io", freq: "50000000" }
    ],

    // Clock Group attributes
    // name: name of group.
    //
    // src: The hierarchical source of the clock
    // "ext"  - clock is supplied from a port of the top module
    // "top"  - clock is supplied from a net inside the top module
    //
    // sw_cg: whether software is allowed to gate the clock
    // "no"   - software is not allowed to gate clocks
    // "yes"  - software is allowed to gate clocks
    // "hint" - software can provide a hint, and hw controls the rest
    //
    // unique: whether each module in the group can be separately gated
    //         if sw_cg is "no", this field has no meaning
    // "yes"  - each clock is individually controlled
    // "no"   - the group is controlled as one single unit
    //
    // The powerup and proc groups are unique.
    // The powerup group of clocks do not feed through the clock
    // controller as they manage clock controller behavior
    // The proc group is not peripheral, and direclty hardwired

    groups: [
      // the powerup group is used exclusively by clk/pwr/rstmgr
      { name: "powerup", src:"top", sw_cg: "no"                   }
      { name: "trans",   src:"top", sw_cg: "hint", unique: "yes", }
      { name: "infra",   src:"top", sw_cg: "no",                  }
      { name: "secure",  src:"top", sw_cg: "no"                   }
      { name: "peri",    src:"top", sw_cg: "yes",  unique: "no"   }
      { name: "timers",  src:"top", sw_cg: "no"                   }
      { name: "proc",
        src: "no"
        sw_cg: "no"
        unique: "no"
        clocks: {
          clk_proc_main: main
        }
      }
    ],
  }

  // Reset attributes
  // name: name of reset.
  //
  // type: the reset type [ext, top]
  // ext: the reset is coming in from the ports, external to earlgrey
  // top: the reset is coming from top level, the rstmgr output struct
  //
  // root: The parent reset
  // If type is "ext", there is no root, since it is external
  //
  // clk:  related clock domain for synchronous release
  // If type is "por", there is not related clock, since it is
  // likely external or generated from a voltage comparator
  //
  resets: [
    { name: "rst_ni",     type: "ext"                                      }
    { name: "por_aon",    type: "top",  root: "rst_ni",  clk: "aon"        }
    { name: "por",        type: "top",  root: "por_aon", clk: "main"       }
    { name: "por_io",     type: "top",  root: "por_aon", clk: "io"         }
    { name: "por_io_div2",type: "top",  root: "por_aon", clk: "io_div2"    }
    { name: "por_usb",    type: "top",  root: "por_aon", clk: "usb"        }
    { name: "lc",         type: "top",  root: "lc",      clk: "io"         }
    { name: "sys",        type: "top",  root: "sys",     clk: "main"       }
    { name: "sys_io",     type: "top",  root: "sys",     clk: "io_div2"    }
    { name: "sys_aon",    type: "top",  root: "sys",     clk: "io_div2"    }
    { name: "spi_device", type: "top",  root: "sys",     clk: "io_div2",  sw: 1 }
    { name: "usb",        type: "top",  root: "sys",     clk: "usb", sw: 1 }
  ]

  // Number of cores: used in rv_plic and timer
  num_cores: "1",

  // `module` defines the peripherals.
  // Details are coming from each modules' config file `ip.hjson`
  // TODO: Define parameter here
  module: [
    { name: "uart",     // instance name
      type: "uart",     // Must be matched to the ip name in `ip.hson` (_reg, _cfg permitted)
                        // and `hw/ip/{type}`

      // clock connections defines the port to top level clock connection
      // the ip.hjson will declare the clock port names
      // If none are defined at ip.hjson, clk_i is used by default
      clock_srcs: {clk_i: "io"},

      // reset connections defines the port to top level reset connection
      // the ip.hjson will declare the reset port names
      // If none are defined at ip.hjson, rst_ni is used by default
      reset_connections: {rst_ni: "sys_io"},

      base_addr: "0x40000000",
    },
    { name: "gpio",
      type: "gpio",
      clock_srcs: {clk_i: "io"},
      clock_group: "peri",
      reset_connections: {rst_ni: "sys_io"},
      base_addr: "0x40010000",
    }

    { name: "spi_device",
      type: "spi_device",
      clock_srcs: {clk_i: "io"},
      clock_group: "peri",
      reset_connections: {rst_ni: "spi_device"},
      base_addr: "0x40020000",
    },
    { name: "flash_ctrl",
      type: "flash_ctrl",
      clock_srcs: {clk_i: "main"},
      clock_group: "infra",
      reset_connections: {rst_ni: "lc"},
      base_addr: "0x40030000",
    },
    { name: "rv_timer",
      type: "rv_timer",
      clock_srcs: {clk_i: "io"},
      clock_group: "timers",
      reset_connections: {rst_ni: "sys_io"},
      base_addr: "0x40080000",
    },
    { name: "aes",
      type: "aes",
      clock_srcs: {clk_i: "main"},
      clock_group: "trans",
      reset_connections: {rst_ni: "sys"},
      base_addr: "0x40110000",
    },
    { name: "hmac",
      type: "hmac",
      clock_srcs: {clk_i: "main"},
      clock_group: "trans",
      reset_connections: {rst_ni: "sys"},
      base_addr: "0x40120000",
    },
    { name: "rv_plic",
      type: "rv_plic",
      clock_srcs: {clk_i: "main"},
      clock_group: "secure",
      reset_connections: {rst_ni: "sys"},
      base_addr: "0x40090000",
      generated: "true"         // Indicate this module is generated in the topgen
    }
    { name: "pinmux",
      type: "pinmux",
      clock: "main",
      clock_srcs: {clk_i: "main", clk_aon_i: "io"},
      clock_group: "secure",
      reset_connections: {rst_ni: "sys", rst_aon_ni: "sys_io"},
      base_addr: "0x40070000",
      generated: "true"
    },
    { name: "padctrl",
      type: "padctrl",
      clock: "main",
      clock_srcs: {clk_i: "main"},
      clock_group: "secure",
      reset_connections: {rst_ni: "sys"},
      base_addr: "0x40160000",
      generated: "true"
    },
    { name: "alert_handler",
      type: "alert_handler",
      clock_srcs: {clk_i: "main"},
      clock_group: "secure",
      reset_connections: {rst_ni: "sys"},
      base_addr: "0x40130000",
      generated: "true"         // Indicate this module is generated in the topgen
      localparam: {
        EscCntDw:  32,
        AccuCntDw: 16,
        LfsrSeed:  "0x7FFFFFFF"
      }
    }
    { name: "pwrmgr",
      type: "pwrmgr",
      clock_srcs: {clk_i: "io", clk_slow_i: "aon"},
      clock_group: "powerup",
      reset_connections: {rst_ni: "por", rst_slow_ni: "por_aon"},
      base_addr: "0x400A0000",
      generated: "true"         // Indicate this module is generated in the topgen

    },
    { name: "rstmgr",
      type: "rstmgr",
      clock_srcs: {clk_i: "io", clk_aon_i: "aon", clk_main_i: "main", clk_io_i: "io", clk_usb_i: "usb",
                   clk_io_div2_i: "io_div2"},
      clock_group: "powerup",
      reset_connections: {rst_ni: "rst_ni"},
      base_addr: "0x400B0000",
    },
    { name: "clkmgr",
      type: "clkmgr",
      //clock_srcs: {clk_i: "io", clk_main_i: "main", clk_io_i: "io", clk_usb_i: "usb", clk_aon_i: "aon"},
      clock_srcs: {clk_i: "io"},
      clock_group: "powerup",
      reset_connections: {rst_ni: "por_io", rst_main_ni: "por", rst_io_ni: "por_io", rst_usb_ni: "por_usb"
                          rst_io_div2_ni: "por_io_div2", },
      base_addr: "0x400C0000",
      generated: "true"
    },
    // dummy module to capture the alert handler escalation signals
    // and test them by converting them into IRQs
    { name: "nmi_gen",
      type: "nmi_gen",
      clock_srcs: {clk_i: "main"},
      clock_group: "secure",
      reset_connections: {rst_ni: "sys"},
      base_addr: "0x40140000",
    }
    { name: "usbdev",
      type: "usbdev",
      clock_srcs: {clk_i: "io", clk_usb_48mhz_i: "usb"},
      clock_group: "peri",
      reset_connections: {rst_ni: "sys_io", rst_usb_48mhz_ni: "usb"},
      base_addr: "0x40150000",
    },
    { name: "otbn",
      type: "otbn",
      clock_srcs: {clk_i: "main"},
      clock_group: "trans",
      reset_connections: {rst_ni: "sys"},
      base_addr: "0x50000000",
    },
  ]

  // Memories (ROM, RAM, eFlash) are defined at the top.
  // It utilizes the primitive cells but configurable
  memory: [
    { name: "rom",
      clock_srcs: {clk_i: "main"},
      clock_group: "infra",
      reset_connections: {rst_ni: "sys"},
      type: "rom",
      base_addr: "0x00008000",
      swaccess: "ro",
      size: "0x4000"
      inter_signal_list: [
        { struct: "tl"
          package: "tlul_pkg"
          type: "req_rsp"
          act: "rsp"
          name: "tl"
        }
      ]
    },
    { name: "ram_main",
      clock_srcs: {clk_i: "main"},
      clock_group: "infra",
      reset_connections: {rst_ni: "sys"},
      type: "ram_1p",
      base_addr: "0x10000000",
      size: "0x10000"
      inter_signal_list: [
        { struct: "tl"
          package: "tlul_pkg"
          type: "req_rsp"
          act: "rsp"
          name: "tl"
        }
      ]
    },
    { name: "ram_ret",
      clock_srcs: {clk_i: "io"},
      clock_group: "infra",
      reset_connections: {rst_ni: "sys_io"},
      type: "ram_1p",
      base_addr: "0x18000000",
      size: "0x1000"
      inter_signal_list: [
        { struct: "tl"
          package: "tlul_pkg"
          type: "req_rsp"
          act: "rsp"
          name: "tl"
        }
      ]
    },
    { name: "eflash",
      clock_srcs: {clk_i: "main"},
      clock_group: "infra",
      reset_connections: {rst_ni: "lc"},
      type: "eflash",
      base_addr: "0x20000000",
      swaccess: "ro",
      size: "0x80000",
      inter_signal_list: [
        { struct: "flash",    // flash_req_t, flash_rsp_t
          type: "req_rsp",
          name: "flash_ctrl", // flash_ctrl_i (req), flash_ctrl_o (rsp)
          act:  "rsp",
        },
        { struct: "tl"
          package: "tlul_pkg"
          type: "req_rsp"
          act: "rsp"
          name: "tl"
        }
      ],
    },
  ],

  // Inter-module Connection.
  // format:
  //    requester: [ resp1, resp2, ... ],
  //
  //  the field and value should be module_inst.port_name
  //  e.g flash_ctrl0.flash: [flash_phy0.flash_ctrl]
  inter_module: {
    'connect': {
      'flash_ctrl.flash': ['eflash.flash_ctrl']
      'pwrmgr.pwr_rst'  : ['rstmgr.pwr'],
      'pwrmgr.pwr_clk'  : ['clkmgr.pwr'],

    }

    // top is to connect to top net/struct.
    // It defines the signal in the top and connect from the module,
    // use of the signal is up to top template
    'top': [
        'rstmgr.resets', 'rstmgr.cpu', 'pwrmgr.pwr_cpu', 'clkmgr.clocks',
        'aes.idle', 'clkmgr.status',

        // Xbars
        'main.tl_corei', 'main.tl_cored', 'main.tl_dm_sba', 'main.tl_debug_mem'
    ],

    // ext is to create port in the top.
    'external': ['clkmgr.clk_main', 'clkmgr.clk_io', 'clkmgr.clk_usb', 'clkmgr.clk_aon'],
  },

  debug_mem_base_addr: "0x1A110000",

  // Crossbars: having a top level crossbar
  // This version assumes all crossbars are instantiated at the top.
  // Assume xbar.hjson is located in the same directory of top.hjson
  xbar: [
    { name: "main",
      clock_srcs: {clk_main_i: "main", clk_fixed_i: "io"},
      clock_group: "infra",
      reset: "sys",
      reset_connections: {rst_main_ni: "sys", rst_fixed_ni: "sys_io"}
    },
    { name: "peri",
      clock_srcs: {clk_peri_i: "io"},
      clock_group: "infra",
      reset: "sys_io",
      reset_connections: {rst_peri_ni: "sys_io"},
    }
  ],

  // ===== INTERRUPT CTRL =====================================================
  // `rv_plic`  will be instantiate (need to be defined in `module` field
  // If interrupt is not defined, it uses the order from the module list
  // and include every modules.
  // first item goes to LSB of the interrupt source
  interrupt_module: ["gpio", "uart", "spi_device", "flash_ctrl",
                     "hmac", "alert_handler", "nmi_gen", "usbdev", "pwrmgr",
                     "otbn" ]

  // RV_PLIC has two searching algorithm internally to pick the most highest priority interrupt
  // source. "sequential" is smaller but slower, "matrix" is larger but faster.
  // Choose depends on the criteria. Currently it is set to "matrix" to meet FPGA timing @ 50MHz

  // generated:
  interrupt: [
  ]

  // ===== ALERT HANDLER ======================================================
  // list all modules that expose alerts
  // first item goes to LSB of the alert source
  alert_module: [ "aes", "hmac", "otbn" ]

  // generated list of alerts:
  alert: [
  ]

  // TODO: PINMUX
  pinmux: {

    // Total number of Multiplexed I/O
    //  All the input/outputs from IPs are muxed in pinmux, and it has # of I/O
    //  talks to the outside of top_earlgrey.
    //  This field will be replaced to the length of PAD if padctrl is defined
    num_mio: 32

    // Dedicated IO modules. The in/out ports of the modules below are connected
    //  to TOP IO port through PADS directly. It bypasses PINMUX multiplexers
    dio_modules: [
      { name: "spi_device", pad: ["ChB[0..3]"] },
      //{ name: "uart.tx", pad: ["ChA[0]"]},
      { name: "uart", pad: ["ChA[0..1]"]},
      // { name: "dio_module.signal_input", pad: ["ChA[31]"] }
      { name: "usbdev", pad: ["ChC[0..8]"]},
    ],

    // Multiplexing IO modules. The in/out ports of the modules below are
    //  connected through PINMUX, which gives controllability of the connection
    //  between the modules and the IO PADS.
    //  If `mio_modules` aren't defined, it uses all remaining modules from
    //  module list except defined in `dio_modules`.
    mio_modules: ["uart", "gpio"]

    // If any module isn't defined in above two lists, its inputs will be tied
    //  to 0, and the output/OE signals will be floating (or connected to
    //  unused signal). `rv_plic` is special module, shouldn't be defined here.
    nc_modules: ["rv_timer", "hmac"]

    // Number of wakeup detectors to instantiate, and bitwidth for the wakeup
    // counters. Note that all MIO pad inputs are connected to the wakeup detectors,
    // and there is no way to disable this. DIO inputs on the other hand are by
    // default not connected.
    // TODO: need to add mechanism to mark them as wakeup pins.
    num_wkup_detect: 8
    wkup_cnt_width:  8

    // Below fields are generated.
    // inputs: [
    //  { name: "xxx", width: xx },
    //  ]
    // outputs: [
    //  { name: "xxx", width: xx },
    //  ]
    // inouts: [
    //  { name: "xxx", width: xx },
    //  ]
  }

  // PADS instantiation
  //  Number of in/outs and the numer of PAD instances doesn't have to be
  //  same. The number given below excludes clock/reset and other necessary
  //  PADS but only defines GPIO pads.
  padctrl: {
    attr_default: ["STRONG"],
    pads: [
      { name: "ChA" type: "IO_33V", count: 32 }, // Accessing as ChA[0] .. ChA[31]
      { name: "ChB" type: "IO_33V", count: 4, attr: ["KEEP", "WEAK"]},
      { name: "ChC" type: "IO_33V", count: 4, attr: ["KEEP", "STRONG"]},
    ]
  }

}