// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{ name: "main",
  type: "xbar",
  clock_primary: "clk_main_i", // Main clock, used in sockets
  other_clock_list: [ "clk_fixed_i" ] // Secondary clocks used by specific nodes
  reset_primary: "rst_main_ni", // Main reset, used in sockets
  other_reset_list: [ "rst_fixed_ni" ] // Secondary clocks used by specific nodes

  nodes: [
    { name:  "corei",
      type:  "host",
      clock: "clk_main_i",
      reset: "rst_main_ni",
      pipeline: "false"

    },
    { name:  "cored",
      type:  "host",
      clock: "clk_main_i",
      reset: "rst_main_ni",
      pipeline: "false"

    },
    { name:  "dm_sba", // DM
      type:  "host",
      clock: "clk_main_i",
      reset: "rst_main_ni",
      pipeline_byp: "false"

    },
    { name:      "rom",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      pipeline:  "false",
    },
    { name:      "debug_mem",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      pipeline_byp: "false"
    },
    { name:      "ram_main",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      pipeline:  "false",
    },
    { name:      "eflash",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      pipeline:  "false",
    },
    { name:      "peri",
      type:      "device",
      clock:     "clk_fixed_i",
      reset:     "rst_fixed_ni",
      pipeline_byp: "false"
    },
    { name:      "flash_ctrl.core",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      pipeline_byp: "false"
    },
    { name:      "flash_ctrl.prim",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      pipeline_byp: "false"
    },
    { name:      "hmac",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      pipeline_byp: "false"
    },
    { name:      "aes",
      type:      "device",
      clock:     "clk_main_i"
      reset:     "rst_main_ni"
      pipeline_byp: "false"
    },
    { name:      "rv_plic",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      inst_type: "rv_plic",
      addr_range: [{
        base_addr: "0x40090000",
        size_byte: "0x1000",
        }],
      pipeline_byp: "false"
    },
    { name:      "sram_ctrl_main",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      pipeline: "false"
    },
  ],
  connections: {
    corei:  ["rom", "debug_mem", "ram_main", "eflash"],
    cored:  ["rom", "debug_mem", "ram_main", "eflash", "peri", "flash_ctrl.core",
    "flash_ctrl.prim",
    "aes",
    "hmac", "rv_plic", "sram_ctrl_main"],
    dm_sba: ["rom",              "ram_main", "eflash", "peri", "flash_ctrl.core",
    "flash_ctrl.prim"
    "aes",
    "hmac", "rv_plic", "sram_ctrl_main"],
  },
}