tree c464d498b6943fbf238cccb9e810ce15e5833668
parent 9fd48839c2a08885a2e923cc3581a9c426c5c9a9
author Eunchan Kim <eunchan@opentitan.org> 1648760657 -0700
committer Eunchan Kim <github@eunchan.kim> 1648844820 -0700

[spi_device] Change addr_latched as a pulse

Problem:

    `addr_latched_i` in `spid_readsram` module is expected to be a pulse
    signal. The `spi_readcmd` module generates the signal as a level by
    comparing `addr_cnt_d` with all zero value.

    As a result, the `strb` register in `spid_readsram` follows the
    current address, which is increased by when a byte is sent to the
    host system. However, the `spid_readsram` logic pushes the data into
    the FIFO already. As the FIFO depth is 2, one more entry has been
    added to the FIFO, which results the host system sees the a byte has
    been shifted.

Resolution:

    Revised the `addr_latched` logic to be a pulse. Either `addr_cnt_d`
    or `addr_latched` can be revised. I chose the latter. Latching the
    latched signal and generated a pulse.

Signed-off-by: Eunchan Kim <eunchan@opentitan.org>