)]}'
{
  "commit": "56f1dbd6b7e30054d29b0da672e560e00be9d6e2",
  "tree": "c464d498b6943fbf238cccb9e810ce15e5833668",
  "parents": [
    "9fd48839c2a08885a2e923cc3581a9c426c5c9a9"
  ],
  "author": {
    "name": "Eunchan Kim",
    "email": "eunchan@opentitan.org",
    "time": "Thu Mar 31 14:04:17 2022 -0700"
  },
  "committer": {
    "name": "Eunchan Kim",
    "email": "github@eunchan.kim",
    "time": "Fri Apr 01 13:27:00 2022 -0700"
  },
  "message": "[spi_device] Change addr_latched as a pulse\n\nProblem:\n\n    `addr_latched_i` in `spid_readsram` module is expected to be a pulse\n    signal. The `spi_readcmd` module generates the signal as a level by\n    comparing `addr_cnt_d` with all zero value.\n\n    As a result, the `strb` register in `spid_readsram` follows the\n    current address, which is increased by when a byte is sent to the\n    host system. However, the `spid_readsram` logic pushes the data into\n    the FIFO already. As the FIFO depth is 2, one more entry has been\n    added to the FIFO, which results the host system sees the a byte has\n    been shifted.\n\nResolution:\n\n    Revised the `addr_latched` logic to be a pulse. Either `addr_cnt_d`\n    or `addr_latched` can be revised. I chose the latter. Latching the\n    latched signal and generated a pulse.\n\nSigned-off-by: Eunchan Kim \u003ceunchan@opentitan.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a6d89096a5453f85532106e3ad58d8db1b7cfb90",
      "old_mode": 33188,
      "old_path": "hw/ip/spi_device/rtl/spi_readcmd.sv",
      "new_id": "e32d2d851242094f8aac813e4e67d13633914b54",
      "new_mode": 33188,
      "new_path": "hw/ip/spi_device/rtl/spi_readcmd.sv"
    },
    {
      "type": "modify",
      "old_id": "cec7d50501a5231e5e9f44aeb360ef6b9ac9691d",
      "old_mode": 33188,
      "old_path": "hw/ip/spi_device/rtl/spid_readsram.sv",
      "new_id": "b9f0dea002aa03d661079cb32606ad8086c1376d",
      "new_mode": 33188,
      "new_path": "hw/ip/spi_device/rtl/spid_readsram.sv"
    }
  ]
}