hw/top_earlgrey/sw/autogen/top_earlgrey_memory.rs

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

#![allow(dead_code)]

///! Rust Top-Specific Definitions.
///!
///! This file contains const definitions for use within Rust code.

/// Memory base for sram_ctrl_ret_aon_ram_ret_aon in top earlgrey.
pub const TOP_EARLGREY_RAM_RET_AON_BASE_ADDR: usize = 0x40600000;

/// Memory size for sram_ctrl_ret_aon_ram_ret_aon in top earlgrey.
pub const TOP_EARLGREY_RAM_RET_AON_SIZE_BYTES: usize = 0x1000;
/// Memory base for flash_ctrl_eflash in top earlgrey.
pub const TOP_EARLGREY_EFLASH_BASE_ADDR: usize = 0x20000000;

/// Memory size for flash_ctrl_eflash in top earlgrey.
pub const TOP_EARLGREY_EFLASH_SIZE_BYTES: usize = 0x100000;
/// Memory base for sram_ctrl_main_ram_main in top earlgrey.
pub const TOP_EARLGREY_RAM_MAIN_BASE_ADDR: usize = 0x10000000;

/// Memory size for sram_ctrl_main_ram_main in top earlgrey.
pub const TOP_EARLGREY_RAM_MAIN_SIZE_BYTES: usize = 0x20000;
/// Memory base for rom_ctrl_rom in top earlgrey.
pub const TOP_EARLGREY_ROM_BASE_ADDR: usize = 0x00008000;

/// Memory size for rom_ctrl_rom in top earlgrey.
pub const TOP_EARLGREY_ROM_SIZE_BYTES: usize = 0x8000;

/// Peripheral base address for uart0 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_UART0_BASE_ADDR: usize = 0x40000000;

/// Peripheral size for uart0 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_UART0_BASE_ADDR and
/// `TOP_EARLGREY_UART0_BASE_ADDR + TOP_EARLGREY_UART0_SIZE_BYTES`.
pub const TOP_EARLGREY_UART0_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for uart1 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_UART1_BASE_ADDR: usize = 0x40010000;

/// Peripheral size for uart1 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_UART1_BASE_ADDR and
/// `TOP_EARLGREY_UART1_BASE_ADDR + TOP_EARLGREY_UART1_SIZE_BYTES`.
pub const TOP_EARLGREY_UART1_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for uart2 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_UART2_BASE_ADDR: usize = 0x40020000;

/// Peripheral size for uart2 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_UART2_BASE_ADDR and
/// `TOP_EARLGREY_UART2_BASE_ADDR + TOP_EARLGREY_UART2_SIZE_BYTES`.
pub const TOP_EARLGREY_UART2_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for uart3 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_UART3_BASE_ADDR: usize = 0x40030000;

/// Peripheral size for uart3 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_UART3_BASE_ADDR and
/// `TOP_EARLGREY_UART3_BASE_ADDR + TOP_EARLGREY_UART3_SIZE_BYTES`.
pub const TOP_EARLGREY_UART3_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for gpio in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_GPIO_BASE_ADDR: usize = 0x40040000;

/// Peripheral size for gpio in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_GPIO_BASE_ADDR and
/// `TOP_EARLGREY_GPIO_BASE_ADDR + TOP_EARLGREY_GPIO_SIZE_BYTES`.
pub const TOP_EARLGREY_GPIO_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for spi_device in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_SPI_DEVICE_BASE_ADDR: usize = 0x40050000;

/// Peripheral size for spi_device in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_SPI_DEVICE_BASE_ADDR and
/// `TOP_EARLGREY_SPI_DEVICE_BASE_ADDR + TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES`.
pub const TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES: usize = 0x2000;

/// Peripheral base address for i2c0 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_I2C0_BASE_ADDR: usize = 0x40080000;

/// Peripheral size for i2c0 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_I2C0_BASE_ADDR and
/// `TOP_EARLGREY_I2C0_BASE_ADDR + TOP_EARLGREY_I2C0_SIZE_BYTES`.
pub const TOP_EARLGREY_I2C0_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for i2c1 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_I2C1_BASE_ADDR: usize = 0x40090000;

/// Peripheral size for i2c1 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_I2C1_BASE_ADDR and
/// `TOP_EARLGREY_I2C1_BASE_ADDR + TOP_EARLGREY_I2C1_SIZE_BYTES`.
pub const TOP_EARLGREY_I2C1_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for i2c2 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_I2C2_BASE_ADDR: usize = 0x400A0000;

/// Peripheral size for i2c2 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_I2C2_BASE_ADDR and
/// `TOP_EARLGREY_I2C2_BASE_ADDR + TOP_EARLGREY_I2C2_SIZE_BYTES`.
pub const TOP_EARLGREY_I2C2_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for pattgen in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_PATTGEN_BASE_ADDR: usize = 0x400E0000;

/// Peripheral size for pattgen in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_PATTGEN_BASE_ADDR and
/// `TOP_EARLGREY_PATTGEN_BASE_ADDR + TOP_EARLGREY_PATTGEN_SIZE_BYTES`.
pub const TOP_EARLGREY_PATTGEN_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for rv_timer in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_RV_TIMER_BASE_ADDR: usize = 0x40100000;

/// Peripheral size for rv_timer in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_RV_TIMER_BASE_ADDR and
/// `TOP_EARLGREY_RV_TIMER_BASE_ADDR + TOP_EARLGREY_RV_TIMER_SIZE_BYTES`.
pub const TOP_EARLGREY_RV_TIMER_SIZE_BYTES: usize = 0x200;

/// Peripheral base address for core device on otp_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR: usize = 0x40130000;

/// Peripheral size for core device on otp_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR and
/// `TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES`.
pub const TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES: usize = 0x2000;

/// Peripheral base address for prim device on otp_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_OTP_CTRL_PRIM_BASE_ADDR: usize = 0x40132000;

/// Peripheral size for prim device on otp_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_OTP_CTRL_PRIM_BASE_ADDR and
/// `TOP_EARLGREY_OTP_CTRL_PRIM_BASE_ADDR + TOP_EARLGREY_OTP_CTRL_PRIM_SIZE_BYTES`.
pub const TOP_EARLGREY_OTP_CTRL_PRIM_SIZE_BYTES: usize = 0x20;

/// Peripheral base address for lc_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_LC_CTRL_BASE_ADDR: usize = 0x40140000;

/// Peripheral size for lc_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_LC_CTRL_BASE_ADDR and
/// `TOP_EARLGREY_LC_CTRL_BASE_ADDR + TOP_EARLGREY_LC_CTRL_SIZE_BYTES`.
pub const TOP_EARLGREY_LC_CTRL_SIZE_BYTES: usize = 0x100;

/// Peripheral base address for alert_handler in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR: usize = 0x40150000;

/// Peripheral size for alert_handler in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR and
/// `TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR + TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES`.
pub const TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES: usize = 0x800;

/// Peripheral base address for spi_host0 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_SPI_HOST0_BASE_ADDR: usize = 0x40300000;

/// Peripheral size for spi_host0 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_SPI_HOST0_BASE_ADDR and
/// `TOP_EARLGREY_SPI_HOST0_BASE_ADDR + TOP_EARLGREY_SPI_HOST0_SIZE_BYTES`.
pub const TOP_EARLGREY_SPI_HOST0_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for spi_host1 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_SPI_HOST1_BASE_ADDR: usize = 0x40310000;

/// Peripheral size for spi_host1 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_SPI_HOST1_BASE_ADDR and
/// `TOP_EARLGREY_SPI_HOST1_BASE_ADDR + TOP_EARLGREY_SPI_HOST1_SIZE_BYTES`.
pub const TOP_EARLGREY_SPI_HOST1_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for usbdev in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_USBDEV_BASE_ADDR: usize = 0x40320000;

/// Peripheral size for usbdev in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_USBDEV_BASE_ADDR and
/// `TOP_EARLGREY_USBDEV_BASE_ADDR + TOP_EARLGREY_USBDEV_SIZE_BYTES`.
pub const TOP_EARLGREY_USBDEV_SIZE_BYTES: usize = 0x1000;

/// Peripheral base address for pwrmgr_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_PWRMGR_AON_BASE_ADDR: usize = 0x40400000;

/// Peripheral size for pwrmgr_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_PWRMGR_AON_BASE_ADDR and
/// `TOP_EARLGREY_PWRMGR_AON_BASE_ADDR + TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES`.
pub const TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for rstmgr_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_RSTMGR_AON_BASE_ADDR: usize = 0x40410000;

/// Peripheral size for rstmgr_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_RSTMGR_AON_BASE_ADDR and
/// `TOP_EARLGREY_RSTMGR_AON_BASE_ADDR + TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES`.
pub const TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for clkmgr_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_CLKMGR_AON_BASE_ADDR: usize = 0x40420000;

/// Peripheral size for clkmgr_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_CLKMGR_AON_BASE_ADDR and
/// `TOP_EARLGREY_CLKMGR_AON_BASE_ADDR + TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES`.
pub const TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for sysrst_ctrl_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR: usize = 0x40430000;

/// Peripheral size for sysrst_ctrl_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR and
/// `TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR + TOP_EARLGREY_SYSRST_CTRL_AON_SIZE_BYTES`.
pub const TOP_EARLGREY_SYSRST_CTRL_AON_SIZE_BYTES: usize = 0x100;

/// Peripheral base address for adc_ctrl_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR: usize = 0x40440000;

/// Peripheral size for adc_ctrl_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR and
/// `TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR + TOP_EARLGREY_ADC_CTRL_AON_SIZE_BYTES`.
pub const TOP_EARLGREY_ADC_CTRL_AON_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for pwm_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_PWM_AON_BASE_ADDR: usize = 0x40450000;

/// Peripheral size for pwm_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_PWM_AON_BASE_ADDR and
/// `TOP_EARLGREY_PWM_AON_BASE_ADDR + TOP_EARLGREY_PWM_AON_SIZE_BYTES`.
pub const TOP_EARLGREY_PWM_AON_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for pinmux_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_PINMUX_AON_BASE_ADDR: usize = 0x40460000;

/// Peripheral size for pinmux_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_PINMUX_AON_BASE_ADDR and
/// `TOP_EARLGREY_PINMUX_AON_BASE_ADDR + TOP_EARLGREY_PINMUX_AON_SIZE_BYTES`.
pub const TOP_EARLGREY_PINMUX_AON_SIZE_BYTES: usize = 0x1000;

/// Peripheral base address for aon_timer_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR: usize = 0x40470000;

/// Peripheral size for aon_timer_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR and
/// `TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR + TOP_EARLGREY_AON_TIMER_AON_SIZE_BYTES`.
pub const TOP_EARLGREY_AON_TIMER_AON_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for ast in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_AST_BASE_ADDR: usize = 0x40480000;

/// Peripheral size for ast in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_AST_BASE_ADDR and
/// `TOP_EARLGREY_AST_BASE_ADDR + TOP_EARLGREY_AST_SIZE_BYTES`.
pub const TOP_EARLGREY_AST_SIZE_BYTES: usize = 0x400;

/// Peripheral base address for sensor_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR: usize = 0x40490000;

/// Peripheral size for sensor_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR and
/// `TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR + TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES`.
pub const TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for regs device on sram_ctrl_ret_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR: usize = 0x40500000;

/// Peripheral size for regs device on sram_ctrl_ret_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and
/// `TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`.
pub const TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES: usize = 0x20;

/// Peripheral base address for ram device on sram_ctrl_ret_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR: usize = 0x40600000;

/// Peripheral size for ram device on sram_ctrl_ret_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and
/// `TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`.
pub const TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES: usize = 0x1000;

/// Peripheral base address for core device on flash_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR: usize = 0x41000000;

/// Peripheral size for core device on flash_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR and
/// `TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES`.
pub const TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES: usize = 0x200;

/// Peripheral base address for prim device on flash_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR: usize = 0x41008000;

/// Peripheral size for prim device on flash_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR and
/// `TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES`.
pub const TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for mem device on flash_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR: usize = 0x20000000;

/// Peripheral size for mem device on flash_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR and
/// `TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES`.
pub const TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES: usize = 0x100000;

/// Peripheral base address for regs device on rv_dm in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_RV_DM_REGS_BASE_ADDR: usize = 0x41200000;

/// Peripheral size for regs device on rv_dm in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_RV_DM_REGS_BASE_ADDR and
/// `TOP_EARLGREY_RV_DM_REGS_BASE_ADDR + TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES`.
pub const TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES: usize = 0x4;

/// Peripheral base address for mem device on rv_dm in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_RV_DM_MEM_BASE_ADDR: usize = 0x10000;

/// Peripheral size for mem device on rv_dm in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_RV_DM_MEM_BASE_ADDR and
/// `TOP_EARLGREY_RV_DM_MEM_BASE_ADDR + TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES`.
pub const TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES: usize = 0x1000;

/// Peripheral base address for rv_plic in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_RV_PLIC_BASE_ADDR: usize = 0x48000000;

/// Peripheral size for rv_plic in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_RV_PLIC_BASE_ADDR and
/// `TOP_EARLGREY_RV_PLIC_BASE_ADDR + TOP_EARLGREY_RV_PLIC_SIZE_BYTES`.
pub const TOP_EARLGREY_RV_PLIC_SIZE_BYTES: usize = 0x8000000;

/// Peripheral base address for aes in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_AES_BASE_ADDR: usize = 0x41100000;

/// Peripheral size for aes in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_AES_BASE_ADDR and
/// `TOP_EARLGREY_AES_BASE_ADDR + TOP_EARLGREY_AES_SIZE_BYTES`.
pub const TOP_EARLGREY_AES_SIZE_BYTES: usize = 0x100;

/// Peripheral base address for hmac in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_HMAC_BASE_ADDR: usize = 0x41110000;

/// Peripheral size for hmac in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_HMAC_BASE_ADDR and
/// `TOP_EARLGREY_HMAC_BASE_ADDR + TOP_EARLGREY_HMAC_SIZE_BYTES`.
pub const TOP_EARLGREY_HMAC_SIZE_BYTES: usize = 0x1000;

/// Peripheral base address for kmac in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_KMAC_BASE_ADDR: usize = 0x41120000;

/// Peripheral size for kmac in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_KMAC_BASE_ADDR and
/// `TOP_EARLGREY_KMAC_BASE_ADDR + TOP_EARLGREY_KMAC_SIZE_BYTES`.
pub const TOP_EARLGREY_KMAC_SIZE_BYTES: usize = 0x1000;

/// Peripheral base address for otbn in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_OTBN_BASE_ADDR: usize = 0x41130000;

/// Peripheral size for otbn in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_OTBN_BASE_ADDR and
/// `TOP_EARLGREY_OTBN_BASE_ADDR + TOP_EARLGREY_OTBN_SIZE_BYTES`.
pub const TOP_EARLGREY_OTBN_SIZE_BYTES: usize = 0x10000;

/// Peripheral base address for keymgr in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_KEYMGR_BASE_ADDR: usize = 0x41140000;

/// Peripheral size for keymgr in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_KEYMGR_BASE_ADDR and
/// `TOP_EARLGREY_KEYMGR_BASE_ADDR + TOP_EARLGREY_KEYMGR_SIZE_BYTES`.
pub const TOP_EARLGREY_KEYMGR_SIZE_BYTES: usize = 0x100;

/// Peripheral base address for csrng in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_CSRNG_BASE_ADDR: usize = 0x41150000;

/// Peripheral size for csrng in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_CSRNG_BASE_ADDR and
/// `TOP_EARLGREY_CSRNG_BASE_ADDR + TOP_EARLGREY_CSRNG_SIZE_BYTES`.
pub const TOP_EARLGREY_CSRNG_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for entropy_src in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR: usize = 0x41160000;

/// Peripheral size for entropy_src in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR and
/// `TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR + TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES`.
pub const TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES: usize = 0x100;

/// Peripheral base address for edn0 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_EDN0_BASE_ADDR: usize = 0x41170000;

/// Peripheral size for edn0 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_EDN0_BASE_ADDR and
/// `TOP_EARLGREY_EDN0_BASE_ADDR + TOP_EARLGREY_EDN0_SIZE_BYTES`.
pub const TOP_EARLGREY_EDN0_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for edn1 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_EDN1_BASE_ADDR: usize = 0x41180000;

/// Peripheral size for edn1 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_EDN1_BASE_ADDR and
/// `TOP_EARLGREY_EDN1_BASE_ADDR + TOP_EARLGREY_EDN1_SIZE_BYTES`.
pub const TOP_EARLGREY_EDN1_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for regs device on sram_ctrl_main in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR: usize = 0x411C0000;

/// Peripheral size for regs device on sram_ctrl_main in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
/// `TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
pub const TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES: usize = 0x20;

/// Peripheral base address for ram device on sram_ctrl_main in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR: usize = 0x10000000;

/// Peripheral size for ram device on sram_ctrl_main in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR and
/// `TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`.
pub const TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES: usize = 0x20000;

/// Peripheral base address for regs device on rom_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR: usize = 0x411E0000;

/// Peripheral size for regs device on rom_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR and
/// `TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR + TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES`.
pub const TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for rom device on rom_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR: usize = 0x8000;

/// Peripheral size for rom device on rom_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR and
/// `TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR + TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES`.
pub const TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES: usize = 0x8000;

/// Peripheral base address for cfg device on rv_core_ibex in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR: usize = 0x411F0000;

/// Peripheral size for cfg device on rv_core_ibex in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR and
/// `TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES`.
pub const TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES: usize = 0x100;

/// MMIO Region
///
/// MMIO region excludes any memory that is separate from the module
/// configuration space, i.e. ROM, main SRAM, and flash are excluded but
/// retention SRAM, spi_device memory, or usbdev memory are included.
pub const TOP_EARLGREY_MMIO_BASE_ADDR: usize = 0x40000000;
pub const TOP_EARLGREY_MMIO_SIZE_BYTES: usize = 0x10000000;