)]}'
{
  "commit": "544da8d7e14a87469bedc5d36a08d69aa7d7a044",
  "tree": "deea143f47bc38a489ccdbe9a39ac722ae85132d",
  "parents": [
    "941227d0df5ccf7738e914f0bfb1dadcdfdd60e0"
  ],
  "author": {
    "name": "Srikrishna Iyer",
    "email": "sriyer@google.com",
    "time": "Tue Jan 14 23:51:41 2020 -0800"
  },
  "committer": {
    "name": "sriyerg",
    "email": "46467186+sriyerg@users.noreply.github.com",
    "time": "Thu Jan 16 13:07:53 2020 -0800"
  },
  "message": "[dv regr tool] Support for multi IP sim runs\n\n- Added support for running sims for multiple IPs in parallel\n  Command line:\n  ```console\n  $ util/dvsim.py hw/dv/data/master_sim_cfgs_list.hjson -i sanity --reseed 1 [--purge]\n  ```\n  - The master_sim_cfgs_list.hjson only adds UART and HMAC hjsons - need to\n  add the cfg hjsons for other IPs once they are available\n\n- Added \u0027FlowCfg.py\u0027 which serves as base class implementation for hjson\nbased infrastructure specification - SimCfg now extends from it. This is\ndone in preperation to add support for other ASIC flows such as FPV,\nlint, etc in future.\n\n- Several optimizations to reduce run time (12x speedup from before!)\n\nSigned-off-by: Srikrishna Iyer \u003csriyer@google.com\u003e\n",
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