diff --git a/hw/top_earlgrey/cdc/cdc_waivers.w_interface.tcl b/hw/top_earlgrey/cdc/cdc_waivers.w_interface.tcl
index 733b925..f2fbbee 100644
--- a/hw/top_earlgrey/cdc/cdc_waivers.w_interface.tcl
+++ b/hw/top_earlgrey/cdc/cdc_waivers.w_interface.tcl
@@ -71,14 +71,14 @@
 set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_otp_ctrl.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.data_q[8][23:16]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors}
 set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_xbar_main.u_asf_35.reqfifo.fifo_rptr_gray_q[0]")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors}
 set_rule_status -rule {W_INTERFACE} -expression {(ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.dr_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors}
-set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.fifo_*ptr_gray_q")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors}
+set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.src_fsm_q")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors}
 set_rule_status -rule {W_INTERFACE} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors}
 set_rule_status -rule {W_INTERFACE} -expression {(ReceivingFlop =~ "top_earlgrey.u_spi_device.u_spi_tpm.sck_st_q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors}
 set_rule_status -rule {W_INTERFACE} -expression {(ComponentClass =~ "CNTL") && (ErrorType =~ "") && (MultiClockDomains =~ "SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK::IO_DIV4_CLK") && (Signal =~ "top_earlgrey.u_spi_device.rxf_full_q")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors}
 set_rule_status -rule {W_INTERFACE} -expression {(ComponentClass =~ "CNTL") && (ErrorType =~ "") && (MultiClockDomains =~ "MAIN_CLK::JTAG_TCK,MAIN_CLK") && (Signal =~ "top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.src_fsm_q")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors}
 set_rule_status -rule {W_INTERFACE} -expression {(ComponentClass =~ "FEEDBACK") && (ErrorType =~ "") && (MultiClockDomains =~ "JTAG_TCK,MAIN_CLK::MAIN_CLK") && (Signal =~ "top_earlgrey.u_rv_dm.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.dst_fsm_q")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors}
 set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_spi_device.u_fwmode.u_*xf_ctrl.*ptr*") && (ReceivingFlop =~ "top_earlgrey.u_spi_device.u_reg.u_intr_state_generic_*x*.q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors}
-set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.fifo_*ptr_gray_q*") && (ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.sync_*ptr.u_sync_1.gen_generic.u_impl_generic.q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors and fifo with feedback path}
+set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.dst_fsm_q") && (ReceivingFlop =~ "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic.q*")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors and fifo with feedback path}
 set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_rom_ctrl.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_done_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic.q_o*") && (ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {rom_ctrl_i.good is not synchronized as it acts as a "payload" signal to "done". Good is only observed if "done" is high}
 set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "IOB*") && (ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {rom_ctrl_i.good is not synchronized as it acts as a "payload" signal to "done". Good is only observed if "done" is high}
 set_rule_status -rule {W_INTERFACE} -expression {(Signal =~ "top_earlgrey.u_rv_core_ibex.core_sleep_q*") && (ReceivingFlop =~ "top_earlgrey.u_pwrmgr_aon.u_cdc.*.u_sync_1.gen_generic.u_impl_generic.q_o*")} -status {Waived} -comment {Handled by CDC handshaking}