tree 003b0fd5541d47bab291ae1032c129ae5ab017d8
parent 64b6d9b7c0143aeeccabb53cf3a3e173962215f4
author Mark Branstad <mark.branstad@wdc.com> 1614019459 -0800
committer Pirmin Vogel <vogelpi@lowrisc.org> 1614539546 +0100

[csrng/rtl] internal state read timing improvements

Re-structed the read flow for the internal state array.
Added parameter to prim_fifo_sync to remove output mux.
Added simple flops to break up configuration paths.
Added fifo output mux back for genbits to prevent assertion.
Cleaned up format for hjson file.
Updated internal state rtl based on feedback.
Fixed hjson register wording.
Added comment for FIFO parameter use.

Signed-off-by: Mark Branstad <mark.branstad@wdc.com>