| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| |
| //================================================== |
| // This file contains the Excluded objects |
| // Generated By User: chencindy |
| // Format Version: 2 |
| // Date: Wed Nov 30 12:30:55 2022 |
| // ExclMode: default |
| //================================================== |
| CHECKSUM: "951561765 3328643058" |
| INSTANCE: tb.dut.u_ping_timer |
| Fsm state_q "2842986776" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition AlertPingSt->FsmErrorSt "369->366" |
| Fsm state_q "2842986776" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition EscWaitSt->FsmErrorSt "182->366" |
| Fsm state_q "2842986776" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition EscPingSt->FsmErrorSt "29->366" |
| Fsm state_q "2842986776" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition InitSt->FsmErrorSt "203->366" |
| CHECKSUM: "3358687906 2811042798" |
| INSTANCE: tb.dut.gen_classes[0].u_esc_timer |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase1St->FsmErrorSt "340->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase2St->FsmErrorSt "25->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase3St->FsmErrorSt "609->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition TerminalSt->FsmErrorSt "895->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition TimeoutSt->FsmErrorSt "38->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase0St->FsmErrorSt "901->488" |
| CHECKSUM: "3358687906 2811042798" |
| INSTANCE: tb.dut.gen_classes[1].u_esc_timer |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase0St->FsmErrorSt "901->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition TerminalSt->FsmErrorSt "895->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition TimeoutSt->FsmErrorSt "38->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase3St->FsmErrorSt "609->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase2St->FsmErrorSt "25->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase1St->FsmErrorSt "340->488" |
| CHECKSUM: "3358687906 2811042798" |
| INSTANCE: tb.dut.gen_classes[2].u_esc_timer |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase0St->FsmErrorSt "901->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition TimeoutSt->FsmErrorSt "38->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition TerminalSt->FsmErrorSt "895->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase3St->FsmErrorSt "609->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase2St->FsmErrorSt "25->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase1St->FsmErrorSt "340->488" |
| CHECKSUM: "3358687906 2811042798" |
| INSTANCE: tb.dut.gen_classes[3].u_esc_timer |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase1St->FsmErrorSt "340->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase2St->FsmErrorSt "25->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase3St->FsmErrorSt "609->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition TerminalSt->FsmErrorSt "895->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition TimeoutSt->FsmErrorSt "38->488" |
| Fsm state_q "3850519017" |
| ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." |
| Transition Phase0St->FsmErrorSt "901->488" |
| CHECKSUM: "1268953672 3214085926" |
| INSTANCE: tb.dut |
| ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000." |
| Toggle crashdump_o.class_esc_cnt [1][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt" |
| ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000." |
| Toggle crashdump_o.class_esc_cnt [2][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt" |
| ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000." |
| Toggle crashdump_o.class_esc_cnt [3][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt" |
| ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000." |
| Toggle crashdump_o.class_esc_cnt [0][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt" |
| CHECKSUM: "2301929872 1403235006" |
| INSTANCE: tb.dut.u_ping_timer.u_prim_count_esc_cnt |
| ANNOTATION: "[UNR]: Tied off to 1." |
| Toggle step_i "net step_i[15:0]" |
| CHECKSUM: "2301929872 1403235006" |
| INSTANCE: tb.dut.u_ping_timer.u_prim_count_cnt |
| ANNOTATION: "[UNR]: Tied off to 1." |
| Toggle step_i "net step_i[15:0]" |
| CHECKSUM: "2301929872 1403235006" |
| INSTANCE: tb.dut.gen_classes[0].u_accu.u_prim_count |
| ANNOTATION: "[UNR]: Tied off to 1." |
| Toggle step_i "net step_i[15:0]" |
| CHECKSUM: "2301929872 1403235006" |
| INSTANCE: tb.dut.gen_classes[1].u_accu.u_prim_count |
| ANNOTATION: "[UNR]: Tied off to 1." |
| Toggle step_i "net step_i[15:0]" |
| CHECKSUM: "2301929872 1403235006" |
| INSTANCE: tb.dut.gen_classes[2].u_accu.u_prim_count |
| ANNOTATION: "[UNR]: Tied off to 1." |
| Toggle step_i "net step_i[15:0]" |
| CHECKSUM: "2301929872 1403235006" |
| INSTANCE: tb.dut.gen_classes[3].u_accu.u_prim_count |
| ANNOTATION: "[UNR]: Tied off to 1." |
| Toggle step_i "net step_i[15:0]" |
| CHECKSUM: "2301929872 277894862" |
| INSTANCE: tb.dut.gen_classes[0].u_esc_timer.u_prim_count |
| ANNOTATION: "[UNR]: Tied off to 1." |
| Toggle set_cnt_i "net set_cnt_i[31:0]" |
| ANNOTATION: "[UNR]: Tied off to 1." |
| Toggle step_i "net step_i[31:0]" |
| CHECKSUM: "2301929872 277894862" |
| INSTANCE: tb.dut.gen_classes[1].u_esc_timer.u_prim_count |
| ANNOTATION: "[UNR]: Tied off to 1." |
| Toggle set_cnt_i "net set_cnt_i[31:0]" |
| ANNOTATION: "[UNR]: Tied off to 1." |
| Toggle step_i "net step_i[31:0]" |
| CHECKSUM: "2301929872 277894862" |
| INSTANCE: tb.dut.gen_classes[2].u_esc_timer.u_prim_count |
| ANNOTATION: "[UNR]: Tied off to 1." |
| Toggle set_cnt_i "net set_cnt_i[31:0]" |
| ANNOTATION: "[UNR]: Tied off to 1." |
| Toggle step_i "net step_i[31:0]" |
| CHECKSUM: "2301929872 277894862" |
| INSTANCE: tb.dut.gen_classes[3].u_esc_timer.u_prim_count |
| ANNOTATION: "[UNR]: Tied off to 1." |
| Toggle step_i "net step_i[31:0]" |
| ANNOTATION: "[UNR]: Tied off to 1." |
| Toggle set_cnt_i "net set_cnt_i[31:0]" |
