hw/ip/sysrst_ctrl/dv/env/sysrst_ctrl_env.core

CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:dv:sysrst_ctrl_env:0.1"
description: "SYSRST_CTRL DV UVM environment"
filesets:
  files_dv:
    depend:
      - lowrisc:dv:ralgen
      - lowrisc:dv:cip_lib
    files:
      - sysrst_ctrl_if.sv
      - sysrst_ctrl_env_pkg.sv
      - sysrst_ctrl_env_cfg.sv: {is_include_file: true}
      - sysrst_ctrl_env_cov.sv: {is_include_file: true}
      - sysrst_ctrl_virtual_sequencer.sv: {is_include_file: true}
      - sysrst_ctrl_scoreboard.sv: {is_include_file: true}
      - sysrst_ctrl_env.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_vseq_list.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_base_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_common_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_smoke_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_in_out_inverted_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_combo_detect_ec_rst_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_pin_access_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_pin_override_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_flash_wr_prot_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_ec_pwr_on_rst_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_auto_blk_key_output_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_ultra_low_pwr_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_combo_detect_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_edge_detect_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_stress_all_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv: {is_include_file: true}
      - seq_lib/sysrst_ctrl_feature_disable_vseq.sv: {is_include_file: true}
    file_type: systemVerilogSource

generate:
  ral:
    generator: ralgen
    parameters:
      name: sysrst_ctrl
      ip_hjson: ../../data/sysrst_ctrl.hjson

targets:
  default:
    filesets:
      - files_dv
    generate:
      - ral