)]}'
{
  "commit": "4a9e9fbb6c91e25ddfe5612b740ccadbb53e61ba",
  "tree": "dc73ce06eb3e64565c7073b4e9cf90acc1fab2e4",
  "parents": [
    "c1328144a07ccd2120eb7b3159a636c4b16f27bd"
  ],
  "author": {
    "name": "Cindy Chen",
    "email": "chencindy@opentitan.org",
    "time": "Fri Jun 24 11:38:32 2022 -0700"
  },
  "committer": {
    "name": "Cindy Chen",
    "email": "cindy.chen0316@gmail.com",
    "time": "Fri Jun 24 14:08:48 2022 -0700"
  },
  "message": "[formal/conn] Update chip level connectivity csvs\n\nThis PR updates two mismatches in connectivity test:\n1). Fix an ibex memory path\n2). Fix usb clock connection\n\nSigned-off-by: Cindy Chen \u003cchencindy@opentitan.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "de0a2d3b610429d2edca7b6ac96c1e21ec926a69",
      "old_mode": 33188,
      "old_path": "hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv",
      "new_id": "16d40bf6d8414943881e328b9836ebaaa066165e",
      "new_mode": 33188,
      "new_path": "hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
    },
    {
      "type": "modify",
      "old_id": "0b9e9b79fbe07e41101470504b1b0b5efe30ae87",
      "old_mode": 33188,
      "old_path": "hw/top_earlgrey/formal/conn_csvs/clkmgr_peri.csv",
      "new_id": "2a558f80f25ce338080c96f12729a56a7a5cba79",
      "new_mode": 33188,
      "new_path": "hw/top_earlgrey/formal/conn_csvs/clkmgr_peri.csv"
    }
  ]
}