)]}'
{
  "commit": "4a86fbf1687b7cfd32c484dfd7b0d52537a3fb3e",
  "tree": "b5584e1c0c9eb318c5ea72091af489e045896963",
  "parents": [
    "5f54587073b01241e8ba2761375a16ccd699416f"
  ],
  "author": {
    "name": "Michael Schaffner",
    "email": "msf@opentitan.org",
    "time": "Fri Mar 05 17:53:04 2021 -0800"
  },
  "committer": {
    "name": "Michael Schaffner",
    "email": "msf@google.com",
    "time": "Wed Mar 10 18:11:41 2021 -0800"
  },
  "message": "[top] Align FPGA, Verilator and DV tops\n\nSigned-off-by: Michael Schaffner \u003cmsf@opentitan.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "hw/top_earlgrey/data/clocks.xdc",
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      "new_mode": 33188,
      "new_path": "hw/top_earlgrey/data/clocks.xdc"
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}