diff --git a/hw/dv/sv/cip_lib/cip_base_env.sv b/hw/dv/sv/cip_lib/cip_base_env.sv
index fb8c394..aac0e5c 100644
--- a/hw/dv/sv/cip_lib/cip_base_env.sv
+++ b/hw/dv/sv/cip_lib/cip_base_env.sv
@@ -38,7 +38,7 @@
 
     // create components
     m_tl_agent = tl_agent::type_id::create("m_tl_agent", this);
-    m_tl_reg_adapter = tl_reg_adapter::type_id::create("m_tl_reg_adapter");
+    m_tl_reg_adapter = tl_reg_adapter#()::type_id::create("m_tl_reg_adapter");
     uvm_config_db#(tl_agent_cfg)::set(this, "m_tl_agent*", "cfg", cfg.m_tl_agent_cfg);
   endfunction
 
diff --git a/hw/ip/prim/rtl/prim_assert.sv b/hw/ip/prim/rtl/prim_assert.sv
index 76a261f..e9369dc 100644
--- a/hw/ip/prim/rtl/prim_assert.sv
+++ b/hw/ip/prim/rtl/prim_assert.sv
@@ -28,9 +28,9 @@
 //------------------------------------------------------------------------------------
 
 // Converts an arbitrary block of code into a Verilog string
-`define STRINGIFY(__x) `"__x`"
+`define PRIM_STRINGIFY(__x) `"__x`"
 
-// ASSERT_RPT is available to change the reporting mechanism when an assert fails
+  // ASSERT_RPT is available to change the reporting mechanism when an assert fails
 `define ASSERT_RPT(__name, __msg)                                         \
 `ifdef UVM_PKG_SV                                                         \
   assert_rpt_pkg::assert_rpt($sformatf("[%m] %s: %s (%s:%0d)",            \
@@ -46,23 +46,23 @@
 //------------------------------------------------------------------------------------
 // Immediate assertion
 // Note that immediate assertions are sensitive to simulation glitches.
-`define ASSERT_I(__name, __prop)                             \
-`ifndef VERILATOR                                            \
-  //pragma translate_off                                     \
-  __name: assert (__prop)                                    \
-    else `ASSERT_RPT(`STRINGIFY(__name), `STRINGIFY(__prop)) \
-  //pragma translate_on                                      \
+`define ASSERT_I(__name, __prop)                                       \
+`ifndef VERILATOR                                                      \
+  //pragma translate_off                                               \
+  __name: assert (__prop)                                              \
+    else `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop)) \
+  //pragma translate_on                                                \
 `endif
 
 //------------------------------------------------------------------------------------
 // Assertion in initial block. Can be used for things like parameter checking.
-`define ASSERT_INIT(__name, __prop)                            \
-`ifndef VERILATOR                                              \
-  //pragma translate_off                                       \
-  initial                                                      \
-    __name: assert (__prop)                                    \
-      else `ASSERT_RPT(`STRINGIFY(__name), `STRINGIFY(__prop)) \
-  //pragma translate_on                                        \
+`define ASSERT_INIT(__name, __prop)                                      \
+`ifndef VERILATOR                                                        \
+  //pragma translate_off                                                 \
+  initial                                                                \
+    __name: assert (__prop)                                              \
+      else `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop)) \
+  //pragma translate_on                                                  \
 `endif
 
 //------------------------------------------------------------------------------------
@@ -74,7 +74,7 @@
   //pragma translate_off                                                     \
   final                                                                      \
     __name: assert (__prop || $test$plusargs("disable_assert_final_checks")) \
-      else `ASSERT_RPT(`STRINGIFY(__name), `STRINGIFY(__prop))               \
+      else `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop))     \
   //pragma translate_on                                                      \
 `endif
 
@@ -85,7 +85,7 @@
 `ifndef VERILATOR                                                                \
   //pragma translate_off                                                         \
   __name: assert property (@(posedge __clk) disable iff (__rst !== '0) (__prop)) \
-    else `ASSERT_RPT(`STRINGIFY(__name), `STRINGIFY(__prop))                     \
+    else `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop))           \
   //pragma translate_on                                                          \
 `endif
 // Note: Above we use (__rst !== '0) in the disable iff statements instead of
@@ -99,7 +99,7 @@
 `ifndef VERILATOR                                                                    \
   //pragma translate_off                                                             \
   __name: assert property (@(posedge __clk) disable iff (__rst !== '0) not (__prop)) \
-    else `ASSERT_RPT(`STRINGIFY(__name), `STRINGIFY(__prop))                         \
+    else `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop))               \
   //pragma translate_on                                                              \
 `endif