tree b73b2beb13c45cb3896b561f9a02676dca5b08be
parent 09402b446218bca323858046dd810ce6c2f94311
author Tom Roberts <tomroberts@lowrisc.org> 1574256796 +0000
committer Philipp Wagner <mail@philipp-wagner.com> 1574352909 +0000

Update lowrisc_ibex to lowRISC/ibex@a264ee6

Relates to #1021
Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
a264ee6e7f654dd2a8114fdf8e802610756917d0

* [make] Add Makefile for common tasks (Tobias Wölfel)
* [doc] Update `mhartid` CSR description (Pirmin Vogel)
* [doc] Document debug CSRs (Pirmin Vogel)
* [rtl] Do not update CSRs upon exceptions in debug mode (Pirmin
  Vogel)
* [DV] umode_tw test (lowRISC/ibex#481) (udinator)
* [DV] Add exit check for setup call (Tobias Wölfel)
* Fix typo in comment (Philipp Wagner)
* [csr tb] Declare registers as a macro list (Tom Roberts)
* [dv] Remove clock gating primitive in `dv/uvm/tb` (Pirmin Vogel)
* [rtl] Add new assertions (Pirmin Vogel)
* [rtl] Rework assertions (Pirmin Vogel)
* [DV] Enable user-mode in DV environment, add basic tests
  (lowRISC/ibex#471) (udinator)
* Update fusesoc usage (Tobias Wölfel)
* Use shared code for Arty A7-100T example (Tobias Wölfel)
* Delay simulator finish (Tobias Wölfel)
* [rtl] Rework `core_busy` signals, remove feedback to clk (Pirmin
  Vogel)
* [rtl] Switch to M mode on debug entry (Tom Roberts)
* Use gitignore for software directory (Tobias Wölfel)
* Update load instruction (Tobias Wölfel)
* [rtl/controller] Remove redundant check in EBREAK handling (Pirmin
  Vogel)
* [rtl/controller] Remove redundant check in execption handling
  (Pirmin Vogel)
* [rtl] Ignore LSB only for writes to `dpc` (Pirmin Vogel)
* Fix formatting of table in simple system (Marek Pikuła)
* Update google_riscv-dv to google/riscv-dv@4b333ba (lowRISC/ibex#462)
  (udinator)
* Add rv32Zicsr target in azure (Tobias Wölfel)
* Update expected failure for riscv-compliance (Tobias Wölfel)
* [funct_cov] Fix GPR assignment bug (lowRISC/ibex#456) (udinator)
* [Doc] Update verification documentation (lowRISC/ibex#449)
  (udinator)
* [funct_cov] Update Makefile options for coverage (lowRISC/ibex#455)
  (udinator)
* [funct_cov] Update Ibex log parsing (lowRISC/ibex#453) (udinator)
* [rtl] Rework access to performance counter CSRs (Pirmin Vogel)
*  Added simple system (Greg Chadwick)
* Added top-level shared directory (Greg Chadwick)
* [DV] clean up stale TODOs (lowRISC/ibex#448) (udinator)
* Update google_riscv-dv to google/riscv-dv@44bec76 (lowRISC/ibex#447)
  (udinator)
* [DV/flow] Integrate with RISCV-DV (lowRISC/ibex#446) (udinator)
* Update google_riscv-dv to google/riscv-dv@cce71d2 (lowRISC/ibex#445)
  (udinator)
* [verilator] Fix a few verilator DV issues (Tom Roberts)
* [rtl] Remove unused set-less-or-equal-than ALU ops (Pirmin Vogel)
* [DV] Assert interrupt during write to MSTATUS and MIE
  (lowRISC/ibex#435) (udinator)
* Add performance counter utils for verilator sims (Greg Chadwick)
* [DV] Add registers testbench (Tom Roberts)
* Error synthesis in Vivado (Pascal Cotret)
* [rtl/lsu] Rework assertion checking response valid (Pirmin Vogel)
* [DV] Increase number of resets in reset_test (lowRISC/ibex#418)
  (udinator)
* [DV] Increase number of illegal instructions generated
  (lowRISC/ibex#426) (udinator)
* [rtl/alu] Remove unused comparison operations (Pirmin Vogel)
* [RTL] Add MultiplierImplementation parameter in top level (Marek
  Pikuła)
* Update google_riscv-dv to google/riscv-dv@46ec4bc (lowRISC/ibex#417)
  (udinator)
* [RTL/Tracer] Fix compressed jump RD write (lowRISC/ibex#416)
  (udinator)
* [DV] Enable timer interrupts (lowRISC/ibex#415) (udinator)
* [DV] Update simulation terminate argument (Tobias Wölfel)
* [DV] testplan documentation (lowRISC/ibex#409) (udinator)
* [DV] Add interrupt wfi test to address coverage hole
  (lowRISC/ibex#410) (udinator)
* Tracer: Decode an all-zero instruction as c.unimp (Philipp Wagner)
* Add Greg Chadwick to CREDITS.md (Greg Chadwick)

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>