)]}'
{
  "commit": "46b06ada169dbde4a505ad191ef379e711bd6eef",
  "tree": "86da0e98002c3312ca1e1a581c98132b0291f851",
  "parents": [
    "62e6b1b85aef9adedefc1d637351892167f3a99f"
  ],
  "author": {
    "name": "Viswanadha Bazawada",
    "email": "viswanadha.bazawada@ensilica.com",
    "time": "Mon Feb 07 14:41:42 2022 +0000"
  },
  "committer": {
    "name": "weicaiyang",
    "email": "49293026+weicaiyang@users.noreply.github.com",
    "time": "Mon May 16 10:09:15 2022 -0700"
  },
  "message": "[spi_host/dv]Modified Pass Through Test and Review Changes\n\n- Modified Error Cmd Test\n- Modified Passthrough Test\n- Added Structs To DV Doc\n- Changed Winbond to V3 In TestPlan\n- CG Updated in TestPlan\n- Modified Event And Stress Seq as per Review\n- Modified Event And Error As Per Review\n- Modified Event With Check Error and Event tasks\n- Modifications As Per Review\n- Renamed Error TX RX Test To Overflow Underflow\n- Removed sck_gate_en From Tb\n- Passthrough Os Clarified To Pull High\n\nSigned-off-by: Viswanadha Bazawada \u003cviswanadha.bazawada@ensilica.com\u003e\n",
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