tree dfcdffeeaf2ba81d1b2c2fed6eee51364824d181
parent 76e35160386278edee3b4bcc5b5a20656a1f6722
author Pirmin Vogel <vogelpi@lowrisc.org> 1615970162 +0100
committer Pirmin Vogel <vogelpi@lowrisc.org> 1616058895 +0100

[aes] Doc clearing sequence upon reset and align STATUS reg reset value

Upon reset, the AES module first performs a PRNG reseed and then clears
key, IV and data registers with pseudo-random data. Only after that, the
module becomes ready for software initialization.

This commit explicitly documents this behavior and changes the reset value
of the IDLE and INPUT_READY fields in the STATUS register. Both should be
low (not idle, not ready to receive inputs) when coming out of reset.
At the end of the clearing sequence, both bits will be high.

This is related to lowRISC/OpenTitan#5646.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>