tree beaca0be2fd81a1a81bad95a57dd5ac16280e87e
parent c909eb30d2be0479d5b013352eab832b46fb41a2
author Michael Schaffner <msf@google.com> 1572365662 -0700
committer Michael Schaffner <msf@google.com> 1572557464 -0700

[prim_fifo_sync] Add synchronous clear signal to the FIFO primitive

This adds a synchronous clr signal to the synchronous FIFO primitive
which synchronously resets the read and write pointers to zero if
asserted. This has been used to replace some of the gated asynchronous
resets in the design.