)]}'
{
  "commit": "42d032fb55c5d30b1834b3fe744c8584fedaba11",
  "tree": "f54e58bad6ec117317bb76fa5f25debf34790139",
  "parents": [
    "3e9d888815f2469b87e2a4f6c5835df41f782ca8"
  ],
  "author": {
    "name": "Srikrishna Iyer",
    "email": "sriyer@google.com",
    "time": "Wed Mar 04 23:55:44 2020 -0800"
  },
  "committer": {
    "name": "sriyerg",
    "email": "46467186+sriyerg@users.noreply.github.com",
    "time": "Thu Mar 05 12:27:56 2020 -0800"
  },
  "message": "[top_earlgrey dv] Enabled DV with dvsim\n\n- Tool updates to enable sw build using meson wihin dvsim\n- SW based tests now passing at chip level\n- Added chip_sim_cfg.hjson to the top_earlgrey sim cfgs set so that chip\nlevel DV tests get run as a part of nightly and CI\n\nSigned-off-by: Srikrishna Iyer \u003csriyer@google.com\u003e\n",
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