// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  name: "pwrmgr"
  // TODO: remove the common testplans if not applicable
  import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson"]
  testpoints: [
    {
      name: smoke
      desc: '''
            Smoke test exercising the pwrmgr state transitions.

            - Brings pwrmgr out of POR.
            - Enables wakeup.
            - Triggers SW initiated low power transition with reset settings
              in `control` CSR.
            - Triggers wakeup.
            - Enables reset.
            - Triggers a reset.
            - Waits for pwrmgr to be out of reset.

            **Stimulus**:
            - CSR writes to `wakeup_en`, `reset_en`, and `low_power_hint`.
            - Needs many input pins to line up correctly in order to prevent the
              pwrmgr from waiting forever.

            **Checks**:
            - Checks that fast fsm is active checking the CSR `ctrl_cfg_regwen`
              is set.
            - Checks that the wakeup and reset causes are as expected reading
              CSRs `wake_status` and `reset_status`.
            - Checks the output `pwr_rst_req.reset_cause` matches a low power or
              reset cause.
            - Checks the output `pwr_rst_req.rstreqs` matches the enabled
              resets.
            '''
      milestone: V1
      tests: ["pwrmgr_smoke"]
    }
    {
      name: wakeup
      desc: '''
            Test random wakeup, wakeup_en, wake_info_capture_dis, and
            interrupt.

            The different wakeup inputs can be disabled via bits in the
            `wakeup_en` CSR. Update of `wakeup_info` can be disabled
            via the `wake_info_capture_dis` CSR. Any wakeup causes an
            interrupt unless interrupts are disabled.

            **Stimulus**:
            - Sets `wakeup_en` randomly but don't set it to zero, or the
              test will timeout.
            - Set `wake_info_capture_dis` randomly on and off.
            - Bring pwrmgr to low power.
            - Set `wakeups_i` inputs randomly.
            - Set `intr_enable` randomly.

            **Checks**:
            - Waits for fast fsm to become active reading `ctrl_cfg_regwen`
              until it becomes 1.
            - Depending on `wakeups_i`:
              - If all wakeups are disabled, wait some time checking the
                state remains inactive.
              - Set `wakeups_i` so at least one is enabled.
            - Checks `ip_clk_en` output has a low transition.
            - Checks `wakeup_status` CSR during transition to active state
              since the reset involved will clear the wakeups_i input.
            - Checks the `wakeup_info` CSR.
            - Checks the output `pwr_rst_req.reset_cause` is `Wake` (1).
            - Check that `intr_wakeup_o` is set according to `intr_enable` CSR.
            - Coverage collected by `wakeup_cg` and `wakeup_intr_cg`.
            '''
      milestone: V2
      tests: ["pwrmgr_wakeup"]
    }
    {
      name: control_clks
      desc: '''
            Test CSR control of peripheral clocks during low power.

            The peripheral clocks can be configured to remain on or be turned
            off during low power with bits in the `control` CSR register. The
            usb clock can also be configured off in active mode.

            **Stimulus**:
            - Sets these control bits at random.
            - Cause a low power transition and wakeup.

            **Checks**:
            - The clock enable outputs to the AST clocks during a low
              power transition match the control bits.
            - The usb clock enable is also checked during active mode against
              the control register.
            '''
      milestone: V2
      tests: ["pwrmgr_wakeup"]
    }
    {
      name: aborted_lowpower
      desc: '''
            Test aborted low power transitions.

            Low power transitions can be aborted in two cases:
            - The processor gets an interrupt soon after a low power entry is
              triggered.
            - OTP, LC, or FLASH are not idle.
            This test aborts low power transitions, and disables any wakeups,
            so the test would timeout if low power was entered.

            **Stimulus**:
            - Bring pwrmgr to low power.
            - Either disable `pwr_cpu.core_sleeping` or keep some of `lc_idle`,
              `otp_idle`, or `flash_idle` inputs off.
            - Disable all wakeup enables.
            - Randomly set `wakeup_info_capture_dis` CSR.

            **Checks**:
            - The `ctrl_cfg_regwen` CSR reads as 1 on the first attempt.
            - Checks the output `pwr_rst_req.reset_cause` doesn't change for
              a bounded amount of time.
            - Check that the `wakeup_info` CSR flags either `fall_through` or
              `abort` events when capture is enabled.
            '''
      milestone: V2
      tests: []
    }
    {
      name: reset
      desc: '''
            Test random reset and reset_en.

            Conditional reset inputs can be disabled via bits in the `reset_en`
            CSR, while escalation and main power are unconditional. Resets can
            be triggered either in active or low power state.

            **Stimulus**:
            - Sets `reset_en` randomly.
            - Randomly choose whether to put the unit in low power mode.
            - Generate resets randomly in value and time:
              - Conditionals via rstreqs_i,
              - Main power glitch via rst_main_ni.
              - Escalation via `esc_rst_tx_i`.

            **Checks**:
            - Waits for fast fsm to become active reading `ctrl_cfg_regwen`
              until it becomes 1.
            - Checks the `reset_status` CSRs.
            - Checks `ip_clk_en` output has a low transition.
            - SVA that when `pwr_rst_req.reset_cause` is HwReq, and the output
             `pwr_rst_req.rstreqs` matches the unconditional and enabled
             conditional resets inputs.
            '''
      milestone: V2
      tests: ["pwrmgr_reset"]
    }
    {
      name: main_power_glitch_reset
      desc: '''
            Test reset due to a glitch in main power.

            A power glitch causes an unconditional reset.

            **Stimulus**:
            - Set the rst_main_ni input low indicating a main power glitch.

            **Checks**:
            - Waits for fast fsm to become active reading `ctrl_cfg_regwen`
              until it becomes 1.
            - Checks the `reset_status` CSRs.
            - Checks `ip_clk_en` output has a low transition.
            - Checks the output `pwr_rst_req.reset_cause` matches HwReq.
            - Checks the output `pwr_rst_req.rstreqs` matches power glitch.
            '''
      milestone: V2
      tests: ["pwrmgr_reset"]
    }
    {
      name: reset_wakeup_race
      desc: '''
            Test wakeup from low power and reset request almost coinciding.

            If a wakeup from low power and a reset occur at nearly the same time
            the system handles them one at a time.

            **Stimulus**:
            - Trigger reset and wakeup from low power as described for other
              testpoints.
            - Make sure to test them coinciding also.

            **Check**:
            - Similar tests as for the wakeup and reset testpoints, except
              making sure they happen per the triggering order.
              '''
      milestone: V2
      tests: []
    }
    {
      name: lowpower_wakeup_race
      desc: '''
            Test wakeups coming close to lowpower entry.

            If low power entry and a wakeup are closely aligned the hardware
            could get confused. Notice this is very unlikely, since wakeup is
            only sensed when the slow fsm is in LowPower state.

            **Stimulus**:
            - Trigger low power entry as described for other testpoints.
            - Have all wakeups enabled.
            - Assert wakeups_i in the temporal neighborhood of low power
              entry.

            **Check**:
            - No timeout occurs.
            - Either pwrmgr remains active or a full low power cycle occurs.
            '''
      milestone: V2
      tests: []
    }
    {
      name: stress
      desc: '''The standard stress test.'''
      milestone: V3
      tests: []
    }
  ]

  covergroups: [
    {
      name: wakeup_ctrl_cg
      desc: '''
            Collects coverage on wakeup enable and capture functionality.

            This is collected per individual wakeup bit. Covergroup contains
            coverpoints for the `wakeup_en` CSR bit, `wakeup_info_capture_dis`
            CSR, `wakeups_i` input bit, and `wakeup_status` CSR bit, and their
            cross.
            '''
    }
    {
      name: wakeup_intr_cg
      desc: '''
            Collects coverage on interrupts for wakeup functionality.

            This is collected per individual wakeup bit. Covergroup contains
            coverpoints for the `intr_en` CSR, the `wakeup_status` CSR bit,
            and `intr_status` CSR, and their cross.
            '''
    }
    {
      name: control_cg
      desc: '''
            Collects coverage on clock and power bits from `control` CSR during
            a lowpower transition and active state.
            '''
    }
    {
      name: reset_cg
      desc: '''
            Collects coverage related to reset reporting.

            Covergroup contains coverpoints for the `rstreqs_i`, alert
            escalation and power glitch inputs, `reset_en`, `reset_status`,
            `escalate_reset_status`, output `pwr_rst_o.rstreqs`, and whether
            reset is asserted during low power state, and suitable crosses.
            '''
    }
    {
      name: reset_lowpower_distance_cg
      desc: '''
            This is a temporal cover statement that records the temporal
            distance between when lowpower entry and reset trigger, in order
            to measure coverage of the reset_wakeup_race sequence.
            '''
    }
  ]
}