)]}'
{
  "commit": "3fe9fdd8b9b3e18c616e7e400155ba7d48040abb",
  "tree": "eda92b099cc8aca2b7fadb339276ecf94f2051da",
  "parents": [
    "bf615137188e1803ca67012927023159e091c109"
  ],
  "author": {
    "name": "Srikrishna Iyer",
    "email": "sriyer@google.com",
    "time": "Thu Mar 17 14:37:31 2022 -0700"
  },
  "committer": {
    "name": "Srikrishna Iyer",
    "email": "46467186+sriyerg@users.noreply.github.com",
    "time": "Thu Mar 17 18:30:39 2022 -0700"
  },
  "message": "[chip dv] Fix AST cfg initialization - part 3\n\n- Add knob `do_creator_sw_cfg_ast_cfg` to control whether the AST init\n  is done.\n- Change `creator_sw_cfg_ast_cfg_data` to reflect the full set of values\n  programmed, including the last REGAL register. This simplifies the\n  logic a bit.\n\nSigned-off-by: Srikrishna Iyer \u003csriyer@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6e264609b5d23b34e7bd0e47f9c025449c87451c",
      "old_mode": 33188,
      "old_path": "hw/top_earlgrey/dv/env/chip_env_cfg.sv",
      "new_id": "dbadce77ef08599bfc88fcbe4cd8ec37a75b6668",
      "new_mode": 33188,
      "new_path": "hw/top_earlgrey/dv/env/chip_env_cfg.sv"
    },
    {
      "type": "modify",
      "old_id": "d20bbff77d83d953a7006c6f8dfdd9c20229071f",
      "old_mode": 33188,
      "old_path": "hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv",
      "new_id": "b94e740e0b076310351e86d83ac4999b80bac691",
      "new_mode": 33188,
      "new_path": "hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "hw/top_earlgrey/dv/env/seq_lib/chip_stub_cpu_base_vseq.sv",
      "new_id": "974f699fbbbcb6cc1d3e57f11317aa71e0f3417f",
      "new_mode": 33188,
      "new_path": "hw/top_earlgrey/dv/env/seq_lib/chip_stub_cpu_base_vseq.sv"
    },
    {
      "type": "modify",
      "old_id": "9bd7507e4ee00bf305d1fde282e772877d8acf18",
      "old_mode": 33188,
      "old_path": "hw/top_earlgrey/dv/tests/chip_base_test.sv",
      "new_id": "81c846d74e5c281bce70f58ff1853a1f529da657",
      "new_mode": 33188,
      "new_path": "hw/top_earlgrey/dv/tests/chip_base_test.sv"
    }
  ]
}