diff --git a/hw/ip/otp_ctrl/data/otp_ctrl.hjson b/hw/ip/otp_ctrl/data/otp_ctrl.hjson
index 7c06f88..aae57c1 100644
--- a/hw/ip/otp_ctrl/data/otp_ctrl.hjson
+++ b/hw/ip/otp_ctrl/data/otp_ctrl.hjson
@@ -991,9 +991,6 @@
       swaccess: "rw",
       hwaccess: "hro",
       regwen:   "CHECK_REGWEN",
-      tags: [ // Do not write to this automatically, as it may trigger unintended side effects
-              // like spurious escalations / alerts.
-              "excl:CsrAllTests:CsrExclWrite"],
       fields: [
         { bits: "31:0",
           desc: '''
diff --git a/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl b/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl
index 575fb5a..3e745b0 100644
--- a/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl
+++ b/hw/ip/otp_ctrl/data/otp_ctrl.hjson.tpl
@@ -656,9 +656,6 @@
       swaccess: "rw",
       hwaccess: "hro",
       regwen:   "CHECK_REGWEN",
-      tags: [ // Do not write to this automatically, as it may trigger unintended side effects
-              // like spurious escalations / alerts.
-              "excl:CsrAllTests:CsrExclWrite"],
       fields: [
         { bits: "31:0",
           desc: '''
diff --git a/hw/ip/otp_ctrl/dv/env/otp_ctrl_if.sv b/hw/ip/otp_ctrl/dv/env/otp_ctrl_if.sv
index f5f9a8e..99dfc52 100644
--- a/hw/ip/otp_ctrl/dv/env/otp_ctrl_if.sv
+++ b/hw/ip/otp_ctrl/dv/env/otp_ctrl_if.sv
@@ -67,10 +67,9 @@
 
   // TODO: for lc_tx, except esc_en signal, all value different from On is treated as Off,
   // technically we can randomize values here once scb supports
-  task automatic init();
+  task automatic init(lc_ctrl_pkg::lc_tx_t lc_seed_hw_rd_en_val = lc_ctrl_pkg::On);
     lc_creator_seed_sw_rw_en_i = lc_ctrl_pkg::On;
-    // TODO: check with designer if we will remove this
-    lc_seed_hw_rd_en_i         = lc_ctrl_pkg::Off;
+    lc_seed_hw_rd_en_i         = lc_seed_hw_rd_en_val;
     lc_dft_en_i                = lc_ctrl_pkg::Off;
     lc_escalate_en_i           = lc_ctrl_pkg::Off;
     lc_check_byp_en_i          = lc_ctrl_pkg::Off;
diff --git a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv
index 071f156..f9f1a5e 100644
--- a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv
+++ b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv
@@ -32,7 +32,7 @@
     super.dut_init(reset_kind);
     cfg.backdoor_clear_mem = 0;
     // reset power init pin and lc pins
-    cfg.otp_ctrl_vif.init();
+    cfg.otp_ctrl_vif.init(randomize_lc_tx_t_val());
     if (do_otp_ctrl_init && do_apply_reset) otp_ctrl_init();
     cfg.clk_rst_vif.wait_clks($urandom_range(0, 10));
     if (do_otp_pwr_init && do_apply_reset) otp_pwr_init();
@@ -71,6 +71,17 @@
     super.read_and_check_all_csrs_after_reset();
   endtask
 
+  // This function randomizes lc_tx_t with 25% lc_ctrl_pkg::On, 25% lc_ctrl_pkg::Off,
+  // and 50% random values
+  virtual function lc_ctrl_pkg::lc_tx_t randomize_lc_tx_t_val();
+    randomize_lc_tx_t_val = $urandom();
+    if ($urandom_range(0, 1)) begin
+      `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(randomize_lc_tx_t_val,
+          randomize_lc_tx_t_val inside {lc_ctrl_pkg::On, lc_ctrl_pkg::Off};)
+    end
+
+  endfunction
+
   // this task triggers an OTP write sequence via the DAI interface
   virtual task dai_wr(bit [TL_DW-1:0] addr,
                       bit [TL_DW-1:0] wdata0,
diff --git a/hw/ip/otp_ctrl/dv/tb.sv b/hw/ip/otp_ctrl/dv/tb.sv
index a433f70..d8a3512 100644
--- a/hw/ip/otp_ctrl/dv/tb.sv
+++ b/hw/ip/otp_ctrl/dv/tb.sv
@@ -146,12 +146,19 @@
   bind `OTP_CTRL_MEM_HIER mem_bkdr_if #(.MEM_ECC(1)) mem_bkdr_if();
 
   initial begin
-    // these SVA checks the lc_escalate_en is either Off or On, we will use more than these 2 values.
-    // If it's not Off, it should be On
+    // These SVA checks the lc_escalate_en is either Off or On, we will use more than these 2 values.
+    // If it's not Off, it should be On.
     $assertoff(0, tb.dut.u_prim_lc_sync_escalate_en.CheckTransients_A);
     $assertoff(0, tb.dut.u_prim_lc_sync_escalate_en.CheckTransients0_A);
     $assertoff(0, tb.dut.u_prim_lc_sync_escalate_en.CheckTransients1_A);
 
+    // These SVA checks the lc_sync_seed_hw_rd_en is either Off or On, we will use more than these
+    // 2 values.
+    // If it's not On, it should be Off.
+    $assertoff(0, tb.dut.u_prim_lc_sync_seed_hw_rd_en.CheckTransients_A);
+    $assertoff(0, tb.dut.u_prim_lc_sync_seed_hw_rd_en.CheckTransients0_A);
+    $assertoff(0, tb.dut.u_prim_lc_sync_seed_hw_rd_en.CheckTransients1_A);
+
     // drive clk and rst_n from clk_if
     clk_rst_if.set_active();
     uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if);