diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 88ee8ad..b557c9c 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -7823,7 +7823,7 @@
       }
       {
         name: IOA0
-        type: InputStd
+        type: BidirStd
         bank: VIOA
         connection: muxed
         desc: Muxed IO pad
@@ -7831,7 +7831,7 @@
       }
       {
         name: IOA1
-        type: InputStd
+        type: BidirStd
         bank: VIOA
         connection: muxed
         desc: Muxed IO pad
@@ -7839,7 +7839,7 @@
       }
       {
         name: IOA2
-        type: InputStd
+        type: BidirStd
         bank: VIOA
         connection: muxed
         desc: Muxed IO pad
@@ -7847,7 +7847,7 @@
       }
       {
         name: IOA3
-        type: InputStd
+        type: BidirStd
         bank: VIOA
         connection: muxed
         desc: Muxed IO pad
@@ -7855,7 +7855,7 @@
       }
       {
         name: IOA4
-        type: BidirOd
+        type: BidirStd
         bank: VIOA
         connection: muxed
         desc: Muxed IO pad
@@ -7863,195 +7863,227 @@
       }
       {
         name: IOA5
-        type: BidirOd
+        type: BidirStd
         bank: VIOA
         connection: muxed
         desc: Muxed IO pad
         idx: 5
       }
       {
-        name: IOB0
-        type: InputStd
-        bank: VIOB
+        name: IOA6
+        type: BidirOd
+        bank: VIOA
         connection: muxed
         desc: Muxed IO pad
         idx: 6
       }
       {
-        name: IOB1
-        type: InputStd
-        bank: VIOB
+        name: IOA7
+        type: BidirOd
+        bank: VIOA
         connection: muxed
         desc: Muxed IO pad
         idx: 7
       }
       {
-        name: IOB2
-        type: InputStd
-        bank: VIOB
+        name: IOA8
+        type: BidirOd
+        bank: VIOA
         connection: muxed
         desc: Muxed IO pad
         idx: 8
       }
       {
-        name: IOB3
-        type: InputStd
+        name: IOB0
+        type: BidirStd
         bank: VIOB
         connection: muxed
         desc: Muxed IO pad
         idx: 9
       }
       {
-        name: IOB4
-        type: InputStd
+        name: IOB1
+        type: BidirStd
         bank: VIOB
         connection: muxed
         desc: Muxed IO pad
         idx: 10
       }
       {
-        name: IOB5
-        type: InputStd
+        name: IOB2
+        type: BidirStd
         bank: VIOB
         connection: muxed
         desc: Muxed IO pad
         idx: 11
       }
       {
-        name: IOB6
-        type: InputStd
+        name: IOB3
+        type: BidirStd
         bank: VIOB
         connection: muxed
         desc: Muxed IO pad
         idx: 12
       }
       {
-        name: IOB7
-        type: InputStd
+        name: IOB4
+        type: BidirStd
         bank: VIOB
         connection: muxed
         desc: Muxed IO pad
         idx: 13
       }
       {
-        name: IOB8
-        type: BidirOd
+        name: IOB5
+        type: BidirStd
         bank: VIOB
         connection: muxed
         desc: Muxed IO pad
         idx: 14
       }
       {
+        name: IOB6
+        type: BidirStd
+        bank: VIOB
+        connection: muxed
+        desc: Muxed IO pad
+        idx: 15
+      }
+      {
+        name: IOB7
+        type: BidirStd
+        bank: VIOB
+        connection: muxed
+        desc: Muxed IO pad
+        idx: 16
+      }
+      {
+        name: IOB8
+        type: BidirStd
+        bank: VIOB
+        connection: muxed
+        desc: Muxed IO pad
+        idx: 17
+      }
+      {
         name: IOB9
         type: BidirOd
         bank: VIOB
         connection: muxed
         desc: Muxed IO pad
-        idx: 15
-      }
-      {
-        name: IOB10
-        type: InputStd
-        bank: VIOB
-        connection: muxed
-        desc: Muxed IO pad
-        idx: 16
-      }
-      {
-        name: IOB11
-        type: InputStd
-        bank: VIOB
-        connection: muxed
-        desc: Muxed IO pad
-        idx: 17
-      }
-      {
-        name: IOC0
-        type: InputStd
-        bank: VCC
-        connection: muxed
-        desc: Muxed IO pad
         idx: 18
       }
       {
-        name: IOC1
-        type: InputStd
-        bank: VCC
+        name: IOB10
+        type: BidirOd
+        bank: VIOB
         connection: muxed
         desc: Muxed IO pad
         idx: 19
       }
       {
-        name: IOC2
-        type: InputStd
-        bank: VCC
+        name: IOB11
+        type: BidirOd
+        bank: VIOB
         connection: muxed
         desc: Muxed IO pad
         idx: 20
       }
       {
-        name: IOC3
-        type: InputStd
-        bank: VCC
+        name: IOB12
+        type: BidirOd
+        bank: VIOB
         connection: muxed
         desc: Muxed IO pad
         idx: 21
       }
       {
-        name: IOC4
-        type: InputStd
+        name: IOC0
+        type: BidirStd
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
         idx: 22
       }
       {
-        name: IOC5
-        type: InputStd
+        name: IOC1
+        type: BidirStd
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
         idx: 23
       }
       {
-        name: IOC6
-        type: InputStd
+        name: IOC2
+        type: BidirStd
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
         idx: 24
       }
       {
-        name: IOC7
-        type: InputStd
+        name: IOC3
+        type: BidirStd
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
         idx: 25
       }
       {
-        name: IOC8
-        type: BidirOd
+        name: IOC4
+        type: BidirStd
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
         idx: 26
       }
       {
-        name: IOC9
-        type: BidirOd
+        name: IOC5
+        type: BidirStd
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
         idx: 27
       }
       {
+        name: IOC6
+        type: BidirStd
+        bank: VCC
+        connection: muxed
+        desc: Muxed IO pad
+        idx: 28
+      }
+      {
+        name: IOC7
+        type: BidirStd
+        bank: VCC
+        connection: muxed
+        desc: Muxed IO pad
+        idx: 29
+      }
+      {
+        name: IOC8
+        type: BidirStd
+        bank: VCC
+        connection: muxed
+        desc: Muxed IO pad
+        idx: 30
+      }
+      {
+        name: IOC9
+        type: BidirStd
+        bank: VCC
+        connection: muxed
+        desc: Muxed IO pad
+        idx: 31
+      }
+      {
         name: IOC10
         type: BidirOd
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
-        idx: 28
+        idx: 32
       }
       {
         name: IOC11
@@ -8059,87 +8091,95 @@
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
-        idx: 29
-      }
-      {
-        name: IOR0
-        type: InputStd
-        bank: VCC
-        connection: muxed
-        desc: Muxed IO pad
-        idx: 30
-      }
-      {
-        name: IOR1
-        type: InputStd
-        bank: VCC
-        connection: muxed
-        desc: Muxed IO pad
-        idx: 31
-      }
-      {
-        name: IOR2
-        type: InputStd
-        bank: VCC
-        connection: muxed
-        desc: Muxed IO pad
-        idx: 32
-      }
-      {
-        name: IOR3
-        type: InputStd
-        bank: VCC
-        connection: muxed
-        desc: Muxed IO pad
         idx: 33
       }
       {
-        name: IOR4
-        type: InputStd
+        name: IOC12
+        type: BidirOd
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
         idx: 34
       }
       {
-        name: IOR5
-        type: InputStd
+        name: IOR0
+        type: BidirStd
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
         idx: 35
       }
       {
-        name: IOR6
-        type: InputStd
+        name: IOR1
+        type: BidirStd
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
         idx: 36
       }
       {
-        name: IOR7
-        type: InputStd
+        name: IOR2
+        type: BidirStd
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
         idx: 37
       }
       {
+        name: IOR3
+        type: BidirStd
+        bank: VCC
+        connection: muxed
+        desc: Muxed IO pad
+        idx: 38
+      }
+      {
+        name: IOR4
+        type: BidirStd
+        bank: VCC
+        connection: muxed
+        desc: Muxed IO pad
+        idx: 39
+      }
+      {
+        name: IOR5
+        type: BidirStd
+        bank: VCC
+        connection: muxed
+        desc: Muxed IO pad
+        idx: 40
+      }
+      {
+        name: IOR6
+        type: BidirStd
+        bank: VCC
+        connection: muxed
+        desc: Muxed IO pad
+        idx: 41
+      }
+      {
+        name: IOR7
+        type: BidirStd
+        bank: VCC
+        connection: muxed
+        desc: Muxed IO pad
+        idx: 42
+      }
+      {
         name: IOR8
         type: BidirOd
         bank: VCC
         connection: direct
-        desc: Dedicated systrst_ctrl output pad
+        desc: Dedicated sysrst_ctrl output (ec_rst_l)
         idx: 22
       }
       {
         name: IOR9
         type: BidirOd
         bank: VCC
-        connection: muxed
-        desc: Muxed IO pad
-        idx: 38
+        connection: direct
+        desc: Dedicated sysrst_ctrl output (pwrb_out)
+        idx: 23
       }
       {
         name: IOR10
@@ -8147,7 +8187,7 @@
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
-        idx: 39
+        idx: 43
       }
       {
         name: IOR11
@@ -8155,7 +8195,7 @@
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
-        idx: 40
+        idx: 44
       }
       {
         name: IOR12
@@ -8163,7 +8203,7 @@
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
-        idx: 41
+        idx: 45
       }
       {
         name: IOR13
@@ -8171,7 +8211,7 @@
         bank: VCC
         connection: muxed
         desc: Muxed IO pad
-        idx: 42
+        idx: 46
       }
     ]
   }
@@ -8434,8 +8474,8 @@
       {
         instance: sysrst_ctrl_aon
         port: pwrb_out
-        connection: muxed
-        pad: ""
+        connection: direct
+        pad: IOR9
         desc: ""
       }
     ]
@@ -9456,9 +9496,9 @@
         width: 1
         type: output
         idx: -1
-        pad: ""
-        connection: muxed
-        glob_idx: 67
+        pad: IOR9
+        connection: direct
+        glob_idx: 22
       }
     ]
     io_counts:
@@ -9467,15 +9507,15 @@
       {
         inouts: 11
         inputs: 3
-        outputs: 8
-        pads: 23
+        outputs: 9
+        pads: 24
       }
       muxed:
       {
         inouts: 42
         inputs: 23
-        outputs: 26
-        pads: 43
+        outputs: 25
+        pads: 47
       }
     }
   }
@@ -9496,55 +9536,55 @@
             name: tap0
             pad: IOC8
             desc: TAP strap signal.
-            idx: 26
+            idx: 30
           }
           {
             name: tap1
             pad: IOC5
             desc: TAP strap signal.
-            idx: 23
+            idx: 27
           }
           {
             name: dft0
             pad: IOC3
             desc: DFT strap signal.
-            idx: 21
+            idx: 25
           }
           {
             name: dft1
             pad: IOC4
             desc: DFT strap signal.
-            idx: 22
+            idx: 26
           }
           {
             name: tck
-            pad: SPI_DEV_CLK
-            desc: JTAG tck signal, overlaid on SPI_DEV.
-            idx: 54
+            pad: IOR3
+            desc: JTAG tck signal.
+            idx: 38
           }
           {
             name: tms
-            pad: SPI_DEV_CS_L
-            desc: JTAG tms signal, overlaid on SPI_DEV.
-            idx: 55
+            pad: IOR0
+            desc: JTAG tms signal.
+            idx: 35
           }
           {
             name: trst_n
-            pad: IOC0
-            desc: JTAG trst_n signal, maps to MIO Pad 18.
-            idx: 18
+            pad: IOR4
+            desc: JTAG trst_n signal.
+            idx: 39
           }
           {
             name: tdi
-            pad: SPI_DEV_D0
-            desc: JTAG tdi signal, overlaid on SPI_DEV.
-            idx: 47
+            pad: IOR2
+            desc: JTAG tdi signal.
+            idx: 37
           }
           {
             name: tdo
-            pad: SPI_DEV_D1
-            desc: JTAG tdo signal, overlaid on SPI_DEV.
-            idx: 48
+            pad: IOR1
+            desc: JTAG tdo signal.
+            idx: 36
           }
         ]
       }
@@ -9557,11 +9597,6 @@
         [
           CC1
           CC2
-          IOC1
-          IOC2
-          IOC3
-          IOC4
-          IOC5
           SPI_DEV_D2
           SPI_DEV_D3
           SPI_HOST_CLK
@@ -9575,6 +9610,16 @@
           FLASH_TEST_MODE1
           FLASH_TEST_MODE2
           FLASH_TEST_MODE3
+          IOB10
+          IOB11
+          IOB12
+          IOC0
+          IOC1
+          IOC12
+          IOR0
+          IOR1
+          IOR2
+          IOR3
           IOR4
           IOR5
           IOR6
@@ -9687,43 +9732,43 @@
         [
           {
             name: tap0
-            pad: IOC2
+            pad: IOC0
             desc: TAP strap signal, maps to a stubbed-off MIO.
-            idx: 20
+            idx: 22
           }
           {
             name: tap1
-            pad: IOB10
+            pad: IOB7
             desc: TAP strap signal, maps to MIO pad 16.
             idx: 16
           }
           {
             name: dft0
-            pad: IOC3
+            pad: IOC1
             desc: DFT strap signal, maps to a stubbed-off MIO.
-            idx: 21
+            idx: 23
           }
           {
             name: dft1
-            pad: IOC4
+            pad: IOC12
             desc: DFT strap signal, maps to a stubbed-off MIO.
-            idx: 22
+            idx: 34
           }
           {
             name: tck
             pad: SPI_DEV_CLK
             desc: JTAG tck signal, overlaid on SPI_DEV.
-            idx: 54
+            idx: 58
           }
           {
             name: tms
             pad: SPI_DEV_CS_L
             desc: JTAG tms signal, overlaid on SPI_DEV.
-            idx: 55
+            idx: 59
           }
           {
             name: trst_n
-            pad: IOC0
+            pad: IOB9
             desc: JTAG trst_n signal, maps to MIO pad 18.
             idx: 18
           }
@@ -9731,13 +9776,13 @@
             name: tdi
             pad: SPI_DEV_D0
             desc: JTAG tdi signal, overlaid on SPI_DEV.
-            idx: 47
+            idx: 51
           }
           {
             name: tdo
             pad: SPI_DEV_D1
             desc: JTAG tdo signal, overlaid on SPI_DEV.
-            idx: 48
+            idx: 52
           }
         ]
       }
diff --git a/hw/top_earlgrey/data/pins_nexysvideo.xdc b/hw/top_earlgrey/data/pins_nexysvideo.xdc
index 2cb510e..7992fdb 100644
--- a/hw/top_earlgrey/data/pins_nexysvideo.xdc
+++ b/hw/top_earlgrey/data/pins_nexysvideo.xdc
@@ -28,14 +28,14 @@
 
 
 ## LEDs
-set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS25 } [get_ports { IOB2 }]; #IO_L15P_T2_DQS_13 Sch=led[0]
-set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS25 } [get_ports { IOB3 }]; #IO_L15N_T2_DQS_13 Sch=led[1]
-set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS25 } [get_ports { IOB4 }]; #IO_L17P_T2_13 Sch=led[2]
-set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS25 } [get_ports { IOB5 }]; #IO_L17N_T2_13 Sch=led[3]
-set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS25 } [get_ports { IOB6 }]; #IO_L14N_T2_SRCC_13 Sch=led[4]
-set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS25 } [get_ports { IOB7 }]; #IO_L16N_T2_13 Sch=led[5]
-set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS25 } [get_ports { IOB8 }]; #IO_L16P_T2_13 Sch=led[6]
-set_property -dict { PACKAGE_PIN Y13   IOSTANDARD LVCMOS25 } [get_ports { IOB9 }]; #IO_L5P_T0_13 Sch=led[7]
+set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS25 } [get_ports { IOA8 }]; #IO_L15P_T2_DQS_13 Sch=led[0]
+set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS25 } [get_ports { IOB0 }]; #IO_L15N_T2_DQS_13 Sch=led[1]
+set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS25 } [get_ports { IOB1 }]; #IO_L17P_T2_13 Sch=led[2]
+set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS25 } [get_ports { IOB2 }]; #IO_L17N_T2_13 Sch=led[3]
+set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS25 } [get_ports { IOB3 }]; #IO_L14N_T2_SRCC_13 Sch=led[4]
+set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS25 } [get_ports { IOB4 }]; #IO_L16N_T2_13 Sch=led[5]
+set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS25 } [get_ports { IOB5 }]; #IO_L16P_T2_13 Sch=led[6]
+set_property -dict { PACKAGE_PIN Y13   IOSTANDARD LVCMOS25 } [get_ports { IOB6 }]; #IO_L5P_T0_13 Sch=led[7]
 
 
 ## Buttons
@@ -54,8 +54,8 @@
 set_property -dict { PACKAGE_PIN G22  IOSTANDARD LVCMOS12 } [get_ports { IOA3 }]; #IO_L24N_T3_16 Sch=sw[3]
 set_property -dict { PACKAGE_PIN H17  IOSTANDARD LVCMOS12 } [get_ports { IOA4 }]; #IO_L6P_T0_15 Sch=sw[4]
 set_property -dict { PACKAGE_PIN J16  IOSTANDARD LVCMOS12 } [get_ports { IOA5 }]; #IO_0_15 Sch=sw[5]
-set_property -dict { PACKAGE_PIN K13  IOSTANDARD LVCMOS12 } [get_ports { IOB0 }]; #IO_L19P_T3_A22_15 Sch=sw[6]
-set_property -dict { PACKAGE_PIN M17  IOSTANDARD LVCMOS12 } [get_ports { IOB1 }]; #IO_25_15 Sch=sw[7]
+set_property -dict { PACKAGE_PIN K13  IOSTANDARD LVCMOS12 } [get_ports { IOA6 }]; #IO_L19P_T3_A22_15 Sch=sw[6]
+set_property -dict { PACKAGE_PIN M17  IOSTANDARD LVCMOS12 } [get_ports { IOA7 }]; #IO_25_15 Sch=sw[7]
 
 
 ## OLED Display
@@ -115,14 +115,14 @@
 
 
 ## Pmod header JA
-set_property -dict { PACKAGE_PIN AB22  IOSTANDARD LVCMOS33 } [get_ports { IOC6 }]; #IO_L10N_T1_D15_14 Sch=ja[1]
-set_property -dict { PACKAGE_PIN AB21  IOSTANDARD LVCMOS33 } [get_ports { IOC7 }]; #IO_L10P_T1_D14_14 Sch=ja[2]
-set_property -dict { PACKAGE_PIN AB20  IOSTANDARD LVCMOS33 } [get_ports { IOC8 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3]
-set_property -dict { PACKAGE_PIN AB18  IOSTANDARD LVCMOS33 } [get_ports { IOC9 }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4]
-set_property -dict { PACKAGE_PIN Y21   IOSTANDARD LVCMOS33 } [get_ports { IOC10 }]; #IO_L9P_T1_DQS_14 Sch=ja[7]
-set_property -dict { PACKAGE_PIN AA21  IOSTANDARD LVCMOS33 } [get_ports { IOC11 }]; #IO_L8N_T1_D12_14 Sch=ja[8]
-set_property -dict { PACKAGE_PIN AA20  IOSTANDARD LVCMOS33 } [get_ports { IOR0 }]; #IO_L8P_T1_D11_14 Sch=ja[9]
-set_property -dict { PACKAGE_PIN AA18  IOSTANDARD LVCMOS33 } [get_ports { IOR1 }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10]
+set_property -dict { PACKAGE_PIN AB22  IOSTANDARD LVCMOS33 } [get_ports { IOC2 }]; #IO_L10N_T1_D15_14 Sch=ja[1]
+set_property -dict { PACKAGE_PIN AB21  IOSTANDARD LVCMOS33 } [get_ports { IOC3 }]; #IO_L10P_T1_D14_14 Sch=ja[2]
+set_property -dict { PACKAGE_PIN AB20  IOSTANDARD LVCMOS33 } [get_ports { IOC4 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3]
+set_property -dict { PACKAGE_PIN AB18  IOSTANDARD LVCMOS33 } [get_ports { IOC5 }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4]
+set_property -dict { PACKAGE_PIN Y21   IOSTANDARD LVCMOS33 } [get_ports { IOC6 }]; #IO_L9P_T1_DQS_14 Sch=ja[7]
+set_property -dict { PACKAGE_PIN AA21  IOSTANDARD LVCMOS33 } [get_ports { IOC7 }]; #IO_L8N_T1_D12_14 Sch=ja[8]
+set_property -dict { PACKAGE_PIN AA20  IOSTANDARD LVCMOS33 } [get_ports { IOC8 }]; #IO_L8P_T1_D11_14 Sch=ja[9]
+set_property -dict { PACKAGE_PIN AA18  IOSTANDARD LVCMOS33 } [get_ports { IOC9 }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10]
 
 
 ## Pmod header JB
@@ -176,8 +176,8 @@
 
 
 ## UART
-set_property -dict { PACKAGE_PIN AA19  IOSTANDARD LVCMOS33 } [get_ports { IOR3 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=uart_rx_out
-set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33 } [get_ports { IOR2 }]; #IO_L14P_T2_SRCC_14 Sch=uart_tx_in
+set_property -dict { PACKAGE_PIN AA19  IOSTANDARD LVCMOS33 } [get_ports { IOC11 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=uart_rx_out
+set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33 } [get_ports { IOC10 }]; #IO_L14P_T2_SRCC_14 Sch=uart_tx_in
 
 
 ## Ethernet
@@ -210,10 +210,10 @@
 set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_D0 }]; #IO_L19P_T3_A10_D26_14 Sch=prog_d1/sdi
 set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_D1 }]; #IO_L22P_T3_A05_D21_14 Sch=prog_d2/sdo
 set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_CS_L }]; #IO_L18P_T2_A12_D28_14 Sch=prog_d3/ss
-set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { IOC0 }]; #IO_L24N_T3_A00_D16_14 Sch=prog_d[4]
+set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { IOB9 }]; #IO_L24N_T3_A00_D16_14 Sch=prog_d[4]
 set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { IO_JSRST_N }]; #IO_L24P_T3_A01_D17_14 Sch=prog_d[5]
-set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB10 }]; #IO_L20P_T3_A08_D24_14 Sch=prog_d[6]
-set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB11 }]; #IO_L23N_T3_A02_D18_14 Sch=prog_d[7]
+set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB7 }]; #IO_L20P_T3_A08_D24_14 Sch=prog_d[6]
+set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB8 }]; #IO_L23N_T3_A02_D18_14 Sch=prog_d[7]
 #set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { prog_oen }]; #IO_L16P_T2_CSI_B_14 Sch=prog_oen
 #set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports { prog_rdn }]; #IO_L5P_T0_D06_14 Sch=prog_rdn
 #set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { prog_rxen }]; #IO_L21P_T3_DQS_14 Sch=prog_rxen
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 4fa11b6..d45c61b 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -1033,7 +1033,6 @@
     //
     // Optionally, each pad can also have a 'desc' field for further description.
     pads: [
-      // TODO: this needs to be updated to the latest ASIC pinout.
       // Dedicated
       { name: 'POR_N'           , type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'System reset'},
       { name: 'SPI_HOST_D0'     , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
@@ -1058,50 +1057,54 @@
       { name: 'FLASH_TEST_MODE3', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'},
       { name: 'FLASH_TEST_VOLT' , type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test voltage input'},
       // IOA
-      { name: 'IOA0'            , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOA1'            , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOA2'            , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOA3'            , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOA4'            , type: 'BidirOd' , bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOA5'            , type: 'BidirOd' , bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA0'            , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA1'            , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA2'            , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA3'            , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA4'            , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA5'            , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA6'            , type: 'BidirOd',  bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA7'            , type: 'BidirOd',  bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA8'            , type: 'BidirOd',  bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
       // IOB
-      { name: 'IOB0'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB1'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB2'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB3'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB4'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB5'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB6'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB7'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB8'            , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB0'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB1'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB2'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB3'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB4'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB5'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB6'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB7'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB8'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
       { name: 'IOB9'            , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB10'           , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB11'           , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB10'           , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB11'           , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB12'           , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
       // IOC
-      { name: 'IOC0'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC1'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC2'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC3'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC4'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC5'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC6'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC7'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC8'            , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC9'            , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC0'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC1'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC2'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC3'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC4'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC5'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC6'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC7'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC8'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC9'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
       { name: 'IOC10'           , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
       { name: 'IOC11'           , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC12'           , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
       // IOR
-      { name: 'IOR0'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR1'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR2'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR3'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR4'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR5'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR6'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR7'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR8'            , type: 'BidirOd' , bank: 'VCC' , connection: 'direct', desc: 'Dedicated systrst_ctrl output pad'},
-      // TODO: this needs to become a direct IO as well
-      { name: 'IOR9'            , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR0'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR1'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR2'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR3'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR4'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR5'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR6'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR7'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR8'            , type: 'BidirOd' , bank: 'VCC' , connection: 'direct', desc: 'Dedicated sysrst_ctrl output (ec_rst_l)'},
+      { name: 'IOR9'            , type: 'BidirOd' , bank: 'VCC' , connection: 'direct', desc: 'Dedicated sysrst_ctrl output (pwrb_out)'},
       { name: 'IOR10'           , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
       { name: 'IOR11'           , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
       { name: 'IOR12'           , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
@@ -1183,7 +1186,7 @@
       { instance: "sysrst_ctrl_aon", port: 'key0_out',     connection: 'muxed' , pad: ''             , desc: ''},
       { instance: "sysrst_ctrl_aon", port: 'key1_out',     connection: 'muxed' , pad: ''             , desc: ''},
       { instance: "sysrst_ctrl_aon", port: 'key2_out',     connection: 'muxed' , pad: ''             , desc: ''},
-      { instance: "sysrst_ctrl_aon", port: 'pwrb_out',     connection: 'muxed' , pad: ''             , desc: ''},
+      { instance: "sysrst_ctrl_aon", port: 'pwrb_out',     connection: 'direct', pad: 'IOR9'         , desc: ''},
     ],
 
     // Number of wakeup detectors to instantiate, and bitwidth for the wakeup counters.
@@ -1244,17 +1247,16 @@
         // Each entry may have an optional 'desc' key for further description.
         special_signals: [
           // Straps
-          { name: 'tap0',   pad: 'IOC8',         desc: 'TAP strap signal.'  },
-          { name: 'tap1',   pad: 'IOC5',         desc: 'TAP strap signal.'  },
-          { name: 'dft0',   pad: 'IOC3',         desc: 'DFT strap signal.'  },
-          { name: 'dft1',   pad: 'IOC4',         desc: 'DFT strap signal.'  },
+          { name: 'tap0',   pad: 'IOC8', desc: 'TAP strap signal.'  },
+          { name: 'tap1',   pad: 'IOC5', desc: 'TAP strap signal.'  },
+          { name: 'dft0',   pad: 'IOC3', desc: 'DFT strap signal.'  },
+          { name: 'dft1',   pad: 'IOC4', desc: 'DFT strap signal.'  },
           // JTAG
-          // TODO: this needs to be updated to the latest ASIC pinout.
-          { name: 'tck',    pad: 'SPI_DEV_CLK' , desc: 'JTAG tck signal, overlaid on SPI_DEV.'   },
-          { name: 'tms',    pad: 'SPI_DEV_CS_L', desc: 'JTAG tms signal, overlaid on SPI_DEV.'   },
-          { name: 'trst_n', pad: 'IOC0'        , desc: 'JTAG trst_n signal, maps to MIO Pad 18.' },
-          { name: 'tdi',    pad: 'SPI_DEV_D0'  , desc: 'JTAG tdi signal, overlaid on SPI_DEV.'   },
-          { name: 'tdo',    pad: 'SPI_DEV_D1'  , desc: 'JTAG tdo signal, overlaid on SPI_DEV.'   },
+          { name: 'tck',    pad: 'IOR3', desc: 'JTAG tck signal.'    },
+          { name: 'tms',    pad: 'IOR0', desc: 'JTAG tms signal.'    },
+          { name: 'trst_n', pad: 'IOR4', desc: 'JTAG trst_n signal.' },
+          { name: 'tdi',    pad: 'IOR2', desc: 'JTAG tdi signal.'    },
+          { name: 'tdo',    pad: 'IOR1', desc: 'JTAG tdo signal.'    },
         ],
       }
     },
@@ -1263,13 +1265,14 @@
       pinout: {
         remove_pads: [
           'CC1', 'CC2',
-          'IOC1', 'IOC2','IOC3','IOC4','IOC5',
           'SPI_DEV_D2', 'SPI_DEV_D3'
           'SPI_HOST_CLK', 'SPI_HOST_CS_L',
           'SPI_HOST_D0', 'SPI_HOST_D1', 'SPI_HOST_D2', 'SPI_HOST_D3',
           'FLASH_TEST_VOLT',
           'FLASH_TEST_MODE0', 'FLASH_TEST_MODE1', 'FLASH_TEST_MODE2', 'FLASH_TEST_MODE3',
-          'IOR4', 'IOR5', 'IOR6', 'IOR7', 'IOR8', 'IOR9', 'IOR10', 'IOR11', 'IOR12', 'IOR13'
+          'IOB10', 'IOB11', 'IOB12',
+          'IOC0', 'IOC1', 'IOC12',
+          'IOR0', 'IOR1', 'IOR2', 'IOR3', 'IOR4', 'IOR5', 'IOR6', 'IOR7', 'IOR8', 'IOR9', 'IOR10', 'IOR11', 'IOR12', 'IOR13'
         ],
 
         add_pads: [
@@ -1291,17 +1294,17 @@
         ],
       },
 
-      pinmux: {
+pinmux: {
         special_signals: [
           // Straps
-          { name: 'tap0',   pad: 'IOC2' ,        desc: 'TAP strap signal, maps to a stubbed-off MIO.'  },
-          { name: 'tap1',   pad: 'IOB10',        desc: 'TAP strap signal, maps to MIO pad 16.'         },
-          { name: 'dft0',   pad: 'IOC3' ,        desc: 'DFT strap signal, maps to a stubbed-off MIO.'  },
-          { name: 'dft1',   pad: 'IOC4' ,        desc: 'DFT strap signal, maps to a stubbed-off MIO.'  },
+          { name: 'tap0',   pad: 'IOC0' ,        desc: 'TAP strap signal, maps to a stubbed-off MIO.'  },
+          { name: 'tap1',   pad: 'IOB7',         desc: 'TAP strap signal, maps to MIO pad 16.'         },
+          { name: 'dft0',   pad: 'IOC1' ,        desc: 'DFT strap signal, maps to a stubbed-off MIO.'  },
+          { name: 'dft1',   pad: 'IOC12',        desc: 'DFT strap signal, maps to a stubbed-off MIO.'  },
           // JTAG
           { name: 'tck',    pad: 'SPI_DEV_CLK' , desc: 'JTAG tck signal, overlaid on SPI_DEV.'   },
           { name: 'tms',    pad: 'SPI_DEV_CS_L', desc: 'JTAG tms signal, overlaid on SPI_DEV.'   },
-          { name: 'trst_n', pad: 'IOC0'        , desc: 'JTAG trst_n signal, maps to MIO pad 18.' },
+          { name: 'trst_n', pad: 'IOB9'        , desc: 'JTAG trst_n signal, maps to MIO pad 18.' },
           { name: 'tdi',    pad: 'SPI_DEV_D0'  , desc: 'JTAG tdi signal, overlaid on SPI_DEV.'   },
           { name: 'tdo',    pad: 'SPI_DEV_D1'  , desc: 'JTAG tdo signal, overlaid on SPI_DEV.'   },
         ],
diff --git a/hw/top_earlgrey/dv/env/chip_env.sv b/hw/top_earlgrey/dv/env/chip_env.sv
index f621c20..8764550 100644
--- a/hw/top_earlgrey/dv/env/chip_env.sv
+++ b/hw/top_earlgrey/dv/env/chip_env.sv
@@ -29,18 +29,19 @@
       `uvm_fatal(`gfn, "failed to get gpio_vif from uvm_config_db")
     end
 
-    if (!uvm_config_db#(virtual pins_if#(1))::get(this, "", "srst_n_vif", cfg.srst_n_vif)) begin
-      `uvm_fatal(`gfn, "failed to get srst_n_vif from uvm_config_db")
+    if (!uvm_config_db#(virtual pins_if#(2))::get(this, "", "tap_straps_vif",
+        cfg.tap_straps_vif)) begin
+      `uvm_fatal(`gfn, "failed to get tap_straps_vif from uvm_config_db")
     end
 
-    if (!uvm_config_db#(virtual pins_if#(1))::get(this, "", "jtag_spi_n_vif",
-        cfg.jtag_spi_n_vif)) begin
-      `uvm_fatal(`gfn, "failed to get jtag_spi_n_vif from uvm_config_db")
+    if (!uvm_config_db#(virtual pins_if#(2))::get(this, "", "dft_straps_vif",
+        cfg.dft_straps_vif)) begin
+      `uvm_fatal(`gfn, "failed to get dft_straps_vif from uvm_config_db")
     end
 
-    if (!uvm_config_db#(virtual pins_if#(1))::get(this, "", "bootstrap_vif",
-        cfg.bootstrap_vif)) begin
-      `uvm_fatal(`gfn, "failed to get bootstrap_vif from uvm_config_db")
+    if (!uvm_config_db#(virtual pins_if#(3))::get(this, "", "sw_straps_vif",
+        cfg.sw_straps_vif)) begin
+      `uvm_fatal(`gfn, "failed to get sw_straps_vif from uvm_config_db")
     end
 
     if (!uvm_config_db#(virtual pins_if#(1))::get(this, "", "rst_n_mon_vif",
diff --git a/hw/top_earlgrey/dv/env/chip_env_cfg.sv b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
index 0fde328..3fa1351 100644
--- a/hw/top_earlgrey/dv/env/chip_env_cfg.sv
+++ b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
@@ -20,9 +20,9 @@
   // chip top interfaces
   virtual clk_rst_if  usb_clk_rst_vif;
   gpio_vif            gpio_vif;
-  virtual pins_if#(1) srst_n_vif;
-  virtual pins_if#(1) jtag_spi_n_vif;
-  virtual pins_if#(1) bootstrap_vif;
+  virtual pins_if#(2) tap_straps_vif;
+  virtual pins_if#(2) dft_straps_vif;
+  virtual pins_if#(3) sw_straps_vif;
   virtual pins_if#(1) rst_n_mon_vif;
 
   // mem backdoors
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv
index f9a54d7..28da07c 100644
--- a/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv
+++ b/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv
@@ -70,9 +70,9 @@
 
     // Drive strap signals at the start.
     if (do_strap_pins_init) begin
-      cfg.srst_n_vif.drive(1'b1);
-      cfg.jtag_spi_n_vif.drive(1'b1); // Select JTAG.
-      cfg.bootstrap_vif.drive(cfg.use_spi_load_bootstrap);
+      cfg.tap_straps_vif.drive(2'b10); // Select JTAG.
+      cfg.dft_straps_vif.drive(2'b00);
+      cfg.sw_straps_vif.drive({2'b00, cfg.use_spi_load_bootstrap});
     end
 
     // Now safe to do DUT init.
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_stub_cpu_base_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_stub_cpu_base_vseq.sv
index cf08374..73b7e5d 100644
--- a/hw/top_earlgrey/dv/env/seq_lib/chip_stub_cpu_base_vseq.sv
+++ b/hw/top_earlgrey/dv/env/seq_lib/chip_stub_cpu_base_vseq.sv
@@ -12,8 +12,8 @@
 
   virtual task pre_start();
     super.pre_start();
-    // Select SPI interface.
-    cfg.jtag_spi_n_vif.drive(1'b0);
+    // Deselect JTAG interface.
+    cfg.tap_straps_vif.drive(2'b00);
     enable_asserts_in_hw_reset_rand_wr = 0;
 
     // In top-level uart RX pin may be selected in pinmux. CSR tests may randomly enable line
@@ -41,9 +41,9 @@
 
   virtual task dut_init(string reset_kind = "HARD");
     // make sure jtag rst triggers
-    cfg.jtag_spi_n_vif.drive(1'b1);
+    cfg.tap_straps_vif.drive(2'b10);
     super.dut_init(reset_kind);
-    cfg.jtag_spi_n_vif.drive(1'b0);
+    cfg.tap_straps_vif.drive(2'b00);
   endtask
 
 endclass
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv
index 8db9a60..25ba066 100644
--- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv
+++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv
@@ -96,7 +96,6 @@
     // TODO, in some cases though, we might use UART logger instead of SW logger - need to keep that
     // in mind
     wait(cfg.sw_logger_vif.printed_log == "HW initialisation completed, waiting for SPI input...");
-    cfg.jtag_spi_n_vif.drive(0); // Select SPI
 
     // for the first frame of data, sdo from chip is unknown, ignore checking that
     cfg.m_spi_agent_cfg.en_monitor_checks = 0;
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_spi_tx_rx_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_spi_tx_rx_vseq.sv
index 21d3da3..dba543a 100644
--- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_spi_tx_rx_vseq.sv
+++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_spi_tx_rx_vseq.sv
@@ -31,7 +31,6 @@
   virtual task body();
     bit [7:0] spi_device_tx_data[$];
     super.body();
-    cfg.jtag_spi_n_vif.drive(1'b0); // Select SPI_DEVICE.
 
     // Wait SPI_DEVICE filled TX FIFO, otherwise SDO will be X
     cfg.clk_rst_vif.wait_clks(100);
diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv
index 146177a..8030a5d3 100644
--- a/hw/top_earlgrey/dv/tb/tb.sv
+++ b/hw/top_earlgrey/dv/tb/tb.sv
@@ -34,8 +34,9 @@
   wire spi_device_sdi_i;
 
   wire srst_n;
-  wire jtag_spi_n;
-  wire bootstrap;
+  wire [1:0] tap_straps;
+  wire [1:0] dft_straps;
+  wire [2:0] sw_straps;
   wire [7:0] io_dps;
 
   wire usb_dp0, usb_dn0, usb_sense0, usb_dppullup0, usb_dnpullup0;
@@ -57,8 +58,9 @@
   alert_esc_if alert_if[NUM_ALERTS](.clk(alert_handler_clk), .rst_n(rst_n));
   pins_if #(NUM_GPIOS) gpio_if(.pins(gpio_pins));
   pins_if #(1) srst_n_if(.pins(srst_n));
-  pins_if #(1) jtag_spi_n_if(.pins(jtag_spi_n));
-  pins_if #(1) bootstrap_if(.pins(bootstrap));
+  pins_if #(2) tap_straps_if(.pins(tap_straps));
+  pins_if #(2) dft_straps_if(.pins(dft_straps));
+  pins_if #(3) sw_straps_if(.pins(sw_straps));
   pins_if #(1) rst_n_mon_if(.pins(cpu_rst_n));
   spi_if spi_if(.rst_n);
   tl_if cpu_d_tl_if(.clk(cpu_clk), .rst_n(cpu_rst_n));
@@ -88,103 +90,100 @@
   // We will need to feed this in via a muxed pin, once that function implemented.
 
   chip_earlgrey_asic dut (
-    // Clock and Reset
+    // Clock and Reset (VCC domain)
     .POR_N(rst_n),
-    // Bank A (VIOA domain)
+    // Dedicated SPI Host (VIOA domain)
     .SPI_HOST_D0(spi_host_tie_off[0]),
     .SPI_HOST_D1(spi_host_tie_off[1]),
     .SPI_HOST_D2(spi_host_tie_off[2]),
     .SPI_HOST_D3(spi_host_tie_off[3]),
     .SPI_HOST_CLK(spi_host_tie_off[4]),
     .SPI_HOST_CS_L(spi_host_tie_off[5]),
-    .SPI_DEV_D0(io_dps[1]),
-    .SPI_DEV_D1(io_dps[2]),
+    // Dedicated SPI Device (VIOA domain)
+    .SPI_DEV_D0(spi_device_sdi_i),
+    .SPI_DEV_D1(spi_device_sdo_o),
     .SPI_DEV_D2(spi_dev_tie_off[0]),
     .SPI_DEV_D3(spi_dev_tie_off[1]),
-    .SPI_DEV_CLK(io_dps[0]),
-    .SPI_DEV_CS_L(io_dps[3]),
+    .SPI_DEV_CLK(spi_device_sck),
+    .SPI_DEV_CS_L(spi_device_csb),
+    // Bank A (VIOA domain)
     .IOA0(gpio_pins[0]),   // MIO 0
     .IOA1(gpio_pins[1]),   // MIO 1
     .IOA2(gpio_pins[2]),   // MIO 2
     .IOA3(gpio_pins[3]),   // MIO 3
     .IOA4(gpio_pins[4]),   // MIO 4
     .IOA5(gpio_pins[5]),   // MIO 5
+    .IOA6(gpio_pins[6]),   // MIO 6
+    .IOA7(gpio_pins[7]),   // MIO 7
+    .IOA8(gpio_pins[8]),   // MIO 8
     // Bank B (VIOB domain)
-    .IOB0(gpio_pins[6]),   // MIO 6
-    .IOB1(gpio_pins[7]),   // MIO 7
-    .IOB2(gpio_pins[8]),   // MIO 8
-    .IOB3(gpio_pins[9]),   // MIO 9
-    .IOB4(gpio_pins[10]),  // MIO 10
-    .IOB5(gpio_pins[11]),  // MIO 11
-    .IOB6(gpio_pins[12]),  // MIO 12
-    .IOB7(gpio_pins[13]),  // MIO 13
-    .IOB8(gpio_pins[14]),  // MIO 14
-    .IOB9(gpio_pins[15]),  // MIO 15
-    .IOB10(io_dps[6]),     // MIO 16
-    .IOB11(io_dps[7]),     // MIO 17
+    .IOB0(gpio_pins[9]),   // MIO 9
+    .IOB1(gpio_pins[10]),  // MIO 10
+    .IOB2(gpio_pins[11]),  // MIO 11
+    .IOB3(gpio_pins[12]),  // MIO 12
+    .IOB4(gpio_pins[13]),  // MIO 13
+    .IOB5(gpio_pins[14]),  // MIO 14
+    .IOB6(gpio_pins[15]),  // MIO 15
+    .IOB7(tie_off[0]),     // MIO 16
+    .IOB8(tie_off[1]),     // MIO 17
+    .IOB9(tie_off[2]),     // MIO 18
+    .IOB10(tie_off[3]),    // MIO 19
+    .IOB11(tie_off[4]),    // MIO 20
+    .IOB12(tie_off[5]),    // MIO 21
     // Bank C (VCC domain)
-    .IOC0(io_dps[4]),      // MIO 18
-    .IOC1(io_dps[5]),      // MIO 19
-    .IOC2(tie_off[0]),     // MIO 20
-    .IOC3(tie_off[1]),     // MIO 21
-    .IOC4(tie_off[2]),     // MIO 22
-    .IOC5(jtag_spi_n),     // MIO 23 -- TAP_STRAP_SEL1
-    .IOC6(tie_off[4]),     // MIO 24
-    .IOC7(tie_off[5]),     // MIO 25
-    .IOC8(tie_off[6]),     // MIO 26 -- TAP_STRAP_SEL0
-    .IOC9(tie_off[7]),     // MIO 27
-    .IOC10(tie_off[8]),    // MIO 28
-    .IOC11(tie_off[9]),    // MIO 29
+    .IOC0(sw_straps[0]),   // MIO 22
+    .IOC1(sw_straps[1]),   // MIO 23
+    .IOC2(sw_straps[2]),   // MIO 24
+    .IOC3(dft_straps[0]),  // MIO 25
+    .IOC4(dft_straps[1]),  // MIO 26
+    .IOC5(tap_straps[1]),  // MIO 27
+    .IOC6(tie_off[6]),     // MIO 28
+    .IOC7(tie_off[7]),     // MIO 29
+    .IOC8(tap_straps[0]),  // MIO 30
+    .IOC9(tie_off[8]),     // MIO 31
+    .IOC10(uart_rx),       // MIO 32
+    .IOC11(uart_tx),       // MIO 33
+    .IOC12(tie_off[9]),    // MIO 34
     // Bank R (VCC domain)
-    .IOR0(tie_off[10]),    // MIO 30
-    .IOR1(tie_off[11]),    // MIO 31
-    .IOR2(uart_rx),        // MIO 32
-    .IOR3(uart_tx),        // MIO 33
-    .IOR4(tie_off[12]),    // MIO 34
-    .IOR5(tie_off[13]),    // MIO 35
-    .IOR6(tie_off[14]),    // MIO 36
-    .IOR7(tie_off[15]),    // MIO 37
-    .IOR8(tie_off[16]),    // MIO 38
-    .IOR9(tie_off[17]),    // MIO 39
-    .IOR10(tie_off[18]),   // MIO 40
-    .IOR11(tie_off[19]),   // MIO 41
-    .IOR12(tie_off[20]),   // MIO 42
-    .IOR13(tie_off[21]),   // MIO 43
+    .IOR0(jtag_tms),       // MIO 35
+    .IOR1(jtag_tdo),       // MIO 36
+    .IOR2(jtag_tdi),       // MIO 37
+    .IOR3(jtag_tck),       // MIO 38
+    .IOR4(jtag_trst_n),    // MIO 39
+    .IOR5(tie_off[10]),    // MIO 40
+    .IOR6(tie_off[11]),    // MIO 41
+    .IOR7(tie_off[12]),    // MIO 42
+    .IOR8(tie_off[13]),    // MIO 43
+    .IOR9(tie_off[14]),    // MIO 44
+    .IOR10(tie_off[15]),   // MIO 45
+    .IOR11(tie_off[16]),   // MIO 46
+    .IOR12(tie_off[17]),   // MIO 47
+    .IOR13(tie_off[18]),   // MIO 48
     // DCD (VCC domain)
-    .CC1(tie_off[22]),
-    .CC2(tie_off[23]),
+    .CC1(tie_off[19]),
+    .CC2(tie_off[20]),
     // USB (VCC domain)
     .USB_P(usb_dp0),
     .USB_N(usb_dn0),
     // FLASH
-    .FLASH_TEST_MODE0(tie_off[24]),
-    .FLASH_TEST_MODE1(tie_off[25]),
-    .FLASH_TEST_MODE2(tie_off[26]),
-    .FLASH_TEST_MODE3(tie_off[27]),
-    .FLASH_TEST_VOLT(tie_off[28])
+    .FLASH_TEST_MODE0(tie_off[21]),
+    .FLASH_TEST_MODE1(tie_off[22]),
+    .FLASH_TEST_MODE2(tie_off[23]),
+    .FLASH_TEST_MODE3(tie_off[24]),
+    .FLASH_TEST_VOLT(tie_off[25])
   );
 
   // connect signals
-  assign io_dps[0]  = jtag_spi_n ? jtag_tck : spi_device_sck;
-  assign io_dps[1]  = jtag_spi_n ? jtag_tdi : spi_device_sdi_i;
-  assign io_dps[3]  = jtag_spi_n ? jtag_tms : spi_device_csb;
-  assign (weak0, weak1) io_dps[4] = 1'b0;
-  assign io_dps[5]  = srst_n;
-  assign io_dps[6]  = jtag_spi_n;
-  assign io_dps[7]  = bootstrap;
-  assign spi_device_sdo_o  = jtag_spi_n ? 1'b0 : io_dps[2];
-  assign jtag_tdo          = jtag_spi_n ? io_dps[2] : 1'b0;
-
   assign jtag_tck         = jtag_if.tck;
   assign jtag_tms         = jtag_if.tms;
   assign jtag_trst_n      = jtag_if.trst_n;
   assign jtag_tdi         = jtag_if.tdi;
   assign jtag_if.tdo      = jtag_tdo;
 
-  assign spi_device_sck     = spi_if.sck;
-  assign spi_device_csb     = spi_if.csb;
-  assign spi_device_sdi_i   = spi_if.sio[0];
-  assign spi_if.sio[1]      = spi_device_sdo_o;
+  assign spi_device_sck   = spi_if.sck;
+  assign spi_device_csb   = spi_if.csb;
+  assign spi_device_sdi_i = spi_if.sio[0];
+  assign spi_if.sio[1]    = spi_device_sdo_o;
 
   // TODO: Replace this weak pull to a known value with initialization
   // in the agent/interface.
@@ -265,12 +264,12 @@
     uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", cpu_d_tl_if);
 
     // Strap pins
-    uvm_config_db#(virtual pins_if #(1))::set(
-        null, "*.env", "srst_n_vif", srst_n_if);
-    uvm_config_db#(virtual pins_if #(1))::set(
-        null, "*.env", "jtag_spi_n_vif", jtag_spi_n_if);
-    uvm_config_db#(virtual pins_if #(1))::set(
-        null, "*.env", "bootstrap_vif", bootstrap_if);
+    uvm_config_db#(virtual pins_if #(2))::set(
+        null, "*.env", "tap_straps_vif", tap_straps_if);
+    uvm_config_db#(virtual pins_if #(2))::set(
+        null, "*.env", "dft_straps_vif", dft_straps_if);
+    uvm_config_db#(virtual pins_if #(3))::set(
+        null, "*.env", "sw_straps_vif", sw_straps_if);
     uvm_config_db#(virtual pins_if #(1))::set(
         null, "*.env", "rst_n_mon_vif", rst_n_mon_if);
 
diff --git a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
index 6a18197..aa44a9f 100644
--- a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
+++ b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
@@ -160,19 +160,19 @@
     { name: "NMioPeriphOut",
       desc: "Number of muxed peripheral outputs",
       type: "int",
-      default: "68",
+      default: "67",
       local: "true"
     },
     { name: "NMioPads",
       desc: "Number of muxed IO pads",
       type: "int",
-      default: "43",
+      default: "47",
       local: "true"
     },
     { name: "NDioPads",
       desc: "Number of dedicated IO pads",
       type: "int",
-      default: "22",
+      default: "23",
       local: "true"
     },
     { name: "NWkupDetect",
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
index 4aa945c..60947d4 100644
--- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
@@ -9,9 +9,9 @@
   // Param list
   parameter int AttrDw = 13;
   parameter int NMioPeriphIn = 65;
-  parameter int NMioPeriphOut = 68;
-  parameter int NMioPads = 43;
-  parameter int NDioPads = 22;
+  parameter int NMioPeriphOut = 67;
+  parameter int NMioPads = 47;
+  parameter int NDioPads = 23;
   parameter int NWkupDetect = 8;
   parameter int WkupCntWidth = 8;
 
@@ -117,16 +117,16 @@
 
   // Register -> HW type
   typedef struct packed {
-    pinmux_reg2hw_mio_periph_insel_mreg_t [64:0] mio_periph_insel; // [2036:1647]
-    pinmux_reg2hw_mio_outsel_mreg_t [42:0] mio_outsel; // [1646:1346]
-    pinmux_reg2hw_mio_pad_attr_mreg_t [42:0] mio_pad_attr; // [1345:744]
-    pinmux_reg2hw_dio_pad_attr_mreg_t [21:0] dio_pad_attr; // [743:436]
-    pinmux_reg2hw_mio_pad_sleep_status_mreg_t [42:0] mio_pad_sleep_status; // [435:393]
-    pinmux_reg2hw_mio_pad_sleep_en_mreg_t [42:0] mio_pad_sleep_en; // [392:350]
-    pinmux_reg2hw_mio_pad_sleep_mode_mreg_t [42:0] mio_pad_sleep_mode; // [349:264]
-    pinmux_reg2hw_dio_pad_sleep_status_mreg_t [21:0] dio_pad_sleep_status; // [263:242]
-    pinmux_reg2hw_dio_pad_sleep_en_mreg_t [21:0] dio_pad_sleep_en; // [241:220]
-    pinmux_reg2hw_dio_pad_sleep_mode_mreg_t [21:0] dio_pad_sleep_mode; // [219:176]
+    pinmux_reg2hw_mio_periph_insel_mreg_t [64:0] mio_periph_insel; // [2154:1765]
+    pinmux_reg2hw_mio_outsel_mreg_t [46:0] mio_outsel; // [1764:1436]
+    pinmux_reg2hw_mio_pad_attr_mreg_t [46:0] mio_pad_attr; // [1435:778]
+    pinmux_reg2hw_dio_pad_attr_mreg_t [22:0] dio_pad_attr; // [777:456]
+    pinmux_reg2hw_mio_pad_sleep_status_mreg_t [46:0] mio_pad_sleep_status; // [455:409]
+    pinmux_reg2hw_mio_pad_sleep_en_mreg_t [46:0] mio_pad_sleep_en; // [408:362]
+    pinmux_reg2hw_mio_pad_sleep_mode_mreg_t [46:0] mio_pad_sleep_mode; // [361:268]
+    pinmux_reg2hw_dio_pad_sleep_status_mreg_t [22:0] dio_pad_sleep_status; // [267:245]
+    pinmux_reg2hw_dio_pad_sleep_en_mreg_t [22:0] dio_pad_sleep_en; // [244:222]
+    pinmux_reg2hw_dio_pad_sleep_mode_mreg_t [22:0] dio_pad_sleep_mode; // [221:176]
     pinmux_reg2hw_wkup_detector_en_mreg_t [7:0] wkup_detector_en; // [175:168]
     pinmux_reg2hw_wkup_detector_mreg_t [7:0] wkup_detector; // [167:128]
     pinmux_reg2hw_wkup_detector_cnt_th_mreg_t [7:0] wkup_detector_cnt_th; // [127:64]
@@ -136,10 +136,10 @@
 
   // HW -> register type
   typedef struct packed {
-    pinmux_hw2reg_mio_pad_attr_mreg_t [42:0] mio_pad_attr; // [982:424]
-    pinmux_hw2reg_dio_pad_attr_mreg_t [21:0] dio_pad_attr; // [423:138]
-    pinmux_hw2reg_mio_pad_sleep_status_mreg_t [42:0] mio_pad_sleep_status; // [137:52]
-    pinmux_hw2reg_dio_pad_sleep_status_mreg_t [21:0] dio_pad_sleep_status; // [51:8]
+    pinmux_hw2reg_mio_pad_attr_mreg_t [46:0] mio_pad_attr; // [1057:447]
+    pinmux_hw2reg_dio_pad_attr_mreg_t [22:0] dio_pad_attr; // [446:148]
+    pinmux_hw2reg_mio_pad_sleep_status_mreg_t [46:0] mio_pad_sleep_status; // [147:54]
+    pinmux_hw2reg_dio_pad_sleep_status_mreg_t [22:0] dio_pad_sleep_status; // [53:8]
     pinmux_hw2reg_wkup_cause_mreg_t [7:0] wkup_cause; // [7:0]
   } pinmux_hw2reg_t;
 
@@ -317,418 +317,451 @@
   parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET = 12'h 2a8;
   parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET = 12'h 2ac;
   parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET = 12'h 2b0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 12'h 2b4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 12'h 2b8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 12'h 2bc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 12'h 2c0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 12'h 2c4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 12'h 2c8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 12'h 2cc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 12'h 2d0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 12'h 2d4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 12'h 2d8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 12'h 2dc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 12'h 2e0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 12'h 2e4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 12'h 2e8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 12'h 2ec;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 12'h 2f0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 12'h 2f4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 12'h 2f8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 12'h 2fc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 12'h 300;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 12'h 304;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 12'h 308;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 12'h 30c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 12'h 310;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 12'h 314;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 12'h 318;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 12'h 31c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 12'h 320;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 12'h 324;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 12'h 328;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 12'h 32c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 12'h 330;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_32_OFFSET = 12'h 334;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_33_OFFSET = 12'h 338;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_34_OFFSET = 12'h 33c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_35_OFFSET = 12'h 340;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_36_OFFSET = 12'h 344;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_37_OFFSET = 12'h 348;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_38_OFFSET = 12'h 34c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_39_OFFSET = 12'h 350;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_40_OFFSET = 12'h 354;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_41_OFFSET = 12'h 358;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_42_OFFSET = 12'h 35c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 360;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 364;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 368;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 36c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 370;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 374;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 378;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 37c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 380;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 384;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 388;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 38c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 390;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 394;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 398;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 39c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 3a0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 3a4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 3a8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 3ac;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 3b0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 3b4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 3b8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 3bc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 3c0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 3c4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 3c8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 3cc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 3d0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 3d4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 3d8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 3dc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 3e0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 3e4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 3e8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 3ec;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 3f0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 3f4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 3f8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 3fc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 400;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 404;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 408;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 12'h 40c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 12'h 410;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 12'h 414;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 12'h 418;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 12'h 41c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 12'h 420;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 12'h 424;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 12'h 428;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 12'h 42c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 12'h 430;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 12'h 434;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 12'h 438;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 12'h 43c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 12'h 440;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 12'h 444;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 12'h 448;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 12'h 44c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 12'h 450;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 12'h 454;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 12'h 458;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 12'h 45c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 12'h 460;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 12'h 464;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 12'h 468;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 12'h 46c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 12'h 470;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 12'h 474;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 12'h 478;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 12'h 47c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 12'h 480;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 12'h 484;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 12'h 488;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_32_OFFSET = 12'h 48c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_33_OFFSET = 12'h 490;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_34_OFFSET = 12'h 494;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_35_OFFSET = 12'h 498;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_36_OFFSET = 12'h 49c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_37_OFFSET = 12'h 4a0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_38_OFFSET = 12'h 4a4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_39_OFFSET = 12'h 4a8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_40_OFFSET = 12'h 4ac;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_41_OFFSET = 12'h 4b0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_42_OFFSET = 12'h 4b4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 4b8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 4bc;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 4c0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 4c4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 4c8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 4cc;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 4d0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 4d4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 4d8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 4dc;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 4e0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 4e4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 4e8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 4ec;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 4f0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 4f4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 4f8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 4fc;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 500;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 504;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 508;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 50c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 12'h 510;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 12'h 514;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 12'h 518;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 12'h 51c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 12'h 520;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 12'h 524;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 12'h 528;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 12'h 52c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 12'h 530;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 12'h 534;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 12'h 538;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 12'h 53c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 12'h 540;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 12'h 544;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 12'h 548;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 12'h 54c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_16_OFFSET = 12'h 550;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_17_OFFSET = 12'h 554;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_18_OFFSET = 12'h 558;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_19_OFFSET = 12'h 55c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_20_OFFSET = 12'h 560;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_21_OFFSET = 12'h 564;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 568;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 56c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 570;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 574;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 578;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 57c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 580;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 584;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 588;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 58c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 590;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 594;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 598;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 59c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 5a0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 5a4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 5a8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 5ac;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 5b0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 5b4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 5b8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 5bc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 5c0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 5c4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 5c8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 5cc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 5d0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 5d4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 5d8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 5dc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 5e0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 5e4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 5e8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 5ec;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 5f0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 5f4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 5f8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 5fc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 600;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 604;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 608;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 60c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 610;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 614;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 618;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 12'h 61c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 12'h 620;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 12'h 624;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 12'h 628;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 12'h 62c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 12'h 630;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 12'h 634;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 12'h 638;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 12'h 63c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 12'h 640;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 12'h 644;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 12'h 648;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 12'h 64c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 12'h 650;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 12'h 654;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 12'h 658;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 12'h 65c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 12'h 660;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 12'h 664;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 12'h 668;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 12'h 66c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 12'h 670;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 12'h 674;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 12'h 678;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 12'h 67c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 12'h 680;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 12'h 684;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 12'h 688;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 12'h 68c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 12'h 690;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 12'h 694;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 12'h 698;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET = 12'h 69c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET = 12'h 6a0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET = 12'h 6a4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET = 12'h 6a8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET = 12'h 6ac;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET = 12'h 6b0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET = 12'h 6b4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET = 12'h 6b8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET = 12'h 6bc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET = 12'h 6c0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET = 12'h 6c4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 6c8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 6cc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 6d0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 6d4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 6d8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 6dc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 6e0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 6e4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 6e8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 6ec;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 6f0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 6f4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 6f8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 6fc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 700;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 704;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 708;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 70c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 710;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 714;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 718;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 71c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 720;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 724;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 12'h 728;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 12'h 72c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 12'h 730;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 12'h 734;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 12'h 738;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 12'h 73c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 12'h 740;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 12'h 744;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET = 12'h 748;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET = 12'h 74c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET = 12'h 750;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET = 12'h 754;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET = 12'h 758;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET = 12'h 75c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET = 12'h 760;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET = 12'h 764;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET = 12'h 768;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET = 12'h 76c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET = 12'h 770;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 12'h 774;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 778;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 77c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 780;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 784;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 788;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 78c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 790;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 794;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 798;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 79c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 7a0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 7a4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 7a8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 7ac;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 7b0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 7b4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 7b8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 7bc;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 7c0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 7c4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 7c8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 7cc;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 12'h 7d0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 12'h 7d4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 12'h 7d8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 12'h 7dc;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 12'h 7e0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 12'h 7e4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 12'h 7e8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 12'h 7ec;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 12'h 7f0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 12'h 7f4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 12'h 7f8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 12'h 7fc;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 12'h 800;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 12'h 804;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 12'h 808;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 12'h 80c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET = 12'h 810;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET = 12'h 814;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET = 12'h 818;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET = 12'h 81c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET = 12'h 820;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET = 12'h 824;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 828;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 82c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 830;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 834;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 838;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 83c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 840;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 844;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 848;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 84c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 850;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 854;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 858;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 85c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 860;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 864;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 868;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 86c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 870;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 874;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 878;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 87c;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 12'h 880;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 12'h 884;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 12'h 888;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 12'h 88c;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 12'h 890;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 12'h 894;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 12'h 898;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 12'h 89c;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 12'h 8a0;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 12'h 8a4;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 12'h 8a8;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 12'h 8ac;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 12'h 8b0;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 12'h 8b4;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 12'h 8b8;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 12'h 8bc;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 12'h 8c0;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 12'h 8c4;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 12'h 8c8;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 12'h 8cc;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 12'h 8d0;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 12'h 8d4;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 12'h 8d8;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 12'h 8dc;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 12'h 8e0;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 12'h 8e4;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 12'h 8e8;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 12'h 8ec;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 12'h 8f0;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 12'h 8f4;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 12'h 8f8;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 12'h 8fc;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 12'h 900;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 12'h 904;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 12'h 908;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 12'h 90c;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 12'h 910;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 12'h 914;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 12'h 918;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 12'h 91c;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 12'h 920;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET = 12'h 2b4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET = 12'h 2b8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET = 12'h 2bc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET = 12'h 2c0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 12'h 2c4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 12'h 2c8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 12'h 2cc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 12'h 2d0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 12'h 2d4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 12'h 2d8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 12'h 2dc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 12'h 2e0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 12'h 2e4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 12'h 2e8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 12'h 2ec;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 12'h 2f0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 12'h 2f4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 12'h 2f8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 12'h 2fc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 12'h 300;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 12'h 304;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 12'h 308;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 12'h 30c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 12'h 310;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 12'h 314;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 12'h 318;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 12'h 31c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 12'h 320;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 12'h 324;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 12'h 328;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 12'h 32c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 12'h 330;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 12'h 334;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 12'h 338;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 12'h 33c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 12'h 340;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_32_OFFSET = 12'h 344;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_33_OFFSET = 12'h 348;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_34_OFFSET = 12'h 34c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_35_OFFSET = 12'h 350;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_36_OFFSET = 12'h 354;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_37_OFFSET = 12'h 358;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_38_OFFSET = 12'h 35c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_39_OFFSET = 12'h 360;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_40_OFFSET = 12'h 364;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_41_OFFSET = 12'h 368;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_42_OFFSET = 12'h 36c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_43_OFFSET = 12'h 370;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_44_OFFSET = 12'h 374;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_45_OFFSET = 12'h 378;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_46_OFFSET = 12'h 37c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 380;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 384;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 388;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 38c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 390;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 394;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 398;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 39c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 3a0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 3a4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 3a8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 3ac;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 3b0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 3b4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 3b8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 3bc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 3c0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 3c4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 3c8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 3cc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 3d0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 3d4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 3d8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 3dc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 3e0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 3e4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 3e8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 3ec;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 3f0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 3f4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 3f8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 3fc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 400;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 404;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 408;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 40c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 410;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 414;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 418;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 41c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 420;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 424;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 428;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET = 12'h 42c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET = 12'h 430;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET = 12'h 434;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET = 12'h 438;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 12'h 43c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 12'h 440;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 12'h 444;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 12'h 448;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 12'h 44c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 12'h 450;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 12'h 454;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 12'h 458;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 12'h 45c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 12'h 460;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 12'h 464;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 12'h 468;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 12'h 46c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 12'h 470;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 12'h 474;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 12'h 478;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 12'h 47c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 12'h 480;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 12'h 484;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 12'h 488;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 12'h 48c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 12'h 490;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 12'h 494;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 12'h 498;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 12'h 49c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 12'h 4a0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 12'h 4a4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 12'h 4a8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 12'h 4ac;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 12'h 4b0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 12'h 4b4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 12'h 4b8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_32_OFFSET = 12'h 4bc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_33_OFFSET = 12'h 4c0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_34_OFFSET = 12'h 4c4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_35_OFFSET = 12'h 4c8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_36_OFFSET = 12'h 4cc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_37_OFFSET = 12'h 4d0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_38_OFFSET = 12'h 4d4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_39_OFFSET = 12'h 4d8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_40_OFFSET = 12'h 4dc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_41_OFFSET = 12'h 4e0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_42_OFFSET = 12'h 4e4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_43_OFFSET = 12'h 4e8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_44_OFFSET = 12'h 4ec;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_45_OFFSET = 12'h 4f0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_46_OFFSET = 12'h 4f4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 4f8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 4fc;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 500;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 504;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 508;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 50c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 510;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 514;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 518;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 51c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 520;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 524;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 528;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 52c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 530;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 534;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 538;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 53c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 540;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 544;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 548;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 54c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 550;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 12'h 554;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 12'h 558;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 12'h 55c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 12'h 560;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 12'h 564;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 12'h 568;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 12'h 56c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 12'h 570;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 12'h 574;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 12'h 578;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 12'h 57c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 12'h 580;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 12'h 584;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 12'h 588;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 12'h 58c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 12'h 590;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_16_OFFSET = 12'h 594;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_17_OFFSET = 12'h 598;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_18_OFFSET = 12'h 59c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_19_OFFSET = 12'h 5a0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_20_OFFSET = 12'h 5a4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_21_OFFSET = 12'h 5a8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_22_OFFSET = 12'h 5ac;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 5b0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 5b4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 5b8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 5bc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 5c0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 5c4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 5c8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 5cc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 5d0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 5d4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 5d8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 5dc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 5e0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 5e4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 5e8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 5ec;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 5f0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 5f4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 5f8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 5fc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 600;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 604;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 608;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 60c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 610;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 614;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 618;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 61c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 620;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 624;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 628;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 62c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 630;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 634;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 638;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 63c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 640;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 644;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 648;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 64c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 650;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 654;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 658;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 65c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 660;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET = 12'h 664;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET = 12'h 668;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET = 12'h 66c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET = 12'h 670;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 12'h 674;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 12'h 678;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 12'h 67c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 12'h 680;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 12'h 684;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 12'h 688;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 12'h 68c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 12'h 690;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 12'h 694;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 12'h 698;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 12'h 69c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 12'h 6a0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 12'h 6a4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 12'h 6a8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 12'h 6ac;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 12'h 6b0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 12'h 6b4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 12'h 6b8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 12'h 6bc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 12'h 6c0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 12'h 6c4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 12'h 6c8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 12'h 6cc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 12'h 6d0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 12'h 6d4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 12'h 6d8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 12'h 6dc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 12'h 6e0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 12'h 6e4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 12'h 6e8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 12'h 6ec;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 12'h 6f0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET = 12'h 6f4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET = 12'h 6f8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET = 12'h 6fc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET = 12'h 700;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET = 12'h 704;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET = 12'h 708;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET = 12'h 70c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET = 12'h 710;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET = 12'h 714;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET = 12'h 718;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET = 12'h 71c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET = 12'h 720;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET = 12'h 724;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET = 12'h 728;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET = 12'h 72c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 730;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 734;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 738;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 73c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 740;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 744;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 748;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 74c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 750;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 754;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 758;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 75c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 760;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 764;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 768;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 76c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 770;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 774;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 778;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 77c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 780;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 784;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 788;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 78c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 12'h 790;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 12'h 794;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 12'h 798;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 12'h 79c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 12'h 7a0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 12'h 7a4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 12'h 7a8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 12'h 7ac;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET = 12'h 7b0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET = 12'h 7b4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET = 12'h 7b8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET = 12'h 7bc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET = 12'h 7c0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET = 12'h 7c4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET = 12'h 7c8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET = 12'h 7cc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET = 12'h 7d0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET = 12'h 7d4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET = 12'h 7d8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET = 12'h 7dc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET = 12'h 7e0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET = 12'h 7e4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET = 12'h 7e8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 12'h 7ec;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 7f0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 7f4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 7f8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 7fc;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 800;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 804;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 808;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 80c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 810;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 814;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 818;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 81c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 820;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 824;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 828;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 82c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 830;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 834;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 838;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 83c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 840;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 844;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 848;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 12'h 84c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 12'h 850;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 12'h 854;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 12'h 858;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 12'h 85c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 12'h 860;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 12'h 864;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 12'h 868;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 12'h 86c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 12'h 870;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 12'h 874;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 12'h 878;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 12'h 87c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 12'h 880;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 12'h 884;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 12'h 888;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET = 12'h 88c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET = 12'h 890;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET = 12'h 894;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET = 12'h 898;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET = 12'h 89c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET = 12'h 8a0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_22_OFFSET = 12'h 8a4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 8a8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 8ac;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 8b0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 8b4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 8b8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 8bc;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 8c0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 8c4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 8c8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 8cc;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 8d0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 8d4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 8d8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 8dc;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 8e0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 8e4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 8e8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 8ec;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 8f0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 8f4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 8f8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 8fc;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 900;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 12'h 904;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 12'h 908;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 12'h 90c;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 12'h 910;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 12'h 914;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 12'h 918;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 12'h 91c;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 12'h 920;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 12'h 924;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 12'h 928;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 12'h 92c;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 12'h 930;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 12'h 934;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 12'h 938;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 12'h 93c;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 12'h 940;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 12'h 944;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 12'h 948;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 12'h 94c;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 12'h 950;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 12'h 954;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 12'h 958;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 12'h 95c;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 12'h 960;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 12'h 964;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 12'h 968;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 12'h 96c;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 12'h 970;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 12'h 974;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 12'h 978;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 12'h 97c;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 12'h 980;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 12'h 984;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 12'h 988;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 12'h 98c;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 12'h 990;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 12'h 994;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 12'h 998;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 12'h 99c;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 12'h 9a0;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 12'h 9a4;
 
   // Reset values for hwext registers and their fields
   parameter logic [12:0] PINMUX_MIO_PAD_ATTR_0_RESVAL = 13'h 0;
@@ -817,6 +850,14 @@
   parameter logic [12:0] PINMUX_MIO_PAD_ATTR_41_ATTR_41_RESVAL = 13'h 0;
   parameter logic [12:0] PINMUX_MIO_PAD_ATTR_42_RESVAL = 13'h 0;
   parameter logic [12:0] PINMUX_MIO_PAD_ATTR_42_ATTR_42_RESVAL = 13'h 0;
+  parameter logic [12:0] PINMUX_MIO_PAD_ATTR_43_RESVAL = 13'h 0;
+  parameter logic [12:0] PINMUX_MIO_PAD_ATTR_43_ATTR_43_RESVAL = 13'h 0;
+  parameter logic [12:0] PINMUX_MIO_PAD_ATTR_44_RESVAL = 13'h 0;
+  parameter logic [12:0] PINMUX_MIO_PAD_ATTR_44_ATTR_44_RESVAL = 13'h 0;
+  parameter logic [12:0] PINMUX_MIO_PAD_ATTR_45_RESVAL = 13'h 0;
+  parameter logic [12:0] PINMUX_MIO_PAD_ATTR_45_ATTR_45_RESVAL = 13'h 0;
+  parameter logic [12:0] PINMUX_MIO_PAD_ATTR_46_RESVAL = 13'h 0;
+  parameter logic [12:0] PINMUX_MIO_PAD_ATTR_46_ATTR_46_RESVAL = 13'h 0;
   parameter logic [12:0] PINMUX_DIO_PAD_ATTR_0_RESVAL = 13'h 0;
   parameter logic [12:0] PINMUX_DIO_PAD_ATTR_0_ATTR_0_RESVAL = 13'h 0;
   parameter logic [12:0] PINMUX_DIO_PAD_ATTR_1_RESVAL = 13'h 0;
@@ -861,6 +902,8 @@
   parameter logic [12:0] PINMUX_DIO_PAD_ATTR_20_ATTR_20_RESVAL = 13'h 0;
   parameter logic [12:0] PINMUX_DIO_PAD_ATTR_21_RESVAL = 13'h 0;
   parameter logic [12:0] PINMUX_DIO_PAD_ATTR_21_ATTR_21_RESVAL = 13'h 0;
+  parameter logic [12:0] PINMUX_DIO_PAD_ATTR_22_RESVAL = 13'h 0;
+  parameter logic [12:0] PINMUX_DIO_PAD_ATTR_22_ATTR_22_RESVAL = 13'h 0;
   parameter logic [7:0] PINMUX_WKUP_CAUSE_RESVAL = 8'h 0;
   parameter logic [0:0] PINMUX_WKUP_CAUSE_CAUSE_0_RESVAL = 1'h 0;
   parameter logic [0:0] PINMUX_WKUP_CAUSE_CAUSE_1_RESVAL = 1'h 0;
@@ -1046,6 +1089,10 @@
     PINMUX_MIO_OUTSEL_REGWEN_40,
     PINMUX_MIO_OUTSEL_REGWEN_41,
     PINMUX_MIO_OUTSEL_REGWEN_42,
+    PINMUX_MIO_OUTSEL_REGWEN_43,
+    PINMUX_MIO_OUTSEL_REGWEN_44,
+    PINMUX_MIO_OUTSEL_REGWEN_45,
+    PINMUX_MIO_OUTSEL_REGWEN_46,
     PINMUX_MIO_OUTSEL_0,
     PINMUX_MIO_OUTSEL_1,
     PINMUX_MIO_OUTSEL_2,
@@ -1089,6 +1136,10 @@
     PINMUX_MIO_OUTSEL_40,
     PINMUX_MIO_OUTSEL_41,
     PINMUX_MIO_OUTSEL_42,
+    PINMUX_MIO_OUTSEL_43,
+    PINMUX_MIO_OUTSEL_44,
+    PINMUX_MIO_OUTSEL_45,
+    PINMUX_MIO_OUTSEL_46,
     PINMUX_MIO_PAD_ATTR_REGWEN_0,
     PINMUX_MIO_PAD_ATTR_REGWEN_1,
     PINMUX_MIO_PAD_ATTR_REGWEN_2,
@@ -1132,6 +1183,10 @@
     PINMUX_MIO_PAD_ATTR_REGWEN_40,
     PINMUX_MIO_PAD_ATTR_REGWEN_41,
     PINMUX_MIO_PAD_ATTR_REGWEN_42,
+    PINMUX_MIO_PAD_ATTR_REGWEN_43,
+    PINMUX_MIO_PAD_ATTR_REGWEN_44,
+    PINMUX_MIO_PAD_ATTR_REGWEN_45,
+    PINMUX_MIO_PAD_ATTR_REGWEN_46,
     PINMUX_MIO_PAD_ATTR_0,
     PINMUX_MIO_PAD_ATTR_1,
     PINMUX_MIO_PAD_ATTR_2,
@@ -1175,6 +1230,10 @@
     PINMUX_MIO_PAD_ATTR_40,
     PINMUX_MIO_PAD_ATTR_41,
     PINMUX_MIO_PAD_ATTR_42,
+    PINMUX_MIO_PAD_ATTR_43,
+    PINMUX_MIO_PAD_ATTR_44,
+    PINMUX_MIO_PAD_ATTR_45,
+    PINMUX_MIO_PAD_ATTR_46,
     PINMUX_DIO_PAD_ATTR_REGWEN_0,
     PINMUX_DIO_PAD_ATTR_REGWEN_1,
     PINMUX_DIO_PAD_ATTR_REGWEN_2,
@@ -1197,6 +1256,7 @@
     PINMUX_DIO_PAD_ATTR_REGWEN_19,
     PINMUX_DIO_PAD_ATTR_REGWEN_20,
     PINMUX_DIO_PAD_ATTR_REGWEN_21,
+    PINMUX_DIO_PAD_ATTR_REGWEN_22,
     PINMUX_DIO_PAD_ATTR_0,
     PINMUX_DIO_PAD_ATTR_1,
     PINMUX_DIO_PAD_ATTR_2,
@@ -1219,6 +1279,7 @@
     PINMUX_DIO_PAD_ATTR_19,
     PINMUX_DIO_PAD_ATTR_20,
     PINMUX_DIO_PAD_ATTR_21,
+    PINMUX_DIO_PAD_ATTR_22,
     PINMUX_MIO_PAD_SLEEP_STATUS_0,
     PINMUX_MIO_PAD_SLEEP_STATUS_1,
     PINMUX_MIO_PAD_SLEEP_REGWEN_0,
@@ -1264,6 +1325,10 @@
     PINMUX_MIO_PAD_SLEEP_REGWEN_40,
     PINMUX_MIO_PAD_SLEEP_REGWEN_41,
     PINMUX_MIO_PAD_SLEEP_REGWEN_42,
+    PINMUX_MIO_PAD_SLEEP_REGWEN_43,
+    PINMUX_MIO_PAD_SLEEP_REGWEN_44,
+    PINMUX_MIO_PAD_SLEEP_REGWEN_45,
+    PINMUX_MIO_PAD_SLEEP_REGWEN_46,
     PINMUX_MIO_PAD_SLEEP_EN_0,
     PINMUX_MIO_PAD_SLEEP_EN_1,
     PINMUX_MIO_PAD_SLEEP_EN_2,
@@ -1307,6 +1372,10 @@
     PINMUX_MIO_PAD_SLEEP_EN_40,
     PINMUX_MIO_PAD_SLEEP_EN_41,
     PINMUX_MIO_PAD_SLEEP_EN_42,
+    PINMUX_MIO_PAD_SLEEP_EN_43,
+    PINMUX_MIO_PAD_SLEEP_EN_44,
+    PINMUX_MIO_PAD_SLEEP_EN_45,
+    PINMUX_MIO_PAD_SLEEP_EN_46,
     PINMUX_MIO_PAD_SLEEP_MODE_0,
     PINMUX_MIO_PAD_SLEEP_MODE_1,
     PINMUX_MIO_PAD_SLEEP_MODE_2,
@@ -1350,6 +1419,10 @@
     PINMUX_MIO_PAD_SLEEP_MODE_40,
     PINMUX_MIO_PAD_SLEEP_MODE_41,
     PINMUX_MIO_PAD_SLEEP_MODE_42,
+    PINMUX_MIO_PAD_SLEEP_MODE_43,
+    PINMUX_MIO_PAD_SLEEP_MODE_44,
+    PINMUX_MIO_PAD_SLEEP_MODE_45,
+    PINMUX_MIO_PAD_SLEEP_MODE_46,
     PINMUX_DIO_PAD_SLEEP_STATUS,
     PINMUX_DIO_PAD_SLEEP_REGWEN_0,
     PINMUX_DIO_PAD_SLEEP_REGWEN_1,
@@ -1373,6 +1446,7 @@
     PINMUX_DIO_PAD_SLEEP_REGWEN_19,
     PINMUX_DIO_PAD_SLEEP_REGWEN_20,
     PINMUX_DIO_PAD_SLEEP_REGWEN_21,
+    PINMUX_DIO_PAD_SLEEP_REGWEN_22,
     PINMUX_DIO_PAD_SLEEP_EN_0,
     PINMUX_DIO_PAD_SLEEP_EN_1,
     PINMUX_DIO_PAD_SLEEP_EN_2,
@@ -1395,6 +1469,7 @@
     PINMUX_DIO_PAD_SLEEP_EN_19,
     PINMUX_DIO_PAD_SLEEP_EN_20,
     PINMUX_DIO_PAD_SLEEP_EN_21,
+    PINMUX_DIO_PAD_SLEEP_EN_22,
     PINMUX_DIO_PAD_SLEEP_MODE_0,
     PINMUX_DIO_PAD_SLEEP_MODE_1,
     PINMUX_DIO_PAD_SLEEP_MODE_2,
@@ -1417,6 +1492,7 @@
     PINMUX_DIO_PAD_SLEEP_MODE_19,
     PINMUX_DIO_PAD_SLEEP_MODE_20,
     PINMUX_DIO_PAD_SLEEP_MODE_21,
+    PINMUX_DIO_PAD_SLEEP_MODE_22,
     PINMUX_WKUP_DETECTOR_REGWEN_0,
     PINMUX_WKUP_DETECTOR_REGWEN_1,
     PINMUX_WKUP_DETECTOR_REGWEN_2,
@@ -1461,7 +1537,7 @@
   } pinmux_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] PINMUX_PERMIT [585] = '{
+  parameter logic [3:0] PINMUX_PERMIT [618] = '{
     4'b 0001, // index[  0] PINMUX_MIO_PERIPH_INSEL_REGWEN_0
     4'b 0001, // index[  1] PINMUX_MIO_PERIPH_INSEL_REGWEN_1
     4'b 0001, // index[  2] PINMUX_MIO_PERIPH_INSEL_REGWEN_2
@@ -1635,418 +1711,451 @@
     4'b 0001, // index[170] PINMUX_MIO_OUTSEL_REGWEN_40
     4'b 0001, // index[171] PINMUX_MIO_OUTSEL_REGWEN_41
     4'b 0001, // index[172] PINMUX_MIO_OUTSEL_REGWEN_42
-    4'b 0001, // index[173] PINMUX_MIO_OUTSEL_0
-    4'b 0001, // index[174] PINMUX_MIO_OUTSEL_1
-    4'b 0001, // index[175] PINMUX_MIO_OUTSEL_2
-    4'b 0001, // index[176] PINMUX_MIO_OUTSEL_3
-    4'b 0001, // index[177] PINMUX_MIO_OUTSEL_4
-    4'b 0001, // index[178] PINMUX_MIO_OUTSEL_5
-    4'b 0001, // index[179] PINMUX_MIO_OUTSEL_6
-    4'b 0001, // index[180] PINMUX_MIO_OUTSEL_7
-    4'b 0001, // index[181] PINMUX_MIO_OUTSEL_8
-    4'b 0001, // index[182] PINMUX_MIO_OUTSEL_9
-    4'b 0001, // index[183] PINMUX_MIO_OUTSEL_10
-    4'b 0001, // index[184] PINMUX_MIO_OUTSEL_11
-    4'b 0001, // index[185] PINMUX_MIO_OUTSEL_12
-    4'b 0001, // index[186] PINMUX_MIO_OUTSEL_13
-    4'b 0001, // index[187] PINMUX_MIO_OUTSEL_14
-    4'b 0001, // index[188] PINMUX_MIO_OUTSEL_15
-    4'b 0001, // index[189] PINMUX_MIO_OUTSEL_16
-    4'b 0001, // index[190] PINMUX_MIO_OUTSEL_17
-    4'b 0001, // index[191] PINMUX_MIO_OUTSEL_18
-    4'b 0001, // index[192] PINMUX_MIO_OUTSEL_19
-    4'b 0001, // index[193] PINMUX_MIO_OUTSEL_20
-    4'b 0001, // index[194] PINMUX_MIO_OUTSEL_21
-    4'b 0001, // index[195] PINMUX_MIO_OUTSEL_22
-    4'b 0001, // index[196] PINMUX_MIO_OUTSEL_23
-    4'b 0001, // index[197] PINMUX_MIO_OUTSEL_24
-    4'b 0001, // index[198] PINMUX_MIO_OUTSEL_25
-    4'b 0001, // index[199] PINMUX_MIO_OUTSEL_26
-    4'b 0001, // index[200] PINMUX_MIO_OUTSEL_27
-    4'b 0001, // index[201] PINMUX_MIO_OUTSEL_28
-    4'b 0001, // index[202] PINMUX_MIO_OUTSEL_29
-    4'b 0001, // index[203] PINMUX_MIO_OUTSEL_30
-    4'b 0001, // index[204] PINMUX_MIO_OUTSEL_31
-    4'b 0001, // index[205] PINMUX_MIO_OUTSEL_32
-    4'b 0001, // index[206] PINMUX_MIO_OUTSEL_33
-    4'b 0001, // index[207] PINMUX_MIO_OUTSEL_34
-    4'b 0001, // index[208] PINMUX_MIO_OUTSEL_35
-    4'b 0001, // index[209] PINMUX_MIO_OUTSEL_36
-    4'b 0001, // index[210] PINMUX_MIO_OUTSEL_37
-    4'b 0001, // index[211] PINMUX_MIO_OUTSEL_38
-    4'b 0001, // index[212] PINMUX_MIO_OUTSEL_39
-    4'b 0001, // index[213] PINMUX_MIO_OUTSEL_40
-    4'b 0001, // index[214] PINMUX_MIO_OUTSEL_41
-    4'b 0001, // index[215] PINMUX_MIO_OUTSEL_42
-    4'b 0001, // index[216] PINMUX_MIO_PAD_ATTR_REGWEN_0
-    4'b 0001, // index[217] PINMUX_MIO_PAD_ATTR_REGWEN_1
-    4'b 0001, // index[218] PINMUX_MIO_PAD_ATTR_REGWEN_2
-    4'b 0001, // index[219] PINMUX_MIO_PAD_ATTR_REGWEN_3
-    4'b 0001, // index[220] PINMUX_MIO_PAD_ATTR_REGWEN_4
-    4'b 0001, // index[221] PINMUX_MIO_PAD_ATTR_REGWEN_5
-    4'b 0001, // index[222] PINMUX_MIO_PAD_ATTR_REGWEN_6
-    4'b 0001, // index[223] PINMUX_MIO_PAD_ATTR_REGWEN_7
-    4'b 0001, // index[224] PINMUX_MIO_PAD_ATTR_REGWEN_8
-    4'b 0001, // index[225] PINMUX_MIO_PAD_ATTR_REGWEN_9
-    4'b 0001, // index[226] PINMUX_MIO_PAD_ATTR_REGWEN_10
-    4'b 0001, // index[227] PINMUX_MIO_PAD_ATTR_REGWEN_11
-    4'b 0001, // index[228] PINMUX_MIO_PAD_ATTR_REGWEN_12
-    4'b 0001, // index[229] PINMUX_MIO_PAD_ATTR_REGWEN_13
-    4'b 0001, // index[230] PINMUX_MIO_PAD_ATTR_REGWEN_14
-    4'b 0001, // index[231] PINMUX_MIO_PAD_ATTR_REGWEN_15
-    4'b 0001, // index[232] PINMUX_MIO_PAD_ATTR_REGWEN_16
-    4'b 0001, // index[233] PINMUX_MIO_PAD_ATTR_REGWEN_17
-    4'b 0001, // index[234] PINMUX_MIO_PAD_ATTR_REGWEN_18
-    4'b 0001, // index[235] PINMUX_MIO_PAD_ATTR_REGWEN_19
-    4'b 0001, // index[236] PINMUX_MIO_PAD_ATTR_REGWEN_20
-    4'b 0001, // index[237] PINMUX_MIO_PAD_ATTR_REGWEN_21
-    4'b 0001, // index[238] PINMUX_MIO_PAD_ATTR_REGWEN_22
-    4'b 0001, // index[239] PINMUX_MIO_PAD_ATTR_REGWEN_23
-    4'b 0001, // index[240] PINMUX_MIO_PAD_ATTR_REGWEN_24
-    4'b 0001, // index[241] PINMUX_MIO_PAD_ATTR_REGWEN_25
-    4'b 0001, // index[242] PINMUX_MIO_PAD_ATTR_REGWEN_26
-    4'b 0001, // index[243] PINMUX_MIO_PAD_ATTR_REGWEN_27
-    4'b 0001, // index[244] PINMUX_MIO_PAD_ATTR_REGWEN_28
-    4'b 0001, // index[245] PINMUX_MIO_PAD_ATTR_REGWEN_29
-    4'b 0001, // index[246] PINMUX_MIO_PAD_ATTR_REGWEN_30
-    4'b 0001, // index[247] PINMUX_MIO_PAD_ATTR_REGWEN_31
-    4'b 0001, // index[248] PINMUX_MIO_PAD_ATTR_REGWEN_32
-    4'b 0001, // index[249] PINMUX_MIO_PAD_ATTR_REGWEN_33
-    4'b 0001, // index[250] PINMUX_MIO_PAD_ATTR_REGWEN_34
-    4'b 0001, // index[251] PINMUX_MIO_PAD_ATTR_REGWEN_35
-    4'b 0001, // index[252] PINMUX_MIO_PAD_ATTR_REGWEN_36
-    4'b 0001, // index[253] PINMUX_MIO_PAD_ATTR_REGWEN_37
-    4'b 0001, // index[254] PINMUX_MIO_PAD_ATTR_REGWEN_38
-    4'b 0001, // index[255] PINMUX_MIO_PAD_ATTR_REGWEN_39
-    4'b 0001, // index[256] PINMUX_MIO_PAD_ATTR_REGWEN_40
-    4'b 0001, // index[257] PINMUX_MIO_PAD_ATTR_REGWEN_41
-    4'b 0001, // index[258] PINMUX_MIO_PAD_ATTR_REGWEN_42
-    4'b 0011, // index[259] PINMUX_MIO_PAD_ATTR_0
-    4'b 0011, // index[260] PINMUX_MIO_PAD_ATTR_1
-    4'b 0011, // index[261] PINMUX_MIO_PAD_ATTR_2
-    4'b 0011, // index[262] PINMUX_MIO_PAD_ATTR_3
-    4'b 0011, // index[263] PINMUX_MIO_PAD_ATTR_4
-    4'b 0011, // index[264] PINMUX_MIO_PAD_ATTR_5
-    4'b 0011, // index[265] PINMUX_MIO_PAD_ATTR_6
-    4'b 0011, // index[266] PINMUX_MIO_PAD_ATTR_7
-    4'b 0011, // index[267] PINMUX_MIO_PAD_ATTR_8
-    4'b 0011, // index[268] PINMUX_MIO_PAD_ATTR_9
-    4'b 0011, // index[269] PINMUX_MIO_PAD_ATTR_10
-    4'b 0011, // index[270] PINMUX_MIO_PAD_ATTR_11
-    4'b 0011, // index[271] PINMUX_MIO_PAD_ATTR_12
-    4'b 0011, // index[272] PINMUX_MIO_PAD_ATTR_13
-    4'b 0011, // index[273] PINMUX_MIO_PAD_ATTR_14
-    4'b 0011, // index[274] PINMUX_MIO_PAD_ATTR_15
-    4'b 0011, // index[275] PINMUX_MIO_PAD_ATTR_16
-    4'b 0011, // index[276] PINMUX_MIO_PAD_ATTR_17
-    4'b 0011, // index[277] PINMUX_MIO_PAD_ATTR_18
-    4'b 0011, // index[278] PINMUX_MIO_PAD_ATTR_19
-    4'b 0011, // index[279] PINMUX_MIO_PAD_ATTR_20
-    4'b 0011, // index[280] PINMUX_MIO_PAD_ATTR_21
-    4'b 0011, // index[281] PINMUX_MIO_PAD_ATTR_22
-    4'b 0011, // index[282] PINMUX_MIO_PAD_ATTR_23
-    4'b 0011, // index[283] PINMUX_MIO_PAD_ATTR_24
-    4'b 0011, // index[284] PINMUX_MIO_PAD_ATTR_25
-    4'b 0011, // index[285] PINMUX_MIO_PAD_ATTR_26
-    4'b 0011, // index[286] PINMUX_MIO_PAD_ATTR_27
-    4'b 0011, // index[287] PINMUX_MIO_PAD_ATTR_28
-    4'b 0011, // index[288] PINMUX_MIO_PAD_ATTR_29
-    4'b 0011, // index[289] PINMUX_MIO_PAD_ATTR_30
-    4'b 0011, // index[290] PINMUX_MIO_PAD_ATTR_31
-    4'b 0011, // index[291] PINMUX_MIO_PAD_ATTR_32
-    4'b 0011, // index[292] PINMUX_MIO_PAD_ATTR_33
-    4'b 0011, // index[293] PINMUX_MIO_PAD_ATTR_34
-    4'b 0011, // index[294] PINMUX_MIO_PAD_ATTR_35
-    4'b 0011, // index[295] PINMUX_MIO_PAD_ATTR_36
-    4'b 0011, // index[296] PINMUX_MIO_PAD_ATTR_37
-    4'b 0011, // index[297] PINMUX_MIO_PAD_ATTR_38
-    4'b 0011, // index[298] PINMUX_MIO_PAD_ATTR_39
-    4'b 0011, // index[299] PINMUX_MIO_PAD_ATTR_40
-    4'b 0011, // index[300] PINMUX_MIO_PAD_ATTR_41
-    4'b 0011, // index[301] PINMUX_MIO_PAD_ATTR_42
-    4'b 0001, // index[302] PINMUX_DIO_PAD_ATTR_REGWEN_0
-    4'b 0001, // index[303] PINMUX_DIO_PAD_ATTR_REGWEN_1
-    4'b 0001, // index[304] PINMUX_DIO_PAD_ATTR_REGWEN_2
-    4'b 0001, // index[305] PINMUX_DIO_PAD_ATTR_REGWEN_3
-    4'b 0001, // index[306] PINMUX_DIO_PAD_ATTR_REGWEN_4
-    4'b 0001, // index[307] PINMUX_DIO_PAD_ATTR_REGWEN_5
-    4'b 0001, // index[308] PINMUX_DIO_PAD_ATTR_REGWEN_6
-    4'b 0001, // index[309] PINMUX_DIO_PAD_ATTR_REGWEN_7
-    4'b 0001, // index[310] PINMUX_DIO_PAD_ATTR_REGWEN_8
-    4'b 0001, // index[311] PINMUX_DIO_PAD_ATTR_REGWEN_9
-    4'b 0001, // index[312] PINMUX_DIO_PAD_ATTR_REGWEN_10
-    4'b 0001, // index[313] PINMUX_DIO_PAD_ATTR_REGWEN_11
-    4'b 0001, // index[314] PINMUX_DIO_PAD_ATTR_REGWEN_12
-    4'b 0001, // index[315] PINMUX_DIO_PAD_ATTR_REGWEN_13
-    4'b 0001, // index[316] PINMUX_DIO_PAD_ATTR_REGWEN_14
-    4'b 0001, // index[317] PINMUX_DIO_PAD_ATTR_REGWEN_15
-    4'b 0001, // index[318] PINMUX_DIO_PAD_ATTR_REGWEN_16
-    4'b 0001, // index[319] PINMUX_DIO_PAD_ATTR_REGWEN_17
-    4'b 0001, // index[320] PINMUX_DIO_PAD_ATTR_REGWEN_18
-    4'b 0001, // index[321] PINMUX_DIO_PAD_ATTR_REGWEN_19
-    4'b 0001, // index[322] PINMUX_DIO_PAD_ATTR_REGWEN_20
-    4'b 0001, // index[323] PINMUX_DIO_PAD_ATTR_REGWEN_21
-    4'b 0011, // index[324] PINMUX_DIO_PAD_ATTR_0
-    4'b 0011, // index[325] PINMUX_DIO_PAD_ATTR_1
-    4'b 0011, // index[326] PINMUX_DIO_PAD_ATTR_2
-    4'b 0011, // index[327] PINMUX_DIO_PAD_ATTR_3
-    4'b 0011, // index[328] PINMUX_DIO_PAD_ATTR_4
-    4'b 0011, // index[329] PINMUX_DIO_PAD_ATTR_5
-    4'b 0011, // index[330] PINMUX_DIO_PAD_ATTR_6
-    4'b 0011, // index[331] PINMUX_DIO_PAD_ATTR_7
-    4'b 0011, // index[332] PINMUX_DIO_PAD_ATTR_8
-    4'b 0011, // index[333] PINMUX_DIO_PAD_ATTR_9
-    4'b 0011, // index[334] PINMUX_DIO_PAD_ATTR_10
-    4'b 0011, // index[335] PINMUX_DIO_PAD_ATTR_11
-    4'b 0011, // index[336] PINMUX_DIO_PAD_ATTR_12
-    4'b 0011, // index[337] PINMUX_DIO_PAD_ATTR_13
-    4'b 0011, // index[338] PINMUX_DIO_PAD_ATTR_14
-    4'b 0011, // index[339] PINMUX_DIO_PAD_ATTR_15
-    4'b 0011, // index[340] PINMUX_DIO_PAD_ATTR_16
-    4'b 0011, // index[341] PINMUX_DIO_PAD_ATTR_17
-    4'b 0011, // index[342] PINMUX_DIO_PAD_ATTR_18
-    4'b 0011, // index[343] PINMUX_DIO_PAD_ATTR_19
-    4'b 0011, // index[344] PINMUX_DIO_PAD_ATTR_20
-    4'b 0011, // index[345] PINMUX_DIO_PAD_ATTR_21
-    4'b 1111, // index[346] PINMUX_MIO_PAD_SLEEP_STATUS_0
-    4'b 0011, // index[347] PINMUX_MIO_PAD_SLEEP_STATUS_1
-    4'b 0001, // index[348] PINMUX_MIO_PAD_SLEEP_REGWEN_0
-    4'b 0001, // index[349] PINMUX_MIO_PAD_SLEEP_REGWEN_1
-    4'b 0001, // index[350] PINMUX_MIO_PAD_SLEEP_REGWEN_2
-    4'b 0001, // index[351] PINMUX_MIO_PAD_SLEEP_REGWEN_3
-    4'b 0001, // index[352] PINMUX_MIO_PAD_SLEEP_REGWEN_4
-    4'b 0001, // index[353] PINMUX_MIO_PAD_SLEEP_REGWEN_5
-    4'b 0001, // index[354] PINMUX_MIO_PAD_SLEEP_REGWEN_6
-    4'b 0001, // index[355] PINMUX_MIO_PAD_SLEEP_REGWEN_7
-    4'b 0001, // index[356] PINMUX_MIO_PAD_SLEEP_REGWEN_8
-    4'b 0001, // index[357] PINMUX_MIO_PAD_SLEEP_REGWEN_9
-    4'b 0001, // index[358] PINMUX_MIO_PAD_SLEEP_REGWEN_10
-    4'b 0001, // index[359] PINMUX_MIO_PAD_SLEEP_REGWEN_11
-    4'b 0001, // index[360] PINMUX_MIO_PAD_SLEEP_REGWEN_12
-    4'b 0001, // index[361] PINMUX_MIO_PAD_SLEEP_REGWEN_13
-    4'b 0001, // index[362] PINMUX_MIO_PAD_SLEEP_REGWEN_14
-    4'b 0001, // index[363] PINMUX_MIO_PAD_SLEEP_REGWEN_15
-    4'b 0001, // index[364] PINMUX_MIO_PAD_SLEEP_REGWEN_16
-    4'b 0001, // index[365] PINMUX_MIO_PAD_SLEEP_REGWEN_17
-    4'b 0001, // index[366] PINMUX_MIO_PAD_SLEEP_REGWEN_18
-    4'b 0001, // index[367] PINMUX_MIO_PAD_SLEEP_REGWEN_19
-    4'b 0001, // index[368] PINMUX_MIO_PAD_SLEEP_REGWEN_20
-    4'b 0001, // index[369] PINMUX_MIO_PAD_SLEEP_REGWEN_21
-    4'b 0001, // index[370] PINMUX_MIO_PAD_SLEEP_REGWEN_22
-    4'b 0001, // index[371] PINMUX_MIO_PAD_SLEEP_REGWEN_23
-    4'b 0001, // index[372] PINMUX_MIO_PAD_SLEEP_REGWEN_24
-    4'b 0001, // index[373] PINMUX_MIO_PAD_SLEEP_REGWEN_25
-    4'b 0001, // index[374] PINMUX_MIO_PAD_SLEEP_REGWEN_26
-    4'b 0001, // index[375] PINMUX_MIO_PAD_SLEEP_REGWEN_27
-    4'b 0001, // index[376] PINMUX_MIO_PAD_SLEEP_REGWEN_28
-    4'b 0001, // index[377] PINMUX_MIO_PAD_SLEEP_REGWEN_29
-    4'b 0001, // index[378] PINMUX_MIO_PAD_SLEEP_REGWEN_30
-    4'b 0001, // index[379] PINMUX_MIO_PAD_SLEEP_REGWEN_31
-    4'b 0001, // index[380] PINMUX_MIO_PAD_SLEEP_REGWEN_32
-    4'b 0001, // index[381] PINMUX_MIO_PAD_SLEEP_REGWEN_33
-    4'b 0001, // index[382] PINMUX_MIO_PAD_SLEEP_REGWEN_34
-    4'b 0001, // index[383] PINMUX_MIO_PAD_SLEEP_REGWEN_35
-    4'b 0001, // index[384] PINMUX_MIO_PAD_SLEEP_REGWEN_36
-    4'b 0001, // index[385] PINMUX_MIO_PAD_SLEEP_REGWEN_37
-    4'b 0001, // index[386] PINMUX_MIO_PAD_SLEEP_REGWEN_38
-    4'b 0001, // index[387] PINMUX_MIO_PAD_SLEEP_REGWEN_39
-    4'b 0001, // index[388] PINMUX_MIO_PAD_SLEEP_REGWEN_40
-    4'b 0001, // index[389] PINMUX_MIO_PAD_SLEEP_REGWEN_41
-    4'b 0001, // index[390] PINMUX_MIO_PAD_SLEEP_REGWEN_42
-    4'b 0001, // index[391] PINMUX_MIO_PAD_SLEEP_EN_0
-    4'b 0001, // index[392] PINMUX_MIO_PAD_SLEEP_EN_1
-    4'b 0001, // index[393] PINMUX_MIO_PAD_SLEEP_EN_2
-    4'b 0001, // index[394] PINMUX_MIO_PAD_SLEEP_EN_3
-    4'b 0001, // index[395] PINMUX_MIO_PAD_SLEEP_EN_4
-    4'b 0001, // index[396] PINMUX_MIO_PAD_SLEEP_EN_5
-    4'b 0001, // index[397] PINMUX_MIO_PAD_SLEEP_EN_6
-    4'b 0001, // index[398] PINMUX_MIO_PAD_SLEEP_EN_7
-    4'b 0001, // index[399] PINMUX_MIO_PAD_SLEEP_EN_8
-    4'b 0001, // index[400] PINMUX_MIO_PAD_SLEEP_EN_9
-    4'b 0001, // index[401] PINMUX_MIO_PAD_SLEEP_EN_10
-    4'b 0001, // index[402] PINMUX_MIO_PAD_SLEEP_EN_11
-    4'b 0001, // index[403] PINMUX_MIO_PAD_SLEEP_EN_12
-    4'b 0001, // index[404] PINMUX_MIO_PAD_SLEEP_EN_13
-    4'b 0001, // index[405] PINMUX_MIO_PAD_SLEEP_EN_14
-    4'b 0001, // index[406] PINMUX_MIO_PAD_SLEEP_EN_15
-    4'b 0001, // index[407] PINMUX_MIO_PAD_SLEEP_EN_16
-    4'b 0001, // index[408] PINMUX_MIO_PAD_SLEEP_EN_17
-    4'b 0001, // index[409] PINMUX_MIO_PAD_SLEEP_EN_18
-    4'b 0001, // index[410] PINMUX_MIO_PAD_SLEEP_EN_19
-    4'b 0001, // index[411] PINMUX_MIO_PAD_SLEEP_EN_20
-    4'b 0001, // index[412] PINMUX_MIO_PAD_SLEEP_EN_21
-    4'b 0001, // index[413] PINMUX_MIO_PAD_SLEEP_EN_22
-    4'b 0001, // index[414] PINMUX_MIO_PAD_SLEEP_EN_23
-    4'b 0001, // index[415] PINMUX_MIO_PAD_SLEEP_EN_24
-    4'b 0001, // index[416] PINMUX_MIO_PAD_SLEEP_EN_25
-    4'b 0001, // index[417] PINMUX_MIO_PAD_SLEEP_EN_26
-    4'b 0001, // index[418] PINMUX_MIO_PAD_SLEEP_EN_27
-    4'b 0001, // index[419] PINMUX_MIO_PAD_SLEEP_EN_28
-    4'b 0001, // index[420] PINMUX_MIO_PAD_SLEEP_EN_29
-    4'b 0001, // index[421] PINMUX_MIO_PAD_SLEEP_EN_30
-    4'b 0001, // index[422] PINMUX_MIO_PAD_SLEEP_EN_31
-    4'b 0001, // index[423] PINMUX_MIO_PAD_SLEEP_EN_32
-    4'b 0001, // index[424] PINMUX_MIO_PAD_SLEEP_EN_33
-    4'b 0001, // index[425] PINMUX_MIO_PAD_SLEEP_EN_34
-    4'b 0001, // index[426] PINMUX_MIO_PAD_SLEEP_EN_35
-    4'b 0001, // index[427] PINMUX_MIO_PAD_SLEEP_EN_36
-    4'b 0001, // index[428] PINMUX_MIO_PAD_SLEEP_EN_37
-    4'b 0001, // index[429] PINMUX_MIO_PAD_SLEEP_EN_38
-    4'b 0001, // index[430] PINMUX_MIO_PAD_SLEEP_EN_39
-    4'b 0001, // index[431] PINMUX_MIO_PAD_SLEEP_EN_40
-    4'b 0001, // index[432] PINMUX_MIO_PAD_SLEEP_EN_41
-    4'b 0001, // index[433] PINMUX_MIO_PAD_SLEEP_EN_42
-    4'b 0001, // index[434] PINMUX_MIO_PAD_SLEEP_MODE_0
-    4'b 0001, // index[435] PINMUX_MIO_PAD_SLEEP_MODE_1
-    4'b 0001, // index[436] PINMUX_MIO_PAD_SLEEP_MODE_2
-    4'b 0001, // index[437] PINMUX_MIO_PAD_SLEEP_MODE_3
-    4'b 0001, // index[438] PINMUX_MIO_PAD_SLEEP_MODE_4
-    4'b 0001, // index[439] PINMUX_MIO_PAD_SLEEP_MODE_5
-    4'b 0001, // index[440] PINMUX_MIO_PAD_SLEEP_MODE_6
-    4'b 0001, // index[441] PINMUX_MIO_PAD_SLEEP_MODE_7
-    4'b 0001, // index[442] PINMUX_MIO_PAD_SLEEP_MODE_8
-    4'b 0001, // index[443] PINMUX_MIO_PAD_SLEEP_MODE_9
-    4'b 0001, // index[444] PINMUX_MIO_PAD_SLEEP_MODE_10
-    4'b 0001, // index[445] PINMUX_MIO_PAD_SLEEP_MODE_11
-    4'b 0001, // index[446] PINMUX_MIO_PAD_SLEEP_MODE_12
-    4'b 0001, // index[447] PINMUX_MIO_PAD_SLEEP_MODE_13
-    4'b 0001, // index[448] PINMUX_MIO_PAD_SLEEP_MODE_14
-    4'b 0001, // index[449] PINMUX_MIO_PAD_SLEEP_MODE_15
-    4'b 0001, // index[450] PINMUX_MIO_PAD_SLEEP_MODE_16
-    4'b 0001, // index[451] PINMUX_MIO_PAD_SLEEP_MODE_17
-    4'b 0001, // index[452] PINMUX_MIO_PAD_SLEEP_MODE_18
-    4'b 0001, // index[453] PINMUX_MIO_PAD_SLEEP_MODE_19
-    4'b 0001, // index[454] PINMUX_MIO_PAD_SLEEP_MODE_20
-    4'b 0001, // index[455] PINMUX_MIO_PAD_SLEEP_MODE_21
-    4'b 0001, // index[456] PINMUX_MIO_PAD_SLEEP_MODE_22
-    4'b 0001, // index[457] PINMUX_MIO_PAD_SLEEP_MODE_23
-    4'b 0001, // index[458] PINMUX_MIO_PAD_SLEEP_MODE_24
-    4'b 0001, // index[459] PINMUX_MIO_PAD_SLEEP_MODE_25
-    4'b 0001, // index[460] PINMUX_MIO_PAD_SLEEP_MODE_26
-    4'b 0001, // index[461] PINMUX_MIO_PAD_SLEEP_MODE_27
-    4'b 0001, // index[462] PINMUX_MIO_PAD_SLEEP_MODE_28
-    4'b 0001, // index[463] PINMUX_MIO_PAD_SLEEP_MODE_29
-    4'b 0001, // index[464] PINMUX_MIO_PAD_SLEEP_MODE_30
-    4'b 0001, // index[465] PINMUX_MIO_PAD_SLEEP_MODE_31
-    4'b 0001, // index[466] PINMUX_MIO_PAD_SLEEP_MODE_32
-    4'b 0001, // index[467] PINMUX_MIO_PAD_SLEEP_MODE_33
-    4'b 0001, // index[468] PINMUX_MIO_PAD_SLEEP_MODE_34
-    4'b 0001, // index[469] PINMUX_MIO_PAD_SLEEP_MODE_35
-    4'b 0001, // index[470] PINMUX_MIO_PAD_SLEEP_MODE_36
-    4'b 0001, // index[471] PINMUX_MIO_PAD_SLEEP_MODE_37
-    4'b 0001, // index[472] PINMUX_MIO_PAD_SLEEP_MODE_38
-    4'b 0001, // index[473] PINMUX_MIO_PAD_SLEEP_MODE_39
-    4'b 0001, // index[474] PINMUX_MIO_PAD_SLEEP_MODE_40
-    4'b 0001, // index[475] PINMUX_MIO_PAD_SLEEP_MODE_41
-    4'b 0001, // index[476] PINMUX_MIO_PAD_SLEEP_MODE_42
-    4'b 0111, // index[477] PINMUX_DIO_PAD_SLEEP_STATUS
-    4'b 0001, // index[478] PINMUX_DIO_PAD_SLEEP_REGWEN_0
-    4'b 0001, // index[479] PINMUX_DIO_PAD_SLEEP_REGWEN_1
-    4'b 0001, // index[480] PINMUX_DIO_PAD_SLEEP_REGWEN_2
-    4'b 0001, // index[481] PINMUX_DIO_PAD_SLEEP_REGWEN_3
-    4'b 0001, // index[482] PINMUX_DIO_PAD_SLEEP_REGWEN_4
-    4'b 0001, // index[483] PINMUX_DIO_PAD_SLEEP_REGWEN_5
-    4'b 0001, // index[484] PINMUX_DIO_PAD_SLEEP_REGWEN_6
-    4'b 0001, // index[485] PINMUX_DIO_PAD_SLEEP_REGWEN_7
-    4'b 0001, // index[486] PINMUX_DIO_PAD_SLEEP_REGWEN_8
-    4'b 0001, // index[487] PINMUX_DIO_PAD_SLEEP_REGWEN_9
-    4'b 0001, // index[488] PINMUX_DIO_PAD_SLEEP_REGWEN_10
-    4'b 0001, // index[489] PINMUX_DIO_PAD_SLEEP_REGWEN_11
-    4'b 0001, // index[490] PINMUX_DIO_PAD_SLEEP_REGWEN_12
-    4'b 0001, // index[491] PINMUX_DIO_PAD_SLEEP_REGWEN_13
-    4'b 0001, // index[492] PINMUX_DIO_PAD_SLEEP_REGWEN_14
-    4'b 0001, // index[493] PINMUX_DIO_PAD_SLEEP_REGWEN_15
-    4'b 0001, // index[494] PINMUX_DIO_PAD_SLEEP_REGWEN_16
-    4'b 0001, // index[495] PINMUX_DIO_PAD_SLEEP_REGWEN_17
-    4'b 0001, // index[496] PINMUX_DIO_PAD_SLEEP_REGWEN_18
-    4'b 0001, // index[497] PINMUX_DIO_PAD_SLEEP_REGWEN_19
-    4'b 0001, // index[498] PINMUX_DIO_PAD_SLEEP_REGWEN_20
-    4'b 0001, // index[499] PINMUX_DIO_PAD_SLEEP_REGWEN_21
-    4'b 0001, // index[500] PINMUX_DIO_PAD_SLEEP_EN_0
-    4'b 0001, // index[501] PINMUX_DIO_PAD_SLEEP_EN_1
-    4'b 0001, // index[502] PINMUX_DIO_PAD_SLEEP_EN_2
-    4'b 0001, // index[503] PINMUX_DIO_PAD_SLEEP_EN_3
-    4'b 0001, // index[504] PINMUX_DIO_PAD_SLEEP_EN_4
-    4'b 0001, // index[505] PINMUX_DIO_PAD_SLEEP_EN_5
-    4'b 0001, // index[506] PINMUX_DIO_PAD_SLEEP_EN_6
-    4'b 0001, // index[507] PINMUX_DIO_PAD_SLEEP_EN_7
-    4'b 0001, // index[508] PINMUX_DIO_PAD_SLEEP_EN_8
-    4'b 0001, // index[509] PINMUX_DIO_PAD_SLEEP_EN_9
-    4'b 0001, // index[510] PINMUX_DIO_PAD_SLEEP_EN_10
-    4'b 0001, // index[511] PINMUX_DIO_PAD_SLEEP_EN_11
-    4'b 0001, // index[512] PINMUX_DIO_PAD_SLEEP_EN_12
-    4'b 0001, // index[513] PINMUX_DIO_PAD_SLEEP_EN_13
-    4'b 0001, // index[514] PINMUX_DIO_PAD_SLEEP_EN_14
-    4'b 0001, // index[515] PINMUX_DIO_PAD_SLEEP_EN_15
-    4'b 0001, // index[516] PINMUX_DIO_PAD_SLEEP_EN_16
-    4'b 0001, // index[517] PINMUX_DIO_PAD_SLEEP_EN_17
-    4'b 0001, // index[518] PINMUX_DIO_PAD_SLEEP_EN_18
-    4'b 0001, // index[519] PINMUX_DIO_PAD_SLEEP_EN_19
-    4'b 0001, // index[520] PINMUX_DIO_PAD_SLEEP_EN_20
-    4'b 0001, // index[521] PINMUX_DIO_PAD_SLEEP_EN_21
-    4'b 0001, // index[522] PINMUX_DIO_PAD_SLEEP_MODE_0
-    4'b 0001, // index[523] PINMUX_DIO_PAD_SLEEP_MODE_1
-    4'b 0001, // index[524] PINMUX_DIO_PAD_SLEEP_MODE_2
-    4'b 0001, // index[525] PINMUX_DIO_PAD_SLEEP_MODE_3
-    4'b 0001, // index[526] PINMUX_DIO_PAD_SLEEP_MODE_4
-    4'b 0001, // index[527] PINMUX_DIO_PAD_SLEEP_MODE_5
-    4'b 0001, // index[528] PINMUX_DIO_PAD_SLEEP_MODE_6
-    4'b 0001, // index[529] PINMUX_DIO_PAD_SLEEP_MODE_7
-    4'b 0001, // index[530] PINMUX_DIO_PAD_SLEEP_MODE_8
-    4'b 0001, // index[531] PINMUX_DIO_PAD_SLEEP_MODE_9
-    4'b 0001, // index[532] PINMUX_DIO_PAD_SLEEP_MODE_10
-    4'b 0001, // index[533] PINMUX_DIO_PAD_SLEEP_MODE_11
-    4'b 0001, // index[534] PINMUX_DIO_PAD_SLEEP_MODE_12
-    4'b 0001, // index[535] PINMUX_DIO_PAD_SLEEP_MODE_13
-    4'b 0001, // index[536] PINMUX_DIO_PAD_SLEEP_MODE_14
-    4'b 0001, // index[537] PINMUX_DIO_PAD_SLEEP_MODE_15
-    4'b 0001, // index[538] PINMUX_DIO_PAD_SLEEP_MODE_16
-    4'b 0001, // index[539] PINMUX_DIO_PAD_SLEEP_MODE_17
-    4'b 0001, // index[540] PINMUX_DIO_PAD_SLEEP_MODE_18
-    4'b 0001, // index[541] PINMUX_DIO_PAD_SLEEP_MODE_19
-    4'b 0001, // index[542] PINMUX_DIO_PAD_SLEEP_MODE_20
-    4'b 0001, // index[543] PINMUX_DIO_PAD_SLEEP_MODE_21
-    4'b 0001, // index[544] PINMUX_WKUP_DETECTOR_REGWEN_0
-    4'b 0001, // index[545] PINMUX_WKUP_DETECTOR_REGWEN_1
-    4'b 0001, // index[546] PINMUX_WKUP_DETECTOR_REGWEN_2
-    4'b 0001, // index[547] PINMUX_WKUP_DETECTOR_REGWEN_3
-    4'b 0001, // index[548] PINMUX_WKUP_DETECTOR_REGWEN_4
-    4'b 0001, // index[549] PINMUX_WKUP_DETECTOR_REGWEN_5
-    4'b 0001, // index[550] PINMUX_WKUP_DETECTOR_REGWEN_6
-    4'b 0001, // index[551] PINMUX_WKUP_DETECTOR_REGWEN_7
-    4'b 0001, // index[552] PINMUX_WKUP_DETECTOR_EN_0
-    4'b 0001, // index[553] PINMUX_WKUP_DETECTOR_EN_1
-    4'b 0001, // index[554] PINMUX_WKUP_DETECTOR_EN_2
-    4'b 0001, // index[555] PINMUX_WKUP_DETECTOR_EN_3
-    4'b 0001, // index[556] PINMUX_WKUP_DETECTOR_EN_4
-    4'b 0001, // index[557] PINMUX_WKUP_DETECTOR_EN_5
-    4'b 0001, // index[558] PINMUX_WKUP_DETECTOR_EN_6
-    4'b 0001, // index[559] PINMUX_WKUP_DETECTOR_EN_7
-    4'b 0001, // index[560] PINMUX_WKUP_DETECTOR_0
-    4'b 0001, // index[561] PINMUX_WKUP_DETECTOR_1
-    4'b 0001, // index[562] PINMUX_WKUP_DETECTOR_2
-    4'b 0001, // index[563] PINMUX_WKUP_DETECTOR_3
-    4'b 0001, // index[564] PINMUX_WKUP_DETECTOR_4
-    4'b 0001, // index[565] PINMUX_WKUP_DETECTOR_5
-    4'b 0001, // index[566] PINMUX_WKUP_DETECTOR_6
-    4'b 0001, // index[567] PINMUX_WKUP_DETECTOR_7
-    4'b 0001, // index[568] PINMUX_WKUP_DETECTOR_CNT_TH_0
-    4'b 0001, // index[569] PINMUX_WKUP_DETECTOR_CNT_TH_1
-    4'b 0001, // index[570] PINMUX_WKUP_DETECTOR_CNT_TH_2
-    4'b 0001, // index[571] PINMUX_WKUP_DETECTOR_CNT_TH_3
-    4'b 0001, // index[572] PINMUX_WKUP_DETECTOR_CNT_TH_4
-    4'b 0001, // index[573] PINMUX_WKUP_DETECTOR_CNT_TH_5
-    4'b 0001, // index[574] PINMUX_WKUP_DETECTOR_CNT_TH_6
-    4'b 0001, // index[575] PINMUX_WKUP_DETECTOR_CNT_TH_7
-    4'b 0001, // index[576] PINMUX_WKUP_DETECTOR_PADSEL_0
-    4'b 0001, // index[577] PINMUX_WKUP_DETECTOR_PADSEL_1
-    4'b 0001, // index[578] PINMUX_WKUP_DETECTOR_PADSEL_2
-    4'b 0001, // index[579] PINMUX_WKUP_DETECTOR_PADSEL_3
-    4'b 0001, // index[580] PINMUX_WKUP_DETECTOR_PADSEL_4
-    4'b 0001, // index[581] PINMUX_WKUP_DETECTOR_PADSEL_5
-    4'b 0001, // index[582] PINMUX_WKUP_DETECTOR_PADSEL_6
-    4'b 0001, // index[583] PINMUX_WKUP_DETECTOR_PADSEL_7
-    4'b 0001  // index[584] PINMUX_WKUP_CAUSE
+    4'b 0001, // index[173] PINMUX_MIO_OUTSEL_REGWEN_43
+    4'b 0001, // index[174] PINMUX_MIO_OUTSEL_REGWEN_44
+    4'b 0001, // index[175] PINMUX_MIO_OUTSEL_REGWEN_45
+    4'b 0001, // index[176] PINMUX_MIO_OUTSEL_REGWEN_46
+    4'b 0001, // index[177] PINMUX_MIO_OUTSEL_0
+    4'b 0001, // index[178] PINMUX_MIO_OUTSEL_1
+    4'b 0001, // index[179] PINMUX_MIO_OUTSEL_2
+    4'b 0001, // index[180] PINMUX_MIO_OUTSEL_3
+    4'b 0001, // index[181] PINMUX_MIO_OUTSEL_4
+    4'b 0001, // index[182] PINMUX_MIO_OUTSEL_5
+    4'b 0001, // index[183] PINMUX_MIO_OUTSEL_6
+    4'b 0001, // index[184] PINMUX_MIO_OUTSEL_7
+    4'b 0001, // index[185] PINMUX_MIO_OUTSEL_8
+    4'b 0001, // index[186] PINMUX_MIO_OUTSEL_9
+    4'b 0001, // index[187] PINMUX_MIO_OUTSEL_10
+    4'b 0001, // index[188] PINMUX_MIO_OUTSEL_11
+    4'b 0001, // index[189] PINMUX_MIO_OUTSEL_12
+    4'b 0001, // index[190] PINMUX_MIO_OUTSEL_13
+    4'b 0001, // index[191] PINMUX_MIO_OUTSEL_14
+    4'b 0001, // index[192] PINMUX_MIO_OUTSEL_15
+    4'b 0001, // index[193] PINMUX_MIO_OUTSEL_16
+    4'b 0001, // index[194] PINMUX_MIO_OUTSEL_17
+    4'b 0001, // index[195] PINMUX_MIO_OUTSEL_18
+    4'b 0001, // index[196] PINMUX_MIO_OUTSEL_19
+    4'b 0001, // index[197] PINMUX_MIO_OUTSEL_20
+    4'b 0001, // index[198] PINMUX_MIO_OUTSEL_21
+    4'b 0001, // index[199] PINMUX_MIO_OUTSEL_22
+    4'b 0001, // index[200] PINMUX_MIO_OUTSEL_23
+    4'b 0001, // index[201] PINMUX_MIO_OUTSEL_24
+    4'b 0001, // index[202] PINMUX_MIO_OUTSEL_25
+    4'b 0001, // index[203] PINMUX_MIO_OUTSEL_26
+    4'b 0001, // index[204] PINMUX_MIO_OUTSEL_27
+    4'b 0001, // index[205] PINMUX_MIO_OUTSEL_28
+    4'b 0001, // index[206] PINMUX_MIO_OUTSEL_29
+    4'b 0001, // index[207] PINMUX_MIO_OUTSEL_30
+    4'b 0001, // index[208] PINMUX_MIO_OUTSEL_31
+    4'b 0001, // index[209] PINMUX_MIO_OUTSEL_32
+    4'b 0001, // index[210] PINMUX_MIO_OUTSEL_33
+    4'b 0001, // index[211] PINMUX_MIO_OUTSEL_34
+    4'b 0001, // index[212] PINMUX_MIO_OUTSEL_35
+    4'b 0001, // index[213] PINMUX_MIO_OUTSEL_36
+    4'b 0001, // index[214] PINMUX_MIO_OUTSEL_37
+    4'b 0001, // index[215] PINMUX_MIO_OUTSEL_38
+    4'b 0001, // index[216] PINMUX_MIO_OUTSEL_39
+    4'b 0001, // index[217] PINMUX_MIO_OUTSEL_40
+    4'b 0001, // index[218] PINMUX_MIO_OUTSEL_41
+    4'b 0001, // index[219] PINMUX_MIO_OUTSEL_42
+    4'b 0001, // index[220] PINMUX_MIO_OUTSEL_43
+    4'b 0001, // index[221] PINMUX_MIO_OUTSEL_44
+    4'b 0001, // index[222] PINMUX_MIO_OUTSEL_45
+    4'b 0001, // index[223] PINMUX_MIO_OUTSEL_46
+    4'b 0001, // index[224] PINMUX_MIO_PAD_ATTR_REGWEN_0
+    4'b 0001, // index[225] PINMUX_MIO_PAD_ATTR_REGWEN_1
+    4'b 0001, // index[226] PINMUX_MIO_PAD_ATTR_REGWEN_2
+    4'b 0001, // index[227] PINMUX_MIO_PAD_ATTR_REGWEN_3
+    4'b 0001, // index[228] PINMUX_MIO_PAD_ATTR_REGWEN_4
+    4'b 0001, // index[229] PINMUX_MIO_PAD_ATTR_REGWEN_5
+    4'b 0001, // index[230] PINMUX_MIO_PAD_ATTR_REGWEN_6
+    4'b 0001, // index[231] PINMUX_MIO_PAD_ATTR_REGWEN_7
+    4'b 0001, // index[232] PINMUX_MIO_PAD_ATTR_REGWEN_8
+    4'b 0001, // index[233] PINMUX_MIO_PAD_ATTR_REGWEN_9
+    4'b 0001, // index[234] PINMUX_MIO_PAD_ATTR_REGWEN_10
+    4'b 0001, // index[235] PINMUX_MIO_PAD_ATTR_REGWEN_11
+    4'b 0001, // index[236] PINMUX_MIO_PAD_ATTR_REGWEN_12
+    4'b 0001, // index[237] PINMUX_MIO_PAD_ATTR_REGWEN_13
+    4'b 0001, // index[238] PINMUX_MIO_PAD_ATTR_REGWEN_14
+    4'b 0001, // index[239] PINMUX_MIO_PAD_ATTR_REGWEN_15
+    4'b 0001, // index[240] PINMUX_MIO_PAD_ATTR_REGWEN_16
+    4'b 0001, // index[241] PINMUX_MIO_PAD_ATTR_REGWEN_17
+    4'b 0001, // index[242] PINMUX_MIO_PAD_ATTR_REGWEN_18
+    4'b 0001, // index[243] PINMUX_MIO_PAD_ATTR_REGWEN_19
+    4'b 0001, // index[244] PINMUX_MIO_PAD_ATTR_REGWEN_20
+    4'b 0001, // index[245] PINMUX_MIO_PAD_ATTR_REGWEN_21
+    4'b 0001, // index[246] PINMUX_MIO_PAD_ATTR_REGWEN_22
+    4'b 0001, // index[247] PINMUX_MIO_PAD_ATTR_REGWEN_23
+    4'b 0001, // index[248] PINMUX_MIO_PAD_ATTR_REGWEN_24
+    4'b 0001, // index[249] PINMUX_MIO_PAD_ATTR_REGWEN_25
+    4'b 0001, // index[250] PINMUX_MIO_PAD_ATTR_REGWEN_26
+    4'b 0001, // index[251] PINMUX_MIO_PAD_ATTR_REGWEN_27
+    4'b 0001, // index[252] PINMUX_MIO_PAD_ATTR_REGWEN_28
+    4'b 0001, // index[253] PINMUX_MIO_PAD_ATTR_REGWEN_29
+    4'b 0001, // index[254] PINMUX_MIO_PAD_ATTR_REGWEN_30
+    4'b 0001, // index[255] PINMUX_MIO_PAD_ATTR_REGWEN_31
+    4'b 0001, // index[256] PINMUX_MIO_PAD_ATTR_REGWEN_32
+    4'b 0001, // index[257] PINMUX_MIO_PAD_ATTR_REGWEN_33
+    4'b 0001, // index[258] PINMUX_MIO_PAD_ATTR_REGWEN_34
+    4'b 0001, // index[259] PINMUX_MIO_PAD_ATTR_REGWEN_35
+    4'b 0001, // index[260] PINMUX_MIO_PAD_ATTR_REGWEN_36
+    4'b 0001, // index[261] PINMUX_MIO_PAD_ATTR_REGWEN_37
+    4'b 0001, // index[262] PINMUX_MIO_PAD_ATTR_REGWEN_38
+    4'b 0001, // index[263] PINMUX_MIO_PAD_ATTR_REGWEN_39
+    4'b 0001, // index[264] PINMUX_MIO_PAD_ATTR_REGWEN_40
+    4'b 0001, // index[265] PINMUX_MIO_PAD_ATTR_REGWEN_41
+    4'b 0001, // index[266] PINMUX_MIO_PAD_ATTR_REGWEN_42
+    4'b 0001, // index[267] PINMUX_MIO_PAD_ATTR_REGWEN_43
+    4'b 0001, // index[268] PINMUX_MIO_PAD_ATTR_REGWEN_44
+    4'b 0001, // index[269] PINMUX_MIO_PAD_ATTR_REGWEN_45
+    4'b 0001, // index[270] PINMUX_MIO_PAD_ATTR_REGWEN_46
+    4'b 0011, // index[271] PINMUX_MIO_PAD_ATTR_0
+    4'b 0011, // index[272] PINMUX_MIO_PAD_ATTR_1
+    4'b 0011, // index[273] PINMUX_MIO_PAD_ATTR_2
+    4'b 0011, // index[274] PINMUX_MIO_PAD_ATTR_3
+    4'b 0011, // index[275] PINMUX_MIO_PAD_ATTR_4
+    4'b 0011, // index[276] PINMUX_MIO_PAD_ATTR_5
+    4'b 0011, // index[277] PINMUX_MIO_PAD_ATTR_6
+    4'b 0011, // index[278] PINMUX_MIO_PAD_ATTR_7
+    4'b 0011, // index[279] PINMUX_MIO_PAD_ATTR_8
+    4'b 0011, // index[280] PINMUX_MIO_PAD_ATTR_9
+    4'b 0011, // index[281] PINMUX_MIO_PAD_ATTR_10
+    4'b 0011, // index[282] PINMUX_MIO_PAD_ATTR_11
+    4'b 0011, // index[283] PINMUX_MIO_PAD_ATTR_12
+    4'b 0011, // index[284] PINMUX_MIO_PAD_ATTR_13
+    4'b 0011, // index[285] PINMUX_MIO_PAD_ATTR_14
+    4'b 0011, // index[286] PINMUX_MIO_PAD_ATTR_15
+    4'b 0011, // index[287] PINMUX_MIO_PAD_ATTR_16
+    4'b 0011, // index[288] PINMUX_MIO_PAD_ATTR_17
+    4'b 0011, // index[289] PINMUX_MIO_PAD_ATTR_18
+    4'b 0011, // index[290] PINMUX_MIO_PAD_ATTR_19
+    4'b 0011, // index[291] PINMUX_MIO_PAD_ATTR_20
+    4'b 0011, // index[292] PINMUX_MIO_PAD_ATTR_21
+    4'b 0011, // index[293] PINMUX_MIO_PAD_ATTR_22
+    4'b 0011, // index[294] PINMUX_MIO_PAD_ATTR_23
+    4'b 0011, // index[295] PINMUX_MIO_PAD_ATTR_24
+    4'b 0011, // index[296] PINMUX_MIO_PAD_ATTR_25
+    4'b 0011, // index[297] PINMUX_MIO_PAD_ATTR_26
+    4'b 0011, // index[298] PINMUX_MIO_PAD_ATTR_27
+    4'b 0011, // index[299] PINMUX_MIO_PAD_ATTR_28
+    4'b 0011, // index[300] PINMUX_MIO_PAD_ATTR_29
+    4'b 0011, // index[301] PINMUX_MIO_PAD_ATTR_30
+    4'b 0011, // index[302] PINMUX_MIO_PAD_ATTR_31
+    4'b 0011, // index[303] PINMUX_MIO_PAD_ATTR_32
+    4'b 0011, // index[304] PINMUX_MIO_PAD_ATTR_33
+    4'b 0011, // index[305] PINMUX_MIO_PAD_ATTR_34
+    4'b 0011, // index[306] PINMUX_MIO_PAD_ATTR_35
+    4'b 0011, // index[307] PINMUX_MIO_PAD_ATTR_36
+    4'b 0011, // index[308] PINMUX_MIO_PAD_ATTR_37
+    4'b 0011, // index[309] PINMUX_MIO_PAD_ATTR_38
+    4'b 0011, // index[310] PINMUX_MIO_PAD_ATTR_39
+    4'b 0011, // index[311] PINMUX_MIO_PAD_ATTR_40
+    4'b 0011, // index[312] PINMUX_MIO_PAD_ATTR_41
+    4'b 0011, // index[313] PINMUX_MIO_PAD_ATTR_42
+    4'b 0011, // index[314] PINMUX_MIO_PAD_ATTR_43
+    4'b 0011, // index[315] PINMUX_MIO_PAD_ATTR_44
+    4'b 0011, // index[316] PINMUX_MIO_PAD_ATTR_45
+    4'b 0011, // index[317] PINMUX_MIO_PAD_ATTR_46
+    4'b 0001, // index[318] PINMUX_DIO_PAD_ATTR_REGWEN_0
+    4'b 0001, // index[319] PINMUX_DIO_PAD_ATTR_REGWEN_1
+    4'b 0001, // index[320] PINMUX_DIO_PAD_ATTR_REGWEN_2
+    4'b 0001, // index[321] PINMUX_DIO_PAD_ATTR_REGWEN_3
+    4'b 0001, // index[322] PINMUX_DIO_PAD_ATTR_REGWEN_4
+    4'b 0001, // index[323] PINMUX_DIO_PAD_ATTR_REGWEN_5
+    4'b 0001, // index[324] PINMUX_DIO_PAD_ATTR_REGWEN_6
+    4'b 0001, // index[325] PINMUX_DIO_PAD_ATTR_REGWEN_7
+    4'b 0001, // index[326] PINMUX_DIO_PAD_ATTR_REGWEN_8
+    4'b 0001, // index[327] PINMUX_DIO_PAD_ATTR_REGWEN_9
+    4'b 0001, // index[328] PINMUX_DIO_PAD_ATTR_REGWEN_10
+    4'b 0001, // index[329] PINMUX_DIO_PAD_ATTR_REGWEN_11
+    4'b 0001, // index[330] PINMUX_DIO_PAD_ATTR_REGWEN_12
+    4'b 0001, // index[331] PINMUX_DIO_PAD_ATTR_REGWEN_13
+    4'b 0001, // index[332] PINMUX_DIO_PAD_ATTR_REGWEN_14
+    4'b 0001, // index[333] PINMUX_DIO_PAD_ATTR_REGWEN_15
+    4'b 0001, // index[334] PINMUX_DIO_PAD_ATTR_REGWEN_16
+    4'b 0001, // index[335] PINMUX_DIO_PAD_ATTR_REGWEN_17
+    4'b 0001, // index[336] PINMUX_DIO_PAD_ATTR_REGWEN_18
+    4'b 0001, // index[337] PINMUX_DIO_PAD_ATTR_REGWEN_19
+    4'b 0001, // index[338] PINMUX_DIO_PAD_ATTR_REGWEN_20
+    4'b 0001, // index[339] PINMUX_DIO_PAD_ATTR_REGWEN_21
+    4'b 0001, // index[340] PINMUX_DIO_PAD_ATTR_REGWEN_22
+    4'b 0011, // index[341] PINMUX_DIO_PAD_ATTR_0
+    4'b 0011, // index[342] PINMUX_DIO_PAD_ATTR_1
+    4'b 0011, // index[343] PINMUX_DIO_PAD_ATTR_2
+    4'b 0011, // index[344] PINMUX_DIO_PAD_ATTR_3
+    4'b 0011, // index[345] PINMUX_DIO_PAD_ATTR_4
+    4'b 0011, // index[346] PINMUX_DIO_PAD_ATTR_5
+    4'b 0011, // index[347] PINMUX_DIO_PAD_ATTR_6
+    4'b 0011, // index[348] PINMUX_DIO_PAD_ATTR_7
+    4'b 0011, // index[349] PINMUX_DIO_PAD_ATTR_8
+    4'b 0011, // index[350] PINMUX_DIO_PAD_ATTR_9
+    4'b 0011, // index[351] PINMUX_DIO_PAD_ATTR_10
+    4'b 0011, // index[352] PINMUX_DIO_PAD_ATTR_11
+    4'b 0011, // index[353] PINMUX_DIO_PAD_ATTR_12
+    4'b 0011, // index[354] PINMUX_DIO_PAD_ATTR_13
+    4'b 0011, // index[355] PINMUX_DIO_PAD_ATTR_14
+    4'b 0011, // index[356] PINMUX_DIO_PAD_ATTR_15
+    4'b 0011, // index[357] PINMUX_DIO_PAD_ATTR_16
+    4'b 0011, // index[358] PINMUX_DIO_PAD_ATTR_17
+    4'b 0011, // index[359] PINMUX_DIO_PAD_ATTR_18
+    4'b 0011, // index[360] PINMUX_DIO_PAD_ATTR_19
+    4'b 0011, // index[361] PINMUX_DIO_PAD_ATTR_20
+    4'b 0011, // index[362] PINMUX_DIO_PAD_ATTR_21
+    4'b 0011, // index[363] PINMUX_DIO_PAD_ATTR_22
+    4'b 1111, // index[364] PINMUX_MIO_PAD_SLEEP_STATUS_0
+    4'b 0011, // index[365] PINMUX_MIO_PAD_SLEEP_STATUS_1
+    4'b 0001, // index[366] PINMUX_MIO_PAD_SLEEP_REGWEN_0
+    4'b 0001, // index[367] PINMUX_MIO_PAD_SLEEP_REGWEN_1
+    4'b 0001, // index[368] PINMUX_MIO_PAD_SLEEP_REGWEN_2
+    4'b 0001, // index[369] PINMUX_MIO_PAD_SLEEP_REGWEN_3
+    4'b 0001, // index[370] PINMUX_MIO_PAD_SLEEP_REGWEN_4
+    4'b 0001, // index[371] PINMUX_MIO_PAD_SLEEP_REGWEN_5
+    4'b 0001, // index[372] PINMUX_MIO_PAD_SLEEP_REGWEN_6
+    4'b 0001, // index[373] PINMUX_MIO_PAD_SLEEP_REGWEN_7
+    4'b 0001, // index[374] PINMUX_MIO_PAD_SLEEP_REGWEN_8
+    4'b 0001, // index[375] PINMUX_MIO_PAD_SLEEP_REGWEN_9
+    4'b 0001, // index[376] PINMUX_MIO_PAD_SLEEP_REGWEN_10
+    4'b 0001, // index[377] PINMUX_MIO_PAD_SLEEP_REGWEN_11
+    4'b 0001, // index[378] PINMUX_MIO_PAD_SLEEP_REGWEN_12
+    4'b 0001, // index[379] PINMUX_MIO_PAD_SLEEP_REGWEN_13
+    4'b 0001, // index[380] PINMUX_MIO_PAD_SLEEP_REGWEN_14
+    4'b 0001, // index[381] PINMUX_MIO_PAD_SLEEP_REGWEN_15
+    4'b 0001, // index[382] PINMUX_MIO_PAD_SLEEP_REGWEN_16
+    4'b 0001, // index[383] PINMUX_MIO_PAD_SLEEP_REGWEN_17
+    4'b 0001, // index[384] PINMUX_MIO_PAD_SLEEP_REGWEN_18
+    4'b 0001, // index[385] PINMUX_MIO_PAD_SLEEP_REGWEN_19
+    4'b 0001, // index[386] PINMUX_MIO_PAD_SLEEP_REGWEN_20
+    4'b 0001, // index[387] PINMUX_MIO_PAD_SLEEP_REGWEN_21
+    4'b 0001, // index[388] PINMUX_MIO_PAD_SLEEP_REGWEN_22
+    4'b 0001, // index[389] PINMUX_MIO_PAD_SLEEP_REGWEN_23
+    4'b 0001, // index[390] PINMUX_MIO_PAD_SLEEP_REGWEN_24
+    4'b 0001, // index[391] PINMUX_MIO_PAD_SLEEP_REGWEN_25
+    4'b 0001, // index[392] PINMUX_MIO_PAD_SLEEP_REGWEN_26
+    4'b 0001, // index[393] PINMUX_MIO_PAD_SLEEP_REGWEN_27
+    4'b 0001, // index[394] PINMUX_MIO_PAD_SLEEP_REGWEN_28
+    4'b 0001, // index[395] PINMUX_MIO_PAD_SLEEP_REGWEN_29
+    4'b 0001, // index[396] PINMUX_MIO_PAD_SLEEP_REGWEN_30
+    4'b 0001, // index[397] PINMUX_MIO_PAD_SLEEP_REGWEN_31
+    4'b 0001, // index[398] PINMUX_MIO_PAD_SLEEP_REGWEN_32
+    4'b 0001, // index[399] PINMUX_MIO_PAD_SLEEP_REGWEN_33
+    4'b 0001, // index[400] PINMUX_MIO_PAD_SLEEP_REGWEN_34
+    4'b 0001, // index[401] PINMUX_MIO_PAD_SLEEP_REGWEN_35
+    4'b 0001, // index[402] PINMUX_MIO_PAD_SLEEP_REGWEN_36
+    4'b 0001, // index[403] PINMUX_MIO_PAD_SLEEP_REGWEN_37
+    4'b 0001, // index[404] PINMUX_MIO_PAD_SLEEP_REGWEN_38
+    4'b 0001, // index[405] PINMUX_MIO_PAD_SLEEP_REGWEN_39
+    4'b 0001, // index[406] PINMUX_MIO_PAD_SLEEP_REGWEN_40
+    4'b 0001, // index[407] PINMUX_MIO_PAD_SLEEP_REGWEN_41
+    4'b 0001, // index[408] PINMUX_MIO_PAD_SLEEP_REGWEN_42
+    4'b 0001, // index[409] PINMUX_MIO_PAD_SLEEP_REGWEN_43
+    4'b 0001, // index[410] PINMUX_MIO_PAD_SLEEP_REGWEN_44
+    4'b 0001, // index[411] PINMUX_MIO_PAD_SLEEP_REGWEN_45
+    4'b 0001, // index[412] PINMUX_MIO_PAD_SLEEP_REGWEN_46
+    4'b 0001, // index[413] PINMUX_MIO_PAD_SLEEP_EN_0
+    4'b 0001, // index[414] PINMUX_MIO_PAD_SLEEP_EN_1
+    4'b 0001, // index[415] PINMUX_MIO_PAD_SLEEP_EN_2
+    4'b 0001, // index[416] PINMUX_MIO_PAD_SLEEP_EN_3
+    4'b 0001, // index[417] PINMUX_MIO_PAD_SLEEP_EN_4
+    4'b 0001, // index[418] PINMUX_MIO_PAD_SLEEP_EN_5
+    4'b 0001, // index[419] PINMUX_MIO_PAD_SLEEP_EN_6
+    4'b 0001, // index[420] PINMUX_MIO_PAD_SLEEP_EN_7
+    4'b 0001, // index[421] PINMUX_MIO_PAD_SLEEP_EN_8
+    4'b 0001, // index[422] PINMUX_MIO_PAD_SLEEP_EN_9
+    4'b 0001, // index[423] PINMUX_MIO_PAD_SLEEP_EN_10
+    4'b 0001, // index[424] PINMUX_MIO_PAD_SLEEP_EN_11
+    4'b 0001, // index[425] PINMUX_MIO_PAD_SLEEP_EN_12
+    4'b 0001, // index[426] PINMUX_MIO_PAD_SLEEP_EN_13
+    4'b 0001, // index[427] PINMUX_MIO_PAD_SLEEP_EN_14
+    4'b 0001, // index[428] PINMUX_MIO_PAD_SLEEP_EN_15
+    4'b 0001, // index[429] PINMUX_MIO_PAD_SLEEP_EN_16
+    4'b 0001, // index[430] PINMUX_MIO_PAD_SLEEP_EN_17
+    4'b 0001, // index[431] PINMUX_MIO_PAD_SLEEP_EN_18
+    4'b 0001, // index[432] PINMUX_MIO_PAD_SLEEP_EN_19
+    4'b 0001, // index[433] PINMUX_MIO_PAD_SLEEP_EN_20
+    4'b 0001, // index[434] PINMUX_MIO_PAD_SLEEP_EN_21
+    4'b 0001, // index[435] PINMUX_MIO_PAD_SLEEP_EN_22
+    4'b 0001, // index[436] PINMUX_MIO_PAD_SLEEP_EN_23
+    4'b 0001, // index[437] PINMUX_MIO_PAD_SLEEP_EN_24
+    4'b 0001, // index[438] PINMUX_MIO_PAD_SLEEP_EN_25
+    4'b 0001, // index[439] PINMUX_MIO_PAD_SLEEP_EN_26
+    4'b 0001, // index[440] PINMUX_MIO_PAD_SLEEP_EN_27
+    4'b 0001, // index[441] PINMUX_MIO_PAD_SLEEP_EN_28
+    4'b 0001, // index[442] PINMUX_MIO_PAD_SLEEP_EN_29
+    4'b 0001, // index[443] PINMUX_MIO_PAD_SLEEP_EN_30
+    4'b 0001, // index[444] PINMUX_MIO_PAD_SLEEP_EN_31
+    4'b 0001, // index[445] PINMUX_MIO_PAD_SLEEP_EN_32
+    4'b 0001, // index[446] PINMUX_MIO_PAD_SLEEP_EN_33
+    4'b 0001, // index[447] PINMUX_MIO_PAD_SLEEP_EN_34
+    4'b 0001, // index[448] PINMUX_MIO_PAD_SLEEP_EN_35
+    4'b 0001, // index[449] PINMUX_MIO_PAD_SLEEP_EN_36
+    4'b 0001, // index[450] PINMUX_MIO_PAD_SLEEP_EN_37
+    4'b 0001, // index[451] PINMUX_MIO_PAD_SLEEP_EN_38
+    4'b 0001, // index[452] PINMUX_MIO_PAD_SLEEP_EN_39
+    4'b 0001, // index[453] PINMUX_MIO_PAD_SLEEP_EN_40
+    4'b 0001, // index[454] PINMUX_MIO_PAD_SLEEP_EN_41
+    4'b 0001, // index[455] PINMUX_MIO_PAD_SLEEP_EN_42
+    4'b 0001, // index[456] PINMUX_MIO_PAD_SLEEP_EN_43
+    4'b 0001, // index[457] PINMUX_MIO_PAD_SLEEP_EN_44
+    4'b 0001, // index[458] PINMUX_MIO_PAD_SLEEP_EN_45
+    4'b 0001, // index[459] PINMUX_MIO_PAD_SLEEP_EN_46
+    4'b 0001, // index[460] PINMUX_MIO_PAD_SLEEP_MODE_0
+    4'b 0001, // index[461] PINMUX_MIO_PAD_SLEEP_MODE_1
+    4'b 0001, // index[462] PINMUX_MIO_PAD_SLEEP_MODE_2
+    4'b 0001, // index[463] PINMUX_MIO_PAD_SLEEP_MODE_3
+    4'b 0001, // index[464] PINMUX_MIO_PAD_SLEEP_MODE_4
+    4'b 0001, // index[465] PINMUX_MIO_PAD_SLEEP_MODE_5
+    4'b 0001, // index[466] PINMUX_MIO_PAD_SLEEP_MODE_6
+    4'b 0001, // index[467] PINMUX_MIO_PAD_SLEEP_MODE_7
+    4'b 0001, // index[468] PINMUX_MIO_PAD_SLEEP_MODE_8
+    4'b 0001, // index[469] PINMUX_MIO_PAD_SLEEP_MODE_9
+    4'b 0001, // index[470] PINMUX_MIO_PAD_SLEEP_MODE_10
+    4'b 0001, // index[471] PINMUX_MIO_PAD_SLEEP_MODE_11
+    4'b 0001, // index[472] PINMUX_MIO_PAD_SLEEP_MODE_12
+    4'b 0001, // index[473] PINMUX_MIO_PAD_SLEEP_MODE_13
+    4'b 0001, // index[474] PINMUX_MIO_PAD_SLEEP_MODE_14
+    4'b 0001, // index[475] PINMUX_MIO_PAD_SLEEP_MODE_15
+    4'b 0001, // index[476] PINMUX_MIO_PAD_SLEEP_MODE_16
+    4'b 0001, // index[477] PINMUX_MIO_PAD_SLEEP_MODE_17
+    4'b 0001, // index[478] PINMUX_MIO_PAD_SLEEP_MODE_18
+    4'b 0001, // index[479] PINMUX_MIO_PAD_SLEEP_MODE_19
+    4'b 0001, // index[480] PINMUX_MIO_PAD_SLEEP_MODE_20
+    4'b 0001, // index[481] PINMUX_MIO_PAD_SLEEP_MODE_21
+    4'b 0001, // index[482] PINMUX_MIO_PAD_SLEEP_MODE_22
+    4'b 0001, // index[483] PINMUX_MIO_PAD_SLEEP_MODE_23
+    4'b 0001, // index[484] PINMUX_MIO_PAD_SLEEP_MODE_24
+    4'b 0001, // index[485] PINMUX_MIO_PAD_SLEEP_MODE_25
+    4'b 0001, // index[486] PINMUX_MIO_PAD_SLEEP_MODE_26
+    4'b 0001, // index[487] PINMUX_MIO_PAD_SLEEP_MODE_27
+    4'b 0001, // index[488] PINMUX_MIO_PAD_SLEEP_MODE_28
+    4'b 0001, // index[489] PINMUX_MIO_PAD_SLEEP_MODE_29
+    4'b 0001, // index[490] PINMUX_MIO_PAD_SLEEP_MODE_30
+    4'b 0001, // index[491] PINMUX_MIO_PAD_SLEEP_MODE_31
+    4'b 0001, // index[492] PINMUX_MIO_PAD_SLEEP_MODE_32
+    4'b 0001, // index[493] PINMUX_MIO_PAD_SLEEP_MODE_33
+    4'b 0001, // index[494] PINMUX_MIO_PAD_SLEEP_MODE_34
+    4'b 0001, // index[495] PINMUX_MIO_PAD_SLEEP_MODE_35
+    4'b 0001, // index[496] PINMUX_MIO_PAD_SLEEP_MODE_36
+    4'b 0001, // index[497] PINMUX_MIO_PAD_SLEEP_MODE_37
+    4'b 0001, // index[498] PINMUX_MIO_PAD_SLEEP_MODE_38
+    4'b 0001, // index[499] PINMUX_MIO_PAD_SLEEP_MODE_39
+    4'b 0001, // index[500] PINMUX_MIO_PAD_SLEEP_MODE_40
+    4'b 0001, // index[501] PINMUX_MIO_PAD_SLEEP_MODE_41
+    4'b 0001, // index[502] PINMUX_MIO_PAD_SLEEP_MODE_42
+    4'b 0001, // index[503] PINMUX_MIO_PAD_SLEEP_MODE_43
+    4'b 0001, // index[504] PINMUX_MIO_PAD_SLEEP_MODE_44
+    4'b 0001, // index[505] PINMUX_MIO_PAD_SLEEP_MODE_45
+    4'b 0001, // index[506] PINMUX_MIO_PAD_SLEEP_MODE_46
+    4'b 0111, // index[507] PINMUX_DIO_PAD_SLEEP_STATUS
+    4'b 0001, // index[508] PINMUX_DIO_PAD_SLEEP_REGWEN_0
+    4'b 0001, // index[509] PINMUX_DIO_PAD_SLEEP_REGWEN_1
+    4'b 0001, // index[510] PINMUX_DIO_PAD_SLEEP_REGWEN_2
+    4'b 0001, // index[511] PINMUX_DIO_PAD_SLEEP_REGWEN_3
+    4'b 0001, // index[512] PINMUX_DIO_PAD_SLEEP_REGWEN_4
+    4'b 0001, // index[513] PINMUX_DIO_PAD_SLEEP_REGWEN_5
+    4'b 0001, // index[514] PINMUX_DIO_PAD_SLEEP_REGWEN_6
+    4'b 0001, // index[515] PINMUX_DIO_PAD_SLEEP_REGWEN_7
+    4'b 0001, // index[516] PINMUX_DIO_PAD_SLEEP_REGWEN_8
+    4'b 0001, // index[517] PINMUX_DIO_PAD_SLEEP_REGWEN_9
+    4'b 0001, // index[518] PINMUX_DIO_PAD_SLEEP_REGWEN_10
+    4'b 0001, // index[519] PINMUX_DIO_PAD_SLEEP_REGWEN_11
+    4'b 0001, // index[520] PINMUX_DIO_PAD_SLEEP_REGWEN_12
+    4'b 0001, // index[521] PINMUX_DIO_PAD_SLEEP_REGWEN_13
+    4'b 0001, // index[522] PINMUX_DIO_PAD_SLEEP_REGWEN_14
+    4'b 0001, // index[523] PINMUX_DIO_PAD_SLEEP_REGWEN_15
+    4'b 0001, // index[524] PINMUX_DIO_PAD_SLEEP_REGWEN_16
+    4'b 0001, // index[525] PINMUX_DIO_PAD_SLEEP_REGWEN_17
+    4'b 0001, // index[526] PINMUX_DIO_PAD_SLEEP_REGWEN_18
+    4'b 0001, // index[527] PINMUX_DIO_PAD_SLEEP_REGWEN_19
+    4'b 0001, // index[528] PINMUX_DIO_PAD_SLEEP_REGWEN_20
+    4'b 0001, // index[529] PINMUX_DIO_PAD_SLEEP_REGWEN_21
+    4'b 0001, // index[530] PINMUX_DIO_PAD_SLEEP_REGWEN_22
+    4'b 0001, // index[531] PINMUX_DIO_PAD_SLEEP_EN_0
+    4'b 0001, // index[532] PINMUX_DIO_PAD_SLEEP_EN_1
+    4'b 0001, // index[533] PINMUX_DIO_PAD_SLEEP_EN_2
+    4'b 0001, // index[534] PINMUX_DIO_PAD_SLEEP_EN_3
+    4'b 0001, // index[535] PINMUX_DIO_PAD_SLEEP_EN_4
+    4'b 0001, // index[536] PINMUX_DIO_PAD_SLEEP_EN_5
+    4'b 0001, // index[537] PINMUX_DIO_PAD_SLEEP_EN_6
+    4'b 0001, // index[538] PINMUX_DIO_PAD_SLEEP_EN_7
+    4'b 0001, // index[539] PINMUX_DIO_PAD_SLEEP_EN_8
+    4'b 0001, // index[540] PINMUX_DIO_PAD_SLEEP_EN_9
+    4'b 0001, // index[541] PINMUX_DIO_PAD_SLEEP_EN_10
+    4'b 0001, // index[542] PINMUX_DIO_PAD_SLEEP_EN_11
+    4'b 0001, // index[543] PINMUX_DIO_PAD_SLEEP_EN_12
+    4'b 0001, // index[544] PINMUX_DIO_PAD_SLEEP_EN_13
+    4'b 0001, // index[545] PINMUX_DIO_PAD_SLEEP_EN_14
+    4'b 0001, // index[546] PINMUX_DIO_PAD_SLEEP_EN_15
+    4'b 0001, // index[547] PINMUX_DIO_PAD_SLEEP_EN_16
+    4'b 0001, // index[548] PINMUX_DIO_PAD_SLEEP_EN_17
+    4'b 0001, // index[549] PINMUX_DIO_PAD_SLEEP_EN_18
+    4'b 0001, // index[550] PINMUX_DIO_PAD_SLEEP_EN_19
+    4'b 0001, // index[551] PINMUX_DIO_PAD_SLEEP_EN_20
+    4'b 0001, // index[552] PINMUX_DIO_PAD_SLEEP_EN_21
+    4'b 0001, // index[553] PINMUX_DIO_PAD_SLEEP_EN_22
+    4'b 0001, // index[554] PINMUX_DIO_PAD_SLEEP_MODE_0
+    4'b 0001, // index[555] PINMUX_DIO_PAD_SLEEP_MODE_1
+    4'b 0001, // index[556] PINMUX_DIO_PAD_SLEEP_MODE_2
+    4'b 0001, // index[557] PINMUX_DIO_PAD_SLEEP_MODE_3
+    4'b 0001, // index[558] PINMUX_DIO_PAD_SLEEP_MODE_4
+    4'b 0001, // index[559] PINMUX_DIO_PAD_SLEEP_MODE_5
+    4'b 0001, // index[560] PINMUX_DIO_PAD_SLEEP_MODE_6
+    4'b 0001, // index[561] PINMUX_DIO_PAD_SLEEP_MODE_7
+    4'b 0001, // index[562] PINMUX_DIO_PAD_SLEEP_MODE_8
+    4'b 0001, // index[563] PINMUX_DIO_PAD_SLEEP_MODE_9
+    4'b 0001, // index[564] PINMUX_DIO_PAD_SLEEP_MODE_10
+    4'b 0001, // index[565] PINMUX_DIO_PAD_SLEEP_MODE_11
+    4'b 0001, // index[566] PINMUX_DIO_PAD_SLEEP_MODE_12
+    4'b 0001, // index[567] PINMUX_DIO_PAD_SLEEP_MODE_13
+    4'b 0001, // index[568] PINMUX_DIO_PAD_SLEEP_MODE_14
+    4'b 0001, // index[569] PINMUX_DIO_PAD_SLEEP_MODE_15
+    4'b 0001, // index[570] PINMUX_DIO_PAD_SLEEP_MODE_16
+    4'b 0001, // index[571] PINMUX_DIO_PAD_SLEEP_MODE_17
+    4'b 0001, // index[572] PINMUX_DIO_PAD_SLEEP_MODE_18
+    4'b 0001, // index[573] PINMUX_DIO_PAD_SLEEP_MODE_19
+    4'b 0001, // index[574] PINMUX_DIO_PAD_SLEEP_MODE_20
+    4'b 0001, // index[575] PINMUX_DIO_PAD_SLEEP_MODE_21
+    4'b 0001, // index[576] PINMUX_DIO_PAD_SLEEP_MODE_22
+    4'b 0001, // index[577] PINMUX_WKUP_DETECTOR_REGWEN_0
+    4'b 0001, // index[578] PINMUX_WKUP_DETECTOR_REGWEN_1
+    4'b 0001, // index[579] PINMUX_WKUP_DETECTOR_REGWEN_2
+    4'b 0001, // index[580] PINMUX_WKUP_DETECTOR_REGWEN_3
+    4'b 0001, // index[581] PINMUX_WKUP_DETECTOR_REGWEN_4
+    4'b 0001, // index[582] PINMUX_WKUP_DETECTOR_REGWEN_5
+    4'b 0001, // index[583] PINMUX_WKUP_DETECTOR_REGWEN_6
+    4'b 0001, // index[584] PINMUX_WKUP_DETECTOR_REGWEN_7
+    4'b 0001, // index[585] PINMUX_WKUP_DETECTOR_EN_0
+    4'b 0001, // index[586] PINMUX_WKUP_DETECTOR_EN_1
+    4'b 0001, // index[587] PINMUX_WKUP_DETECTOR_EN_2
+    4'b 0001, // index[588] PINMUX_WKUP_DETECTOR_EN_3
+    4'b 0001, // index[589] PINMUX_WKUP_DETECTOR_EN_4
+    4'b 0001, // index[590] PINMUX_WKUP_DETECTOR_EN_5
+    4'b 0001, // index[591] PINMUX_WKUP_DETECTOR_EN_6
+    4'b 0001, // index[592] PINMUX_WKUP_DETECTOR_EN_7
+    4'b 0001, // index[593] PINMUX_WKUP_DETECTOR_0
+    4'b 0001, // index[594] PINMUX_WKUP_DETECTOR_1
+    4'b 0001, // index[595] PINMUX_WKUP_DETECTOR_2
+    4'b 0001, // index[596] PINMUX_WKUP_DETECTOR_3
+    4'b 0001, // index[597] PINMUX_WKUP_DETECTOR_4
+    4'b 0001, // index[598] PINMUX_WKUP_DETECTOR_5
+    4'b 0001, // index[599] PINMUX_WKUP_DETECTOR_6
+    4'b 0001, // index[600] PINMUX_WKUP_DETECTOR_7
+    4'b 0001, // index[601] PINMUX_WKUP_DETECTOR_CNT_TH_0
+    4'b 0001, // index[602] PINMUX_WKUP_DETECTOR_CNT_TH_1
+    4'b 0001, // index[603] PINMUX_WKUP_DETECTOR_CNT_TH_2
+    4'b 0001, // index[604] PINMUX_WKUP_DETECTOR_CNT_TH_3
+    4'b 0001, // index[605] PINMUX_WKUP_DETECTOR_CNT_TH_4
+    4'b 0001, // index[606] PINMUX_WKUP_DETECTOR_CNT_TH_5
+    4'b 0001, // index[607] PINMUX_WKUP_DETECTOR_CNT_TH_6
+    4'b 0001, // index[608] PINMUX_WKUP_DETECTOR_CNT_TH_7
+    4'b 0001, // index[609] PINMUX_WKUP_DETECTOR_PADSEL_0
+    4'b 0001, // index[610] PINMUX_WKUP_DETECTOR_PADSEL_1
+    4'b 0001, // index[611] PINMUX_WKUP_DETECTOR_PADSEL_2
+    4'b 0001, // index[612] PINMUX_WKUP_DETECTOR_PADSEL_3
+    4'b 0001, // index[613] PINMUX_WKUP_DETECTOR_PADSEL_4
+    4'b 0001, // index[614] PINMUX_WKUP_DETECTOR_PADSEL_5
+    4'b 0001, // index[615] PINMUX_WKUP_DETECTOR_PADSEL_6
+    4'b 0001, // index[616] PINMUX_WKUP_DETECTOR_PADSEL_7
+    4'b 0001  // index[617] PINMUX_WKUP_CAUSE
   };
 
 endpackage
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
index c206e42..2773ffa 100644
--- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
+++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
@@ -623,6 +623,18 @@
   logic mio_outsel_regwen_42_qs;
   logic mio_outsel_regwen_42_wd;
   logic mio_outsel_regwen_42_we;
+  logic mio_outsel_regwen_43_qs;
+  logic mio_outsel_regwen_43_wd;
+  logic mio_outsel_regwen_43_we;
+  logic mio_outsel_regwen_44_qs;
+  logic mio_outsel_regwen_44_wd;
+  logic mio_outsel_regwen_44_we;
+  logic mio_outsel_regwen_45_qs;
+  logic mio_outsel_regwen_45_wd;
+  logic mio_outsel_regwen_45_we;
+  logic mio_outsel_regwen_46_qs;
+  logic mio_outsel_regwen_46_wd;
+  logic mio_outsel_regwen_46_we;
   logic [6:0] mio_outsel_0_qs;
   logic [6:0] mio_outsel_0_wd;
   logic mio_outsel_0_we;
@@ -752,6 +764,18 @@
   logic [6:0] mio_outsel_42_qs;
   logic [6:0] mio_outsel_42_wd;
   logic mio_outsel_42_we;
+  logic [6:0] mio_outsel_43_qs;
+  logic [6:0] mio_outsel_43_wd;
+  logic mio_outsel_43_we;
+  logic [6:0] mio_outsel_44_qs;
+  logic [6:0] mio_outsel_44_wd;
+  logic mio_outsel_44_we;
+  logic [6:0] mio_outsel_45_qs;
+  logic [6:0] mio_outsel_45_wd;
+  logic mio_outsel_45_we;
+  logic [6:0] mio_outsel_46_qs;
+  logic [6:0] mio_outsel_46_wd;
+  logic mio_outsel_46_we;
   logic mio_pad_attr_regwen_0_qs;
   logic mio_pad_attr_regwen_0_wd;
   logic mio_pad_attr_regwen_0_we;
@@ -881,6 +905,18 @@
   logic mio_pad_attr_regwen_42_qs;
   logic mio_pad_attr_regwen_42_wd;
   logic mio_pad_attr_regwen_42_we;
+  logic mio_pad_attr_regwen_43_qs;
+  logic mio_pad_attr_regwen_43_wd;
+  logic mio_pad_attr_regwen_43_we;
+  logic mio_pad_attr_regwen_44_qs;
+  logic mio_pad_attr_regwen_44_wd;
+  logic mio_pad_attr_regwen_44_we;
+  logic mio_pad_attr_regwen_45_qs;
+  logic mio_pad_attr_regwen_45_wd;
+  logic mio_pad_attr_regwen_45_we;
+  logic mio_pad_attr_regwen_46_qs;
+  logic mio_pad_attr_regwen_46_wd;
+  logic mio_pad_attr_regwen_46_we;
   logic [12:0] mio_pad_attr_0_qs;
   logic [12:0] mio_pad_attr_0_wd;
   logic mio_pad_attr_0_we;
@@ -1053,6 +1089,22 @@
   logic [12:0] mio_pad_attr_42_wd;
   logic mio_pad_attr_42_we;
   logic mio_pad_attr_42_re;
+  logic [12:0] mio_pad_attr_43_qs;
+  logic [12:0] mio_pad_attr_43_wd;
+  logic mio_pad_attr_43_we;
+  logic mio_pad_attr_43_re;
+  logic [12:0] mio_pad_attr_44_qs;
+  logic [12:0] mio_pad_attr_44_wd;
+  logic mio_pad_attr_44_we;
+  logic mio_pad_attr_44_re;
+  logic [12:0] mio_pad_attr_45_qs;
+  logic [12:0] mio_pad_attr_45_wd;
+  logic mio_pad_attr_45_we;
+  logic mio_pad_attr_45_re;
+  logic [12:0] mio_pad_attr_46_qs;
+  logic [12:0] mio_pad_attr_46_wd;
+  logic mio_pad_attr_46_we;
+  logic mio_pad_attr_46_re;
   logic dio_pad_attr_regwen_0_qs;
   logic dio_pad_attr_regwen_0_wd;
   logic dio_pad_attr_regwen_0_we;
@@ -1119,6 +1171,9 @@
   logic dio_pad_attr_regwen_21_qs;
   logic dio_pad_attr_regwen_21_wd;
   logic dio_pad_attr_regwen_21_we;
+  logic dio_pad_attr_regwen_22_qs;
+  logic dio_pad_attr_regwen_22_wd;
+  logic dio_pad_attr_regwen_22_we;
   logic [12:0] dio_pad_attr_0_qs;
   logic [12:0] dio_pad_attr_0_wd;
   logic dio_pad_attr_0_we;
@@ -1207,6 +1262,10 @@
   logic [12:0] dio_pad_attr_21_wd;
   logic dio_pad_attr_21_we;
   logic dio_pad_attr_21_re;
+  logic [12:0] dio_pad_attr_22_qs;
+  logic [12:0] dio_pad_attr_22_wd;
+  logic dio_pad_attr_22_we;
+  logic dio_pad_attr_22_re;
   logic mio_pad_sleep_status_0_en_0_qs;
   logic mio_pad_sleep_status_0_en_0_wd;
   logic mio_pad_sleep_status_0_en_0_we;
@@ -1336,6 +1395,18 @@
   logic mio_pad_sleep_status_1_en_42_qs;
   logic mio_pad_sleep_status_1_en_42_wd;
   logic mio_pad_sleep_status_1_en_42_we;
+  logic mio_pad_sleep_status_1_en_43_qs;
+  logic mio_pad_sleep_status_1_en_43_wd;
+  logic mio_pad_sleep_status_1_en_43_we;
+  logic mio_pad_sleep_status_1_en_44_qs;
+  logic mio_pad_sleep_status_1_en_44_wd;
+  logic mio_pad_sleep_status_1_en_44_we;
+  logic mio_pad_sleep_status_1_en_45_qs;
+  logic mio_pad_sleep_status_1_en_45_wd;
+  logic mio_pad_sleep_status_1_en_45_we;
+  logic mio_pad_sleep_status_1_en_46_qs;
+  logic mio_pad_sleep_status_1_en_46_wd;
+  logic mio_pad_sleep_status_1_en_46_we;
   logic mio_pad_sleep_regwen_0_qs;
   logic mio_pad_sleep_regwen_0_wd;
   logic mio_pad_sleep_regwen_0_we;
@@ -1465,6 +1536,18 @@
   logic mio_pad_sleep_regwen_42_qs;
   logic mio_pad_sleep_regwen_42_wd;
   logic mio_pad_sleep_regwen_42_we;
+  logic mio_pad_sleep_regwen_43_qs;
+  logic mio_pad_sleep_regwen_43_wd;
+  logic mio_pad_sleep_regwen_43_we;
+  logic mio_pad_sleep_regwen_44_qs;
+  logic mio_pad_sleep_regwen_44_wd;
+  logic mio_pad_sleep_regwen_44_we;
+  logic mio_pad_sleep_regwen_45_qs;
+  logic mio_pad_sleep_regwen_45_wd;
+  logic mio_pad_sleep_regwen_45_we;
+  logic mio_pad_sleep_regwen_46_qs;
+  logic mio_pad_sleep_regwen_46_wd;
+  logic mio_pad_sleep_regwen_46_we;
   logic mio_pad_sleep_en_0_qs;
   logic mio_pad_sleep_en_0_wd;
   logic mio_pad_sleep_en_0_we;
@@ -1594,6 +1677,18 @@
   logic mio_pad_sleep_en_42_qs;
   logic mio_pad_sleep_en_42_wd;
   logic mio_pad_sleep_en_42_we;
+  logic mio_pad_sleep_en_43_qs;
+  logic mio_pad_sleep_en_43_wd;
+  logic mio_pad_sleep_en_43_we;
+  logic mio_pad_sleep_en_44_qs;
+  logic mio_pad_sleep_en_44_wd;
+  logic mio_pad_sleep_en_44_we;
+  logic mio_pad_sleep_en_45_qs;
+  logic mio_pad_sleep_en_45_wd;
+  logic mio_pad_sleep_en_45_we;
+  logic mio_pad_sleep_en_46_qs;
+  logic mio_pad_sleep_en_46_wd;
+  logic mio_pad_sleep_en_46_we;
   logic [1:0] mio_pad_sleep_mode_0_qs;
   logic [1:0] mio_pad_sleep_mode_0_wd;
   logic mio_pad_sleep_mode_0_we;
@@ -1723,6 +1818,18 @@
   logic [1:0] mio_pad_sleep_mode_42_qs;
   logic [1:0] mio_pad_sleep_mode_42_wd;
   logic mio_pad_sleep_mode_42_we;
+  logic [1:0] mio_pad_sleep_mode_43_qs;
+  logic [1:0] mio_pad_sleep_mode_43_wd;
+  logic mio_pad_sleep_mode_43_we;
+  logic [1:0] mio_pad_sleep_mode_44_qs;
+  logic [1:0] mio_pad_sleep_mode_44_wd;
+  logic mio_pad_sleep_mode_44_we;
+  logic [1:0] mio_pad_sleep_mode_45_qs;
+  logic [1:0] mio_pad_sleep_mode_45_wd;
+  logic mio_pad_sleep_mode_45_we;
+  logic [1:0] mio_pad_sleep_mode_46_qs;
+  logic [1:0] mio_pad_sleep_mode_46_wd;
+  logic mio_pad_sleep_mode_46_we;
   logic dio_pad_sleep_status_en_0_qs;
   logic dio_pad_sleep_status_en_0_wd;
   logic dio_pad_sleep_status_en_0_we;
@@ -1789,6 +1896,9 @@
   logic dio_pad_sleep_status_en_21_qs;
   logic dio_pad_sleep_status_en_21_wd;
   logic dio_pad_sleep_status_en_21_we;
+  logic dio_pad_sleep_status_en_22_qs;
+  logic dio_pad_sleep_status_en_22_wd;
+  logic dio_pad_sleep_status_en_22_we;
   logic dio_pad_sleep_regwen_0_qs;
   logic dio_pad_sleep_regwen_0_wd;
   logic dio_pad_sleep_regwen_0_we;
@@ -1855,6 +1965,9 @@
   logic dio_pad_sleep_regwen_21_qs;
   logic dio_pad_sleep_regwen_21_wd;
   logic dio_pad_sleep_regwen_21_we;
+  logic dio_pad_sleep_regwen_22_qs;
+  logic dio_pad_sleep_regwen_22_wd;
+  logic dio_pad_sleep_regwen_22_we;
   logic dio_pad_sleep_en_0_qs;
   logic dio_pad_sleep_en_0_wd;
   logic dio_pad_sleep_en_0_we;
@@ -1921,6 +2034,9 @@
   logic dio_pad_sleep_en_21_qs;
   logic dio_pad_sleep_en_21_wd;
   logic dio_pad_sleep_en_21_we;
+  logic dio_pad_sleep_en_22_qs;
+  logic dio_pad_sleep_en_22_wd;
+  logic dio_pad_sleep_en_22_we;
   logic [1:0] dio_pad_sleep_mode_0_qs;
   logic [1:0] dio_pad_sleep_mode_0_wd;
   logic dio_pad_sleep_mode_0_we;
@@ -1987,6 +2103,9 @@
   logic [1:0] dio_pad_sleep_mode_21_qs;
   logic [1:0] dio_pad_sleep_mode_21_wd;
   logic dio_pad_sleep_mode_21_we;
+  logic [1:0] dio_pad_sleep_mode_22_qs;
+  logic [1:0] dio_pad_sleep_mode_22_wd;
+  logic dio_pad_sleep_mode_22_we;
   logic wkup_detector_regwen_0_qs;
   logic wkup_detector_regwen_0_wd;
   logic wkup_detector_regwen_0_we;
@@ -6865,6 +6984,114 @@
     .qs     (mio_outsel_regwen_42_qs)
   );
 
+  // Subregister 43 of Multireg mio_outsel_regwen
+  // R[mio_outsel_regwen_43]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_outsel_regwen_43 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_outsel_regwen_43_we),
+    .wd     (mio_outsel_regwen_43_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_outsel_regwen_43_qs)
+  );
+
+  // Subregister 44 of Multireg mio_outsel_regwen
+  // R[mio_outsel_regwen_44]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_outsel_regwen_44 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_outsel_regwen_44_we),
+    .wd     (mio_outsel_regwen_44_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_outsel_regwen_44_qs)
+  );
+
+  // Subregister 45 of Multireg mio_outsel_regwen
+  // R[mio_outsel_regwen_45]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_outsel_regwen_45 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_outsel_regwen_45_we),
+    .wd     (mio_outsel_regwen_45_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_outsel_regwen_45_qs)
+  );
+
+  // Subregister 46 of Multireg mio_outsel_regwen
+  // R[mio_outsel_regwen_46]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_outsel_regwen_46 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_outsel_regwen_46_we),
+    .wd     (mio_outsel_regwen_46_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_outsel_regwen_46_qs)
+  );
+
 
 
   // Subregister 0 of Multireg mio_outsel
@@ -8028,6 +8255,114 @@
     .qs     (mio_outsel_42_qs)
   );
 
+  // Subregister 43 of Multireg mio_outsel
+  // R[mio_outsel_43]: V(False)
+
+  prim_subreg #(
+    .DW      (7),
+    .SWACCESS("RW"),
+    .RESVAL  (7'h2)
+  ) u_mio_outsel_43 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_outsel_43_we & mio_outsel_regwen_43_qs),
+    .wd     (mio_outsel_43_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_outsel[43].q ),
+
+    // to register interface (read)
+    .qs     (mio_outsel_43_qs)
+  );
+
+  // Subregister 44 of Multireg mio_outsel
+  // R[mio_outsel_44]: V(False)
+
+  prim_subreg #(
+    .DW      (7),
+    .SWACCESS("RW"),
+    .RESVAL  (7'h2)
+  ) u_mio_outsel_44 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_outsel_44_we & mio_outsel_regwen_44_qs),
+    .wd     (mio_outsel_44_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_outsel[44].q ),
+
+    // to register interface (read)
+    .qs     (mio_outsel_44_qs)
+  );
+
+  // Subregister 45 of Multireg mio_outsel
+  // R[mio_outsel_45]: V(False)
+
+  prim_subreg #(
+    .DW      (7),
+    .SWACCESS("RW"),
+    .RESVAL  (7'h2)
+  ) u_mio_outsel_45 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_outsel_45_we & mio_outsel_regwen_45_qs),
+    .wd     (mio_outsel_45_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_outsel[45].q ),
+
+    // to register interface (read)
+    .qs     (mio_outsel_45_qs)
+  );
+
+  // Subregister 46 of Multireg mio_outsel
+  // R[mio_outsel_46]: V(False)
+
+  prim_subreg #(
+    .DW      (7),
+    .SWACCESS("RW"),
+    .RESVAL  (7'h2)
+  ) u_mio_outsel_46 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_outsel_46_we & mio_outsel_regwen_46_qs),
+    .wd     (mio_outsel_46_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_outsel[46].q ),
+
+    // to register interface (read)
+    .qs     (mio_outsel_46_qs)
+  );
+
 
 
   // Subregister 0 of Multireg mio_pad_attr_regwen
@@ -9191,6 +9526,114 @@
     .qs     (mio_pad_attr_regwen_42_qs)
   );
 
+  // Subregister 43 of Multireg mio_pad_attr_regwen
+  // R[mio_pad_attr_regwen_43]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_pad_attr_regwen_43 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_pad_attr_regwen_43_we),
+    .wd     (mio_pad_attr_regwen_43_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_pad_attr_regwen_43_qs)
+  );
+
+  // Subregister 44 of Multireg mio_pad_attr_regwen
+  // R[mio_pad_attr_regwen_44]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_pad_attr_regwen_44 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_pad_attr_regwen_44_we),
+    .wd     (mio_pad_attr_regwen_44_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_pad_attr_regwen_44_qs)
+  );
+
+  // Subregister 45 of Multireg mio_pad_attr_regwen
+  // R[mio_pad_attr_regwen_45]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_pad_attr_regwen_45 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_pad_attr_regwen_45_we),
+    .wd     (mio_pad_attr_regwen_45_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_pad_attr_regwen_45_qs)
+  );
+
+  // Subregister 46 of Multireg mio_pad_attr_regwen
+  // R[mio_pad_attr_regwen_46]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_pad_attr_regwen_46 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_pad_attr_regwen_46_we),
+    .wd     (mio_pad_attr_regwen_46_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_pad_attr_regwen_46_qs)
+  );
+
 
 
   // Subregister 0 of Multireg mio_pad_attr
@@ -9924,6 +10367,74 @@
     .qs     (mio_pad_attr_42_qs)
   );
 
+  // Subregister 43 of Multireg mio_pad_attr
+  // R[mio_pad_attr_43]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (13)
+  ) u_mio_pad_attr_43 (
+    .re     (mio_pad_attr_43_re),
+    // qualified with register enable
+    .we     (mio_pad_attr_43_we & mio_pad_attr_regwen_43_qs),
+    .wd     (mio_pad_attr_43_wd),
+    .d      (hw2reg.mio_pad_attr[43].d),
+    .qre    (),
+    .qe     (reg2hw.mio_pad_attr[43].qe),
+    .q      (reg2hw.mio_pad_attr[43].q ),
+    .qs     (mio_pad_attr_43_qs)
+  );
+
+  // Subregister 44 of Multireg mio_pad_attr
+  // R[mio_pad_attr_44]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (13)
+  ) u_mio_pad_attr_44 (
+    .re     (mio_pad_attr_44_re),
+    // qualified with register enable
+    .we     (mio_pad_attr_44_we & mio_pad_attr_regwen_44_qs),
+    .wd     (mio_pad_attr_44_wd),
+    .d      (hw2reg.mio_pad_attr[44].d),
+    .qre    (),
+    .qe     (reg2hw.mio_pad_attr[44].qe),
+    .q      (reg2hw.mio_pad_attr[44].q ),
+    .qs     (mio_pad_attr_44_qs)
+  );
+
+  // Subregister 45 of Multireg mio_pad_attr
+  // R[mio_pad_attr_45]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (13)
+  ) u_mio_pad_attr_45 (
+    .re     (mio_pad_attr_45_re),
+    // qualified with register enable
+    .we     (mio_pad_attr_45_we & mio_pad_attr_regwen_45_qs),
+    .wd     (mio_pad_attr_45_wd),
+    .d      (hw2reg.mio_pad_attr[45].d),
+    .qre    (),
+    .qe     (reg2hw.mio_pad_attr[45].qe),
+    .q      (reg2hw.mio_pad_attr[45].q ),
+    .qs     (mio_pad_attr_45_qs)
+  );
+
+  // Subregister 46 of Multireg mio_pad_attr
+  // R[mio_pad_attr_46]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (13)
+  ) u_mio_pad_attr_46 (
+    .re     (mio_pad_attr_46_re),
+    // qualified with register enable
+    .we     (mio_pad_attr_46_we & mio_pad_attr_regwen_46_qs),
+    .wd     (mio_pad_attr_46_wd),
+    .d      (hw2reg.mio_pad_attr[46].d),
+    .qre    (),
+    .qe     (reg2hw.mio_pad_attr[46].qe),
+    .q      (reg2hw.mio_pad_attr[46].q ),
+    .qs     (mio_pad_attr_46_qs)
+  );
+
 
 
   // Subregister 0 of Multireg dio_pad_attr_regwen
@@ -10520,6 +11031,33 @@
     .qs     (dio_pad_attr_regwen_21_qs)
   );
 
+  // Subregister 22 of Multireg dio_pad_attr_regwen
+  // R[dio_pad_attr_regwen_22]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_dio_pad_attr_regwen_22 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_attr_regwen_22_we),
+    .wd     (dio_pad_attr_regwen_22_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (dio_pad_attr_regwen_22_qs)
+  );
+
 
 
   // Subregister 0 of Multireg dio_pad_attr
@@ -10896,6 +11434,23 @@
     .qs     (dio_pad_attr_21_qs)
   );
 
+  // Subregister 22 of Multireg dio_pad_attr
+  // R[dio_pad_attr_22]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (13)
+  ) u_dio_pad_attr_22 (
+    .re     (dio_pad_attr_22_re),
+    // qualified with register enable
+    .we     (dio_pad_attr_22_we & dio_pad_attr_regwen_22_qs),
+    .wd     (dio_pad_attr_22_wd),
+    .d      (hw2reg.dio_pad_attr[22].d),
+    .qre    (),
+    .qe     (reg2hw.dio_pad_attr[22].qe),
+    .q      (reg2hw.dio_pad_attr[22].q ),
+    .qs     (dio_pad_attr_22_qs)
+  );
+
 
 
   // Subregister 0 of Multireg mio_pad_sleep_status
@@ -12022,6 +12577,110 @@
   );
 
 
+  // F[en_43]: 11:11
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h0)
+  ) u_mio_pad_sleep_status_1_en_43 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_pad_sleep_status_1_en_43_we),
+    .wd     (mio_pad_sleep_status_1_en_43_wd),
+
+    // from internal hardware
+    .de     (hw2reg.mio_pad_sleep_status[43].de),
+    .d      (hw2reg.mio_pad_sleep_status[43].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_pad_sleep_status[43].q ),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_status_1_en_43_qs)
+  );
+
+
+  // F[en_44]: 12:12
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h0)
+  ) u_mio_pad_sleep_status_1_en_44 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_pad_sleep_status_1_en_44_we),
+    .wd     (mio_pad_sleep_status_1_en_44_wd),
+
+    // from internal hardware
+    .de     (hw2reg.mio_pad_sleep_status[44].de),
+    .d      (hw2reg.mio_pad_sleep_status[44].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_pad_sleep_status[44].q ),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_status_1_en_44_qs)
+  );
+
+
+  // F[en_45]: 13:13
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h0)
+  ) u_mio_pad_sleep_status_1_en_45 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_pad_sleep_status_1_en_45_we),
+    .wd     (mio_pad_sleep_status_1_en_45_wd),
+
+    // from internal hardware
+    .de     (hw2reg.mio_pad_sleep_status[45].de),
+    .d      (hw2reg.mio_pad_sleep_status[45].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_pad_sleep_status[45].q ),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_status_1_en_45_qs)
+  );
+
+
+  // F[en_46]: 14:14
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h0)
+  ) u_mio_pad_sleep_status_1_en_46 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_pad_sleep_status_1_en_46_we),
+    .wd     (mio_pad_sleep_status_1_en_46_wd),
+
+    // from internal hardware
+    .de     (hw2reg.mio_pad_sleep_status[46].de),
+    .d      (hw2reg.mio_pad_sleep_status[46].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_pad_sleep_status[46].q ),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_status_1_en_46_qs)
+  );
+
+
 
 
   // Subregister 0 of Multireg mio_pad_sleep_regwen
@@ -13185,6 +13844,114 @@
     .qs     (mio_pad_sleep_regwen_42_qs)
   );
 
+  // Subregister 43 of Multireg mio_pad_sleep_regwen
+  // R[mio_pad_sleep_regwen_43]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_pad_sleep_regwen_43 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_pad_sleep_regwen_43_we),
+    .wd     (mio_pad_sleep_regwen_43_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_regwen_43_qs)
+  );
+
+  // Subregister 44 of Multireg mio_pad_sleep_regwen
+  // R[mio_pad_sleep_regwen_44]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_pad_sleep_regwen_44 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_pad_sleep_regwen_44_we),
+    .wd     (mio_pad_sleep_regwen_44_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_regwen_44_qs)
+  );
+
+  // Subregister 45 of Multireg mio_pad_sleep_regwen
+  // R[mio_pad_sleep_regwen_45]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_pad_sleep_regwen_45 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_pad_sleep_regwen_45_we),
+    .wd     (mio_pad_sleep_regwen_45_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_regwen_45_qs)
+  );
+
+  // Subregister 46 of Multireg mio_pad_sleep_regwen
+  // R[mio_pad_sleep_regwen_46]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_pad_sleep_regwen_46 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_pad_sleep_regwen_46_we),
+    .wd     (mio_pad_sleep_regwen_46_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_regwen_46_qs)
+  );
+
 
 
   // Subregister 0 of Multireg mio_pad_sleep_en
@@ -14348,6 +15115,114 @@
     .qs     (mio_pad_sleep_en_42_qs)
   );
 
+  // Subregister 43 of Multireg mio_pad_sleep_en
+  // R[mio_pad_sleep_en_43]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_mio_pad_sleep_en_43 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_pad_sleep_en_43_we & mio_pad_sleep_regwen_43_qs),
+    .wd     (mio_pad_sleep_en_43_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_pad_sleep_en[43].q ),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_en_43_qs)
+  );
+
+  // Subregister 44 of Multireg mio_pad_sleep_en
+  // R[mio_pad_sleep_en_44]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_mio_pad_sleep_en_44 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_pad_sleep_en_44_we & mio_pad_sleep_regwen_44_qs),
+    .wd     (mio_pad_sleep_en_44_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_pad_sleep_en[44].q ),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_en_44_qs)
+  );
+
+  // Subregister 45 of Multireg mio_pad_sleep_en
+  // R[mio_pad_sleep_en_45]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_mio_pad_sleep_en_45 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_pad_sleep_en_45_we & mio_pad_sleep_regwen_45_qs),
+    .wd     (mio_pad_sleep_en_45_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_pad_sleep_en[45].q ),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_en_45_qs)
+  );
+
+  // Subregister 46 of Multireg mio_pad_sleep_en
+  // R[mio_pad_sleep_en_46]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_mio_pad_sleep_en_46 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_pad_sleep_en_46_we & mio_pad_sleep_regwen_46_qs),
+    .wd     (mio_pad_sleep_en_46_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_pad_sleep_en[46].q ),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_en_46_qs)
+  );
+
 
 
   // Subregister 0 of Multireg mio_pad_sleep_mode
@@ -15511,6 +16386,114 @@
     .qs     (mio_pad_sleep_mode_42_qs)
   );
 
+  // Subregister 43 of Multireg mio_pad_sleep_mode
+  // R[mio_pad_sleep_mode_43]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h2)
+  ) u_mio_pad_sleep_mode_43 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_pad_sleep_mode_43_we & mio_pad_sleep_regwen_43_qs),
+    .wd     (mio_pad_sleep_mode_43_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_pad_sleep_mode[43].q ),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_mode_43_qs)
+  );
+
+  // Subregister 44 of Multireg mio_pad_sleep_mode
+  // R[mio_pad_sleep_mode_44]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h2)
+  ) u_mio_pad_sleep_mode_44 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_pad_sleep_mode_44_we & mio_pad_sleep_regwen_44_qs),
+    .wd     (mio_pad_sleep_mode_44_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_pad_sleep_mode[44].q ),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_mode_44_qs)
+  );
+
+  // Subregister 45 of Multireg mio_pad_sleep_mode
+  // R[mio_pad_sleep_mode_45]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h2)
+  ) u_mio_pad_sleep_mode_45 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_pad_sleep_mode_45_we & mio_pad_sleep_regwen_45_qs),
+    .wd     (mio_pad_sleep_mode_45_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_pad_sleep_mode[45].q ),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_mode_45_qs)
+  );
+
+  // Subregister 46 of Multireg mio_pad_sleep_mode
+  // R[mio_pad_sleep_mode_46]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h2)
+  ) u_mio_pad_sleep_mode_46 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_pad_sleep_mode_46_we & mio_pad_sleep_regwen_46_qs),
+    .wd     (mio_pad_sleep_mode_46_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_pad_sleep_mode[46].q ),
+
+    // to register interface (read)
+    .qs     (mio_pad_sleep_mode_46_qs)
+  );
+
 
 
   // Subregister 0 of Multireg dio_pad_sleep_status
@@ -16088,6 +17071,32 @@
   );
 
 
+  // F[en_22]: 22:22
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h0)
+  ) u_dio_pad_sleep_status_en_22 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_sleep_status_en_22_we),
+    .wd     (dio_pad_sleep_status_en_22_wd),
+
+    // from internal hardware
+    .de     (hw2reg.dio_pad_sleep_status[22].de),
+    .d      (hw2reg.dio_pad_sleep_status[22].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_status[22].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_status_en_22_qs)
+  );
+
+
 
 
   // Subregister 0 of Multireg dio_pad_sleep_regwen
@@ -16684,6 +17693,33 @@
     .qs     (dio_pad_sleep_regwen_21_qs)
   );
 
+  // Subregister 22 of Multireg dio_pad_sleep_regwen
+  // R[dio_pad_sleep_regwen_22]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_dio_pad_sleep_regwen_22 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_sleep_regwen_22_we),
+    .wd     (dio_pad_sleep_regwen_22_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_regwen_22_qs)
+  );
+
 
 
   // Subregister 0 of Multireg dio_pad_sleep_en
@@ -17280,6 +18316,33 @@
     .qs     (dio_pad_sleep_en_21_qs)
   );
 
+  // Subregister 22 of Multireg dio_pad_sleep_en
+  // R[dio_pad_sleep_en_22]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_dio_pad_sleep_en_22 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (dio_pad_sleep_en_22_we & dio_pad_sleep_regwen_22_qs),
+    .wd     (dio_pad_sleep_en_22_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_en[22].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_en_22_qs)
+  );
+
 
 
   // Subregister 0 of Multireg dio_pad_sleep_mode
@@ -17876,6 +18939,33 @@
     .qs     (dio_pad_sleep_mode_21_qs)
   );
 
+  // Subregister 22 of Multireg dio_pad_sleep_mode
+  // R[dio_pad_sleep_mode_22]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h2)
+  ) u_dio_pad_sleep_mode_22 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (dio_pad_sleep_mode_22_we & dio_pad_sleep_regwen_22_qs),
+    .wd     (dio_pad_sleep_mode_22_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_mode[22].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_mode_22_qs)
+  );
+
 
 
   // Subregister 0 of Multireg wkup_detector_regwen
@@ -19526,7 +20616,7 @@
 
 
 
-  logic [584:0] addr_hit;
+  logic [617:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[  0] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET);
@@ -19702,418 +20792,451 @@
     addr_hit[170] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET);
     addr_hit[171] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET);
     addr_hit[172] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET);
-    addr_hit[173] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET);
-    addr_hit[174] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET);
-    addr_hit[175] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET);
-    addr_hit[176] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET);
-    addr_hit[177] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET);
-    addr_hit[178] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET);
-    addr_hit[179] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET);
-    addr_hit[180] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET);
-    addr_hit[181] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET);
-    addr_hit[182] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET);
-    addr_hit[183] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET);
-    addr_hit[184] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET);
-    addr_hit[185] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET);
-    addr_hit[186] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET);
-    addr_hit[187] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET);
-    addr_hit[188] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET);
-    addr_hit[189] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET);
-    addr_hit[190] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET);
-    addr_hit[191] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET);
-    addr_hit[192] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET);
-    addr_hit[193] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET);
-    addr_hit[194] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET);
-    addr_hit[195] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET);
-    addr_hit[196] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET);
-    addr_hit[197] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET);
-    addr_hit[198] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET);
-    addr_hit[199] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET);
-    addr_hit[200] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET);
-    addr_hit[201] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET);
-    addr_hit[202] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET);
-    addr_hit[203] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET);
-    addr_hit[204] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET);
-    addr_hit[205] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET);
-    addr_hit[206] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET);
-    addr_hit[207] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET);
-    addr_hit[208] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET);
-    addr_hit[209] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET);
-    addr_hit[210] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET);
-    addr_hit[211] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET);
-    addr_hit[212] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET);
-    addr_hit[213] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET);
-    addr_hit[214] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET);
-    addr_hit[215] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET);
-    addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET);
-    addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET);
-    addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET);
-    addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET);
-    addr_hit[220] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET);
-    addr_hit[221] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET);
-    addr_hit[222] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET);
-    addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET);
-    addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET);
-    addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET);
-    addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET);
-    addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET);
-    addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET);
-    addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET);
-    addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET);
-    addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET);
-    addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET);
-    addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET);
-    addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET);
-    addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET);
-    addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET);
-    addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET);
-    addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET);
-    addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET);
-    addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET);
-    addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET);
-    addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET);
-    addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET);
-    addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET);
-    addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET);
-    addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET);
-    addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET);
-    addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET);
-    addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET);
-    addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET);
-    addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET);
-    addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET);
-    addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET);
-    addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET);
-    addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET);
-    addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET);
-    addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET);
-    addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET);
-    addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET);
-    addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET);
-    addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET);
-    addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET);
-    addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET);
-    addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET);
-    addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET);
-    addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET);
-    addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET);
-    addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET);
-    addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET);
-    addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET);
-    addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET);
-    addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET);
-    addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET);
-    addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET);
-    addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET);
-    addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET);
-    addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET);
-    addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET);
-    addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET);
-    addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET);
-    addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET);
-    addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET);
-    addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET);
-    addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET);
-    addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET);
-    addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET);
-    addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET);
-    addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET);
-    addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET);
-    addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET);
-    addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET);
-    addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET);
-    addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET);
-    addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET);
-    addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET);
-    addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET);
-    addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET);
-    addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET);
-    addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET);
-    addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET);
-    addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET);
-    addr_hit[302] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET);
-    addr_hit[303] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET);
-    addr_hit[304] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET);
-    addr_hit[305] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET);
-    addr_hit[306] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET);
-    addr_hit[307] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET);
-    addr_hit[308] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET);
-    addr_hit[309] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET);
-    addr_hit[310] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET);
-    addr_hit[311] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET);
-    addr_hit[312] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET);
-    addr_hit[313] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET);
-    addr_hit[314] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET);
-    addr_hit[315] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET);
-    addr_hit[316] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET);
-    addr_hit[317] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET);
-    addr_hit[318] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET);
-    addr_hit[319] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET);
-    addr_hit[320] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET);
-    addr_hit[321] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET);
-    addr_hit[322] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET);
-    addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET);
-    addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET);
-    addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET);
-    addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET);
-    addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET);
-    addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET);
-    addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET);
-    addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET);
-    addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET);
-    addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET);
-    addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET);
-    addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET);
-    addr_hit[335] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET);
-    addr_hit[336] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET);
-    addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET);
-    addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET);
-    addr_hit[339] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET);
-    addr_hit[340] = (reg_addr == PINMUX_DIO_PAD_ATTR_16_OFFSET);
-    addr_hit[341] = (reg_addr == PINMUX_DIO_PAD_ATTR_17_OFFSET);
-    addr_hit[342] = (reg_addr == PINMUX_DIO_PAD_ATTR_18_OFFSET);
-    addr_hit[343] = (reg_addr == PINMUX_DIO_PAD_ATTR_19_OFFSET);
-    addr_hit[344] = (reg_addr == PINMUX_DIO_PAD_ATTR_20_OFFSET);
-    addr_hit[345] = (reg_addr == PINMUX_DIO_PAD_ATTR_21_OFFSET);
-    addr_hit[346] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET);
-    addr_hit[347] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET);
-    addr_hit[348] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET);
-    addr_hit[349] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET);
-    addr_hit[350] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET);
-    addr_hit[351] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET);
-    addr_hit[352] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET);
-    addr_hit[353] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET);
-    addr_hit[354] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET);
-    addr_hit[355] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET);
-    addr_hit[356] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET);
-    addr_hit[357] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET);
-    addr_hit[358] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET);
-    addr_hit[359] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET);
-    addr_hit[360] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET);
-    addr_hit[361] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET);
-    addr_hit[362] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET);
-    addr_hit[363] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET);
-    addr_hit[364] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET);
-    addr_hit[365] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET);
-    addr_hit[366] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET);
-    addr_hit[367] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET);
-    addr_hit[368] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET);
-    addr_hit[369] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET);
-    addr_hit[370] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET);
-    addr_hit[371] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET);
-    addr_hit[372] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET);
-    addr_hit[373] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET);
-    addr_hit[374] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET);
-    addr_hit[375] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET);
-    addr_hit[376] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET);
-    addr_hit[377] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET);
-    addr_hit[378] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET);
-    addr_hit[379] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET);
-    addr_hit[380] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET);
-    addr_hit[381] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET);
-    addr_hit[382] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET);
-    addr_hit[383] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET);
-    addr_hit[384] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET);
-    addr_hit[385] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET);
-    addr_hit[386] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET);
-    addr_hit[387] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET);
-    addr_hit[388] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET);
-    addr_hit[389] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET);
-    addr_hit[390] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET);
-    addr_hit[391] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET);
-    addr_hit[392] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET);
-    addr_hit[393] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET);
-    addr_hit[394] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET);
-    addr_hit[395] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET);
-    addr_hit[396] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET);
-    addr_hit[397] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET);
-    addr_hit[398] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET);
-    addr_hit[399] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET);
-    addr_hit[400] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET);
-    addr_hit[401] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET);
-    addr_hit[402] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET);
-    addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET);
-    addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET);
-    addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET);
-    addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET);
-    addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET);
-    addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET);
-    addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET);
-    addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET);
-    addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET);
-    addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET);
-    addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET);
-    addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET);
-    addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET);
-    addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET);
-    addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET);
-    addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET);
-    addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET);
-    addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET);
-    addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET);
-    addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET);
-    addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET);
-    addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET);
-    addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET);
-    addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET);
-    addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET);
-    addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET);
-    addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET);
-    addr_hit[430] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET);
-    addr_hit[431] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET);
-    addr_hit[432] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET);
-    addr_hit[433] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET);
-    addr_hit[434] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET);
-    addr_hit[435] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET);
-    addr_hit[436] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET);
-    addr_hit[437] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET);
-    addr_hit[438] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET);
-    addr_hit[439] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET);
-    addr_hit[440] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET);
-    addr_hit[441] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET);
-    addr_hit[442] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET);
-    addr_hit[443] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET);
-    addr_hit[444] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET);
-    addr_hit[445] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET);
-    addr_hit[446] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET);
-    addr_hit[447] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET);
-    addr_hit[448] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET);
-    addr_hit[449] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET);
-    addr_hit[450] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET);
-    addr_hit[451] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET);
-    addr_hit[452] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET);
-    addr_hit[453] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET);
-    addr_hit[454] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET);
-    addr_hit[455] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET);
-    addr_hit[456] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET);
-    addr_hit[457] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET);
-    addr_hit[458] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET);
-    addr_hit[459] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET);
-    addr_hit[460] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET);
-    addr_hit[461] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET);
-    addr_hit[462] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET);
-    addr_hit[463] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET);
-    addr_hit[464] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET);
-    addr_hit[465] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET);
-    addr_hit[466] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET);
-    addr_hit[467] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET);
-    addr_hit[468] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET);
-    addr_hit[469] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET);
-    addr_hit[470] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET);
-    addr_hit[471] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET);
-    addr_hit[472] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET);
-    addr_hit[473] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET);
-    addr_hit[474] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET);
-    addr_hit[475] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET);
-    addr_hit[476] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET);
-    addr_hit[477] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET);
-    addr_hit[478] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET);
-    addr_hit[479] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET);
-    addr_hit[480] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET);
-    addr_hit[481] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET);
-    addr_hit[482] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET);
-    addr_hit[483] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET);
-    addr_hit[484] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET);
-    addr_hit[485] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET);
-    addr_hit[486] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET);
-    addr_hit[487] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET);
-    addr_hit[488] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET);
-    addr_hit[489] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET);
-    addr_hit[490] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET);
-    addr_hit[491] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET);
-    addr_hit[492] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET);
-    addr_hit[493] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET);
-    addr_hit[494] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET);
-    addr_hit[495] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET);
-    addr_hit[496] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET);
-    addr_hit[497] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET);
-    addr_hit[498] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET);
-    addr_hit[499] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET);
-    addr_hit[500] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET);
-    addr_hit[501] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET);
-    addr_hit[502] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET);
-    addr_hit[503] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET);
-    addr_hit[504] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET);
-    addr_hit[505] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET);
-    addr_hit[506] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET);
-    addr_hit[507] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET);
-    addr_hit[508] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET);
-    addr_hit[509] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET);
-    addr_hit[510] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET);
-    addr_hit[511] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET);
-    addr_hit[512] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET);
-    addr_hit[513] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET);
-    addr_hit[514] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET);
-    addr_hit[515] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET);
-    addr_hit[516] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET);
-    addr_hit[517] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET);
-    addr_hit[518] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET);
-    addr_hit[519] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET);
-    addr_hit[520] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET);
-    addr_hit[521] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET);
-    addr_hit[522] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET);
-    addr_hit[523] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET);
-    addr_hit[524] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET);
-    addr_hit[525] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET);
-    addr_hit[526] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET);
-    addr_hit[527] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET);
-    addr_hit[528] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET);
-    addr_hit[529] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET);
-    addr_hit[530] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET);
-    addr_hit[531] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET);
-    addr_hit[532] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET);
-    addr_hit[533] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET);
-    addr_hit[534] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET);
-    addr_hit[535] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET);
-    addr_hit[536] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET);
-    addr_hit[537] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET);
-    addr_hit[538] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET);
-    addr_hit[539] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET);
-    addr_hit[540] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET);
-    addr_hit[541] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET);
-    addr_hit[542] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET);
-    addr_hit[543] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET);
-    addr_hit[544] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET);
-    addr_hit[545] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET);
-    addr_hit[546] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET);
-    addr_hit[547] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET);
-    addr_hit[548] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET);
-    addr_hit[549] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET);
-    addr_hit[550] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET);
-    addr_hit[551] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET);
-    addr_hit[552] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET);
-    addr_hit[553] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET);
-    addr_hit[554] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET);
-    addr_hit[555] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET);
-    addr_hit[556] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET);
-    addr_hit[557] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET);
-    addr_hit[558] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET);
-    addr_hit[559] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET);
-    addr_hit[560] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET);
-    addr_hit[561] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET);
-    addr_hit[562] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET);
-    addr_hit[563] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET);
-    addr_hit[564] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET);
-    addr_hit[565] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET);
-    addr_hit[566] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET);
-    addr_hit[567] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET);
-    addr_hit[568] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET);
-    addr_hit[569] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET);
-    addr_hit[570] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET);
-    addr_hit[571] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET);
-    addr_hit[572] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET);
-    addr_hit[573] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET);
-    addr_hit[574] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET);
-    addr_hit[575] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET);
-    addr_hit[576] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET);
-    addr_hit[577] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET);
-    addr_hit[578] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET);
-    addr_hit[579] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET);
-    addr_hit[580] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET);
-    addr_hit[581] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET);
-    addr_hit[582] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET);
-    addr_hit[583] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET);
-    addr_hit[584] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET);
+    addr_hit[173] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET);
+    addr_hit[174] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET);
+    addr_hit[175] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET);
+    addr_hit[176] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET);
+    addr_hit[177] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET);
+    addr_hit[178] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET);
+    addr_hit[179] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET);
+    addr_hit[180] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET);
+    addr_hit[181] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET);
+    addr_hit[182] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET);
+    addr_hit[183] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET);
+    addr_hit[184] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET);
+    addr_hit[185] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET);
+    addr_hit[186] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET);
+    addr_hit[187] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET);
+    addr_hit[188] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET);
+    addr_hit[189] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET);
+    addr_hit[190] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET);
+    addr_hit[191] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET);
+    addr_hit[192] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET);
+    addr_hit[193] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET);
+    addr_hit[194] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET);
+    addr_hit[195] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET);
+    addr_hit[196] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET);
+    addr_hit[197] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET);
+    addr_hit[198] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET);
+    addr_hit[199] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET);
+    addr_hit[200] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET);
+    addr_hit[201] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET);
+    addr_hit[202] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET);
+    addr_hit[203] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET);
+    addr_hit[204] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET);
+    addr_hit[205] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET);
+    addr_hit[206] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET);
+    addr_hit[207] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET);
+    addr_hit[208] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET);
+    addr_hit[209] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET);
+    addr_hit[210] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET);
+    addr_hit[211] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET);
+    addr_hit[212] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET);
+    addr_hit[213] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET);
+    addr_hit[214] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET);
+    addr_hit[215] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET);
+    addr_hit[216] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET);
+    addr_hit[217] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET);
+    addr_hit[218] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET);
+    addr_hit[219] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET);
+    addr_hit[220] = (reg_addr == PINMUX_MIO_OUTSEL_43_OFFSET);
+    addr_hit[221] = (reg_addr == PINMUX_MIO_OUTSEL_44_OFFSET);
+    addr_hit[222] = (reg_addr == PINMUX_MIO_OUTSEL_45_OFFSET);
+    addr_hit[223] = (reg_addr == PINMUX_MIO_OUTSEL_46_OFFSET);
+    addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET);
+    addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET);
+    addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET);
+    addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET);
+    addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET);
+    addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET);
+    addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET);
+    addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET);
+    addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET);
+    addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET);
+    addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET);
+    addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET);
+    addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET);
+    addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET);
+    addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET);
+    addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET);
+    addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET);
+    addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET);
+    addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET);
+    addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET);
+    addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET);
+    addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET);
+    addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET);
+    addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET);
+    addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET);
+    addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET);
+    addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET);
+    addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET);
+    addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET);
+    addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET);
+    addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET);
+    addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET);
+    addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET);
+    addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET);
+    addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET);
+    addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET);
+    addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET);
+    addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET);
+    addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET);
+    addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET);
+    addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET);
+    addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET);
+    addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET);
+    addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET);
+    addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET);
+    addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET);
+    addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET);
+    addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET);
+    addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET);
+    addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET);
+    addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET);
+    addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET);
+    addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET);
+    addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET);
+    addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET);
+    addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET);
+    addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET);
+    addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET);
+    addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET);
+    addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET);
+    addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET);
+    addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET);
+    addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET);
+    addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET);
+    addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET);
+    addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET);
+    addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET);
+    addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET);
+    addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET);
+    addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET);
+    addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET);
+    addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET);
+    addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET);
+    addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET);
+    addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET);
+    addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET);
+    addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET);
+    addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET);
+    addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET);
+    addr_hit[303] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET);
+    addr_hit[304] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET);
+    addr_hit[305] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET);
+    addr_hit[306] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET);
+    addr_hit[307] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET);
+    addr_hit[308] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET);
+    addr_hit[309] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET);
+    addr_hit[310] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET);
+    addr_hit[311] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET);
+    addr_hit[312] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET);
+    addr_hit[313] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET);
+    addr_hit[314] = (reg_addr == PINMUX_MIO_PAD_ATTR_43_OFFSET);
+    addr_hit[315] = (reg_addr == PINMUX_MIO_PAD_ATTR_44_OFFSET);
+    addr_hit[316] = (reg_addr == PINMUX_MIO_PAD_ATTR_45_OFFSET);
+    addr_hit[317] = (reg_addr == PINMUX_MIO_PAD_ATTR_46_OFFSET);
+    addr_hit[318] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET);
+    addr_hit[319] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET);
+    addr_hit[320] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET);
+    addr_hit[321] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET);
+    addr_hit[322] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET);
+    addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET);
+    addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET);
+    addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET);
+    addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET);
+    addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET);
+    addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET);
+    addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET);
+    addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET);
+    addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET);
+    addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET);
+    addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET);
+    addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET);
+    addr_hit[335] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET);
+    addr_hit[336] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET);
+    addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET);
+    addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET);
+    addr_hit[339] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET);
+    addr_hit[340] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_22_OFFSET);
+    addr_hit[341] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET);
+    addr_hit[342] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET);
+    addr_hit[343] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET);
+    addr_hit[344] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET);
+    addr_hit[345] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET);
+    addr_hit[346] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET);
+    addr_hit[347] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET);
+    addr_hit[348] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET);
+    addr_hit[349] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET);
+    addr_hit[350] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET);
+    addr_hit[351] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET);
+    addr_hit[352] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET);
+    addr_hit[353] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET);
+    addr_hit[354] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET);
+    addr_hit[355] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET);
+    addr_hit[356] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET);
+    addr_hit[357] = (reg_addr == PINMUX_DIO_PAD_ATTR_16_OFFSET);
+    addr_hit[358] = (reg_addr == PINMUX_DIO_PAD_ATTR_17_OFFSET);
+    addr_hit[359] = (reg_addr == PINMUX_DIO_PAD_ATTR_18_OFFSET);
+    addr_hit[360] = (reg_addr == PINMUX_DIO_PAD_ATTR_19_OFFSET);
+    addr_hit[361] = (reg_addr == PINMUX_DIO_PAD_ATTR_20_OFFSET);
+    addr_hit[362] = (reg_addr == PINMUX_DIO_PAD_ATTR_21_OFFSET);
+    addr_hit[363] = (reg_addr == PINMUX_DIO_PAD_ATTR_22_OFFSET);
+    addr_hit[364] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET);
+    addr_hit[365] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET);
+    addr_hit[366] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET);
+    addr_hit[367] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET);
+    addr_hit[368] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET);
+    addr_hit[369] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET);
+    addr_hit[370] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET);
+    addr_hit[371] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET);
+    addr_hit[372] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET);
+    addr_hit[373] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET);
+    addr_hit[374] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET);
+    addr_hit[375] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET);
+    addr_hit[376] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET);
+    addr_hit[377] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET);
+    addr_hit[378] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET);
+    addr_hit[379] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET);
+    addr_hit[380] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET);
+    addr_hit[381] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET);
+    addr_hit[382] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET);
+    addr_hit[383] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET);
+    addr_hit[384] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET);
+    addr_hit[385] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET);
+    addr_hit[386] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET);
+    addr_hit[387] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET);
+    addr_hit[388] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET);
+    addr_hit[389] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET);
+    addr_hit[390] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET);
+    addr_hit[391] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET);
+    addr_hit[392] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET);
+    addr_hit[393] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET);
+    addr_hit[394] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET);
+    addr_hit[395] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET);
+    addr_hit[396] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET);
+    addr_hit[397] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET);
+    addr_hit[398] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET);
+    addr_hit[399] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET);
+    addr_hit[400] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET);
+    addr_hit[401] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET);
+    addr_hit[402] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET);
+    addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET);
+    addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET);
+    addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET);
+    addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET);
+    addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET);
+    addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET);
+    addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET);
+    addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET);
+    addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET);
+    addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET);
+    addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET);
+    addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET);
+    addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET);
+    addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET);
+    addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET);
+    addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET);
+    addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET);
+    addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET);
+    addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET);
+    addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET);
+    addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET);
+    addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET);
+    addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET);
+    addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET);
+    addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET);
+    addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET);
+    addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET);
+    addr_hit[430] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET);
+    addr_hit[431] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET);
+    addr_hit[432] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET);
+    addr_hit[433] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET);
+    addr_hit[434] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET);
+    addr_hit[435] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET);
+    addr_hit[436] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET);
+    addr_hit[437] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET);
+    addr_hit[438] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET);
+    addr_hit[439] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET);
+    addr_hit[440] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET);
+    addr_hit[441] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET);
+    addr_hit[442] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET);
+    addr_hit[443] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET);
+    addr_hit[444] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET);
+    addr_hit[445] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET);
+    addr_hit[446] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET);
+    addr_hit[447] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET);
+    addr_hit[448] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET);
+    addr_hit[449] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET);
+    addr_hit[450] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET);
+    addr_hit[451] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET);
+    addr_hit[452] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET);
+    addr_hit[453] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET);
+    addr_hit[454] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET);
+    addr_hit[455] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET);
+    addr_hit[456] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET);
+    addr_hit[457] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET);
+    addr_hit[458] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET);
+    addr_hit[459] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET);
+    addr_hit[460] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET);
+    addr_hit[461] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET);
+    addr_hit[462] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET);
+    addr_hit[463] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET);
+    addr_hit[464] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET);
+    addr_hit[465] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET);
+    addr_hit[466] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET);
+    addr_hit[467] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET);
+    addr_hit[468] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET);
+    addr_hit[469] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET);
+    addr_hit[470] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET);
+    addr_hit[471] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET);
+    addr_hit[472] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET);
+    addr_hit[473] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET);
+    addr_hit[474] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET);
+    addr_hit[475] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET);
+    addr_hit[476] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET);
+    addr_hit[477] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET);
+    addr_hit[478] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET);
+    addr_hit[479] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET);
+    addr_hit[480] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET);
+    addr_hit[481] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET);
+    addr_hit[482] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET);
+    addr_hit[483] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET);
+    addr_hit[484] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET);
+    addr_hit[485] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET);
+    addr_hit[486] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET);
+    addr_hit[487] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET);
+    addr_hit[488] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET);
+    addr_hit[489] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET);
+    addr_hit[490] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET);
+    addr_hit[491] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET);
+    addr_hit[492] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET);
+    addr_hit[493] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET);
+    addr_hit[494] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET);
+    addr_hit[495] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET);
+    addr_hit[496] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET);
+    addr_hit[497] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET);
+    addr_hit[498] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET);
+    addr_hit[499] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET);
+    addr_hit[500] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET);
+    addr_hit[501] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET);
+    addr_hit[502] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET);
+    addr_hit[503] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET);
+    addr_hit[504] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET);
+    addr_hit[505] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET);
+    addr_hit[506] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET);
+    addr_hit[507] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET);
+    addr_hit[508] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET);
+    addr_hit[509] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET);
+    addr_hit[510] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET);
+    addr_hit[511] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET);
+    addr_hit[512] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET);
+    addr_hit[513] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET);
+    addr_hit[514] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET);
+    addr_hit[515] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET);
+    addr_hit[516] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET);
+    addr_hit[517] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET);
+    addr_hit[518] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET);
+    addr_hit[519] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET);
+    addr_hit[520] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET);
+    addr_hit[521] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET);
+    addr_hit[522] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET);
+    addr_hit[523] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET);
+    addr_hit[524] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET);
+    addr_hit[525] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET);
+    addr_hit[526] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET);
+    addr_hit[527] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET);
+    addr_hit[528] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET);
+    addr_hit[529] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET);
+    addr_hit[530] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_22_OFFSET);
+    addr_hit[531] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET);
+    addr_hit[532] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET);
+    addr_hit[533] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET);
+    addr_hit[534] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET);
+    addr_hit[535] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET);
+    addr_hit[536] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET);
+    addr_hit[537] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET);
+    addr_hit[538] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET);
+    addr_hit[539] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET);
+    addr_hit[540] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET);
+    addr_hit[541] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET);
+    addr_hit[542] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET);
+    addr_hit[543] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET);
+    addr_hit[544] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET);
+    addr_hit[545] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET);
+    addr_hit[546] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET);
+    addr_hit[547] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET);
+    addr_hit[548] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET);
+    addr_hit[549] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET);
+    addr_hit[550] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET);
+    addr_hit[551] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET);
+    addr_hit[552] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET);
+    addr_hit[553] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_22_OFFSET);
+    addr_hit[554] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET);
+    addr_hit[555] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET);
+    addr_hit[556] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET);
+    addr_hit[557] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET);
+    addr_hit[558] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET);
+    addr_hit[559] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET);
+    addr_hit[560] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET);
+    addr_hit[561] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET);
+    addr_hit[562] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET);
+    addr_hit[563] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET);
+    addr_hit[564] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET);
+    addr_hit[565] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET);
+    addr_hit[566] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET);
+    addr_hit[567] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET);
+    addr_hit[568] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET);
+    addr_hit[569] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET);
+    addr_hit[570] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET);
+    addr_hit[571] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET);
+    addr_hit[572] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET);
+    addr_hit[573] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET);
+    addr_hit[574] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET);
+    addr_hit[575] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET);
+    addr_hit[576] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_22_OFFSET);
+    addr_hit[577] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET);
+    addr_hit[578] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET);
+    addr_hit[579] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET);
+    addr_hit[580] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET);
+    addr_hit[581] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET);
+    addr_hit[582] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET);
+    addr_hit[583] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET);
+    addr_hit[584] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET);
+    addr_hit[585] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET);
+    addr_hit[586] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET);
+    addr_hit[587] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET);
+    addr_hit[588] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET);
+    addr_hit[589] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET);
+    addr_hit[590] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET);
+    addr_hit[591] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET);
+    addr_hit[592] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET);
+    addr_hit[593] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET);
+    addr_hit[594] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET);
+    addr_hit[595] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET);
+    addr_hit[596] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET);
+    addr_hit[597] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET);
+    addr_hit[598] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET);
+    addr_hit[599] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET);
+    addr_hit[600] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET);
+    addr_hit[601] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET);
+    addr_hit[602] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET);
+    addr_hit[603] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET);
+    addr_hit[604] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET);
+    addr_hit[605] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET);
+    addr_hit[606] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET);
+    addr_hit[607] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET);
+    addr_hit[608] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET);
+    addr_hit[609] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET);
+    addr_hit[610] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET);
+    addr_hit[611] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET);
+    addr_hit[612] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET);
+    addr_hit[613] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET);
+    addr_hit[614] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET);
+    addr_hit[615] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET);
+    addr_hit[616] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET);
+    addr_hit[617] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -20706,6 +21829,39 @@
     if (addr_hit[582] && reg_we && (PINMUX_PERMIT[582] != (PINMUX_PERMIT[582] & reg_be))) wr_err = 1'b1 ;
     if (addr_hit[583] && reg_we && (PINMUX_PERMIT[583] != (PINMUX_PERMIT[583] & reg_be))) wr_err = 1'b1 ;
     if (addr_hit[584] && reg_we && (PINMUX_PERMIT[584] != (PINMUX_PERMIT[584] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[585] && reg_we && (PINMUX_PERMIT[585] != (PINMUX_PERMIT[585] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[586] && reg_we && (PINMUX_PERMIT[586] != (PINMUX_PERMIT[586] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[587] && reg_we && (PINMUX_PERMIT[587] != (PINMUX_PERMIT[587] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[588] && reg_we && (PINMUX_PERMIT[588] != (PINMUX_PERMIT[588] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[589] && reg_we && (PINMUX_PERMIT[589] != (PINMUX_PERMIT[589] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[590] && reg_we && (PINMUX_PERMIT[590] != (PINMUX_PERMIT[590] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[591] && reg_we && (PINMUX_PERMIT[591] != (PINMUX_PERMIT[591] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[592] && reg_we && (PINMUX_PERMIT[592] != (PINMUX_PERMIT[592] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[593] && reg_we && (PINMUX_PERMIT[593] != (PINMUX_PERMIT[593] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[594] && reg_we && (PINMUX_PERMIT[594] != (PINMUX_PERMIT[594] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[595] && reg_we && (PINMUX_PERMIT[595] != (PINMUX_PERMIT[595] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[596] && reg_we && (PINMUX_PERMIT[596] != (PINMUX_PERMIT[596] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[597] && reg_we && (PINMUX_PERMIT[597] != (PINMUX_PERMIT[597] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[598] && reg_we && (PINMUX_PERMIT[598] != (PINMUX_PERMIT[598] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[599] && reg_we && (PINMUX_PERMIT[599] != (PINMUX_PERMIT[599] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[600] && reg_we && (PINMUX_PERMIT[600] != (PINMUX_PERMIT[600] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[601] && reg_we && (PINMUX_PERMIT[601] != (PINMUX_PERMIT[601] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[602] && reg_we && (PINMUX_PERMIT[602] != (PINMUX_PERMIT[602] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[603] && reg_we && (PINMUX_PERMIT[603] != (PINMUX_PERMIT[603] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[604] && reg_we && (PINMUX_PERMIT[604] != (PINMUX_PERMIT[604] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[605] && reg_we && (PINMUX_PERMIT[605] != (PINMUX_PERMIT[605] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[606] && reg_we && (PINMUX_PERMIT[606] != (PINMUX_PERMIT[606] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[607] && reg_we && (PINMUX_PERMIT[607] != (PINMUX_PERMIT[607] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[608] && reg_we && (PINMUX_PERMIT[608] != (PINMUX_PERMIT[608] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[609] && reg_we && (PINMUX_PERMIT[609] != (PINMUX_PERMIT[609] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[610] && reg_we && (PINMUX_PERMIT[610] != (PINMUX_PERMIT[610] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[611] && reg_we && (PINMUX_PERMIT[611] != (PINMUX_PERMIT[611] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[612] && reg_we && (PINMUX_PERMIT[612] != (PINMUX_PERMIT[612] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[613] && reg_we && (PINMUX_PERMIT[613] != (PINMUX_PERMIT[613] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[614] && reg_we && (PINMUX_PERMIT[614] != (PINMUX_PERMIT[614] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[615] && reg_we && (PINMUX_PERMIT[615] != (PINMUX_PERMIT[615] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[616] && reg_we && (PINMUX_PERMIT[616] != (PINMUX_PERMIT[616] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[617] && reg_we && (PINMUX_PERMIT[617] != (PINMUX_PERMIT[617] & reg_be))) wr_err = 1'b1 ;
   end
 
   assign mio_periph_insel_regwen_0_we = addr_hit[0] & reg_we & !reg_error;
@@ -21227,1569 +22383,1688 @@
   assign mio_outsel_regwen_42_we = addr_hit[172] & reg_we & !reg_error;
   assign mio_outsel_regwen_42_wd = reg_wdata[0];
 
-  assign mio_outsel_0_we = addr_hit[173] & reg_we & !reg_error;
+  assign mio_outsel_regwen_43_we = addr_hit[173] & reg_we & !reg_error;
+  assign mio_outsel_regwen_43_wd = reg_wdata[0];
+
+  assign mio_outsel_regwen_44_we = addr_hit[174] & reg_we & !reg_error;
+  assign mio_outsel_regwen_44_wd = reg_wdata[0];
+
+  assign mio_outsel_regwen_45_we = addr_hit[175] & reg_we & !reg_error;
+  assign mio_outsel_regwen_45_wd = reg_wdata[0];
+
+  assign mio_outsel_regwen_46_we = addr_hit[176] & reg_we & !reg_error;
+  assign mio_outsel_regwen_46_wd = reg_wdata[0];
+
+  assign mio_outsel_0_we = addr_hit[177] & reg_we & !reg_error;
   assign mio_outsel_0_wd = reg_wdata[6:0];
 
-  assign mio_outsel_1_we = addr_hit[174] & reg_we & !reg_error;
+  assign mio_outsel_1_we = addr_hit[178] & reg_we & !reg_error;
   assign mio_outsel_1_wd = reg_wdata[6:0];
 
-  assign mio_outsel_2_we = addr_hit[175] & reg_we & !reg_error;
+  assign mio_outsel_2_we = addr_hit[179] & reg_we & !reg_error;
   assign mio_outsel_2_wd = reg_wdata[6:0];
 
-  assign mio_outsel_3_we = addr_hit[176] & reg_we & !reg_error;
+  assign mio_outsel_3_we = addr_hit[180] & reg_we & !reg_error;
   assign mio_outsel_3_wd = reg_wdata[6:0];
 
-  assign mio_outsel_4_we = addr_hit[177] & reg_we & !reg_error;
+  assign mio_outsel_4_we = addr_hit[181] & reg_we & !reg_error;
   assign mio_outsel_4_wd = reg_wdata[6:0];
 
-  assign mio_outsel_5_we = addr_hit[178] & reg_we & !reg_error;
+  assign mio_outsel_5_we = addr_hit[182] & reg_we & !reg_error;
   assign mio_outsel_5_wd = reg_wdata[6:0];
 
-  assign mio_outsel_6_we = addr_hit[179] & reg_we & !reg_error;
+  assign mio_outsel_6_we = addr_hit[183] & reg_we & !reg_error;
   assign mio_outsel_6_wd = reg_wdata[6:0];
 
-  assign mio_outsel_7_we = addr_hit[180] & reg_we & !reg_error;
+  assign mio_outsel_7_we = addr_hit[184] & reg_we & !reg_error;
   assign mio_outsel_7_wd = reg_wdata[6:0];
 
-  assign mio_outsel_8_we = addr_hit[181] & reg_we & !reg_error;
+  assign mio_outsel_8_we = addr_hit[185] & reg_we & !reg_error;
   assign mio_outsel_8_wd = reg_wdata[6:0];
 
-  assign mio_outsel_9_we = addr_hit[182] & reg_we & !reg_error;
+  assign mio_outsel_9_we = addr_hit[186] & reg_we & !reg_error;
   assign mio_outsel_9_wd = reg_wdata[6:0];
 
-  assign mio_outsel_10_we = addr_hit[183] & reg_we & !reg_error;
+  assign mio_outsel_10_we = addr_hit[187] & reg_we & !reg_error;
   assign mio_outsel_10_wd = reg_wdata[6:0];
 
-  assign mio_outsel_11_we = addr_hit[184] & reg_we & !reg_error;
+  assign mio_outsel_11_we = addr_hit[188] & reg_we & !reg_error;
   assign mio_outsel_11_wd = reg_wdata[6:0];
 
-  assign mio_outsel_12_we = addr_hit[185] & reg_we & !reg_error;
+  assign mio_outsel_12_we = addr_hit[189] & reg_we & !reg_error;
   assign mio_outsel_12_wd = reg_wdata[6:0];
 
-  assign mio_outsel_13_we = addr_hit[186] & reg_we & !reg_error;
+  assign mio_outsel_13_we = addr_hit[190] & reg_we & !reg_error;
   assign mio_outsel_13_wd = reg_wdata[6:0];
 
-  assign mio_outsel_14_we = addr_hit[187] & reg_we & !reg_error;
+  assign mio_outsel_14_we = addr_hit[191] & reg_we & !reg_error;
   assign mio_outsel_14_wd = reg_wdata[6:0];
 
-  assign mio_outsel_15_we = addr_hit[188] & reg_we & !reg_error;
+  assign mio_outsel_15_we = addr_hit[192] & reg_we & !reg_error;
   assign mio_outsel_15_wd = reg_wdata[6:0];
 
-  assign mio_outsel_16_we = addr_hit[189] & reg_we & !reg_error;
+  assign mio_outsel_16_we = addr_hit[193] & reg_we & !reg_error;
   assign mio_outsel_16_wd = reg_wdata[6:0];
 
-  assign mio_outsel_17_we = addr_hit[190] & reg_we & !reg_error;
+  assign mio_outsel_17_we = addr_hit[194] & reg_we & !reg_error;
   assign mio_outsel_17_wd = reg_wdata[6:0];
 
-  assign mio_outsel_18_we = addr_hit[191] & reg_we & !reg_error;
+  assign mio_outsel_18_we = addr_hit[195] & reg_we & !reg_error;
   assign mio_outsel_18_wd = reg_wdata[6:0];
 
-  assign mio_outsel_19_we = addr_hit[192] & reg_we & !reg_error;
+  assign mio_outsel_19_we = addr_hit[196] & reg_we & !reg_error;
   assign mio_outsel_19_wd = reg_wdata[6:0];
 
-  assign mio_outsel_20_we = addr_hit[193] & reg_we & !reg_error;
+  assign mio_outsel_20_we = addr_hit[197] & reg_we & !reg_error;
   assign mio_outsel_20_wd = reg_wdata[6:0];
 
-  assign mio_outsel_21_we = addr_hit[194] & reg_we & !reg_error;
+  assign mio_outsel_21_we = addr_hit[198] & reg_we & !reg_error;
   assign mio_outsel_21_wd = reg_wdata[6:0];
 
-  assign mio_outsel_22_we = addr_hit[195] & reg_we & !reg_error;
+  assign mio_outsel_22_we = addr_hit[199] & reg_we & !reg_error;
   assign mio_outsel_22_wd = reg_wdata[6:0];
 
-  assign mio_outsel_23_we = addr_hit[196] & reg_we & !reg_error;
+  assign mio_outsel_23_we = addr_hit[200] & reg_we & !reg_error;
   assign mio_outsel_23_wd = reg_wdata[6:0];
 
-  assign mio_outsel_24_we = addr_hit[197] & reg_we & !reg_error;
+  assign mio_outsel_24_we = addr_hit[201] & reg_we & !reg_error;
   assign mio_outsel_24_wd = reg_wdata[6:0];
 
-  assign mio_outsel_25_we = addr_hit[198] & reg_we & !reg_error;
+  assign mio_outsel_25_we = addr_hit[202] & reg_we & !reg_error;
   assign mio_outsel_25_wd = reg_wdata[6:0];
 
-  assign mio_outsel_26_we = addr_hit[199] & reg_we & !reg_error;
+  assign mio_outsel_26_we = addr_hit[203] & reg_we & !reg_error;
   assign mio_outsel_26_wd = reg_wdata[6:0];
 
-  assign mio_outsel_27_we = addr_hit[200] & reg_we & !reg_error;
+  assign mio_outsel_27_we = addr_hit[204] & reg_we & !reg_error;
   assign mio_outsel_27_wd = reg_wdata[6:0];
 
-  assign mio_outsel_28_we = addr_hit[201] & reg_we & !reg_error;
+  assign mio_outsel_28_we = addr_hit[205] & reg_we & !reg_error;
   assign mio_outsel_28_wd = reg_wdata[6:0];
 
-  assign mio_outsel_29_we = addr_hit[202] & reg_we & !reg_error;
+  assign mio_outsel_29_we = addr_hit[206] & reg_we & !reg_error;
   assign mio_outsel_29_wd = reg_wdata[6:0];
 
-  assign mio_outsel_30_we = addr_hit[203] & reg_we & !reg_error;
+  assign mio_outsel_30_we = addr_hit[207] & reg_we & !reg_error;
   assign mio_outsel_30_wd = reg_wdata[6:0];
 
-  assign mio_outsel_31_we = addr_hit[204] & reg_we & !reg_error;
+  assign mio_outsel_31_we = addr_hit[208] & reg_we & !reg_error;
   assign mio_outsel_31_wd = reg_wdata[6:0];
 
-  assign mio_outsel_32_we = addr_hit[205] & reg_we & !reg_error;
+  assign mio_outsel_32_we = addr_hit[209] & reg_we & !reg_error;
   assign mio_outsel_32_wd = reg_wdata[6:0];
 
-  assign mio_outsel_33_we = addr_hit[206] & reg_we & !reg_error;
+  assign mio_outsel_33_we = addr_hit[210] & reg_we & !reg_error;
   assign mio_outsel_33_wd = reg_wdata[6:0];
 
-  assign mio_outsel_34_we = addr_hit[207] & reg_we & !reg_error;
+  assign mio_outsel_34_we = addr_hit[211] & reg_we & !reg_error;
   assign mio_outsel_34_wd = reg_wdata[6:0];
 
-  assign mio_outsel_35_we = addr_hit[208] & reg_we & !reg_error;
+  assign mio_outsel_35_we = addr_hit[212] & reg_we & !reg_error;
   assign mio_outsel_35_wd = reg_wdata[6:0];
 
-  assign mio_outsel_36_we = addr_hit[209] & reg_we & !reg_error;
+  assign mio_outsel_36_we = addr_hit[213] & reg_we & !reg_error;
   assign mio_outsel_36_wd = reg_wdata[6:0];
 
-  assign mio_outsel_37_we = addr_hit[210] & reg_we & !reg_error;
+  assign mio_outsel_37_we = addr_hit[214] & reg_we & !reg_error;
   assign mio_outsel_37_wd = reg_wdata[6:0];
 
-  assign mio_outsel_38_we = addr_hit[211] & reg_we & !reg_error;
+  assign mio_outsel_38_we = addr_hit[215] & reg_we & !reg_error;
   assign mio_outsel_38_wd = reg_wdata[6:0];
 
-  assign mio_outsel_39_we = addr_hit[212] & reg_we & !reg_error;
+  assign mio_outsel_39_we = addr_hit[216] & reg_we & !reg_error;
   assign mio_outsel_39_wd = reg_wdata[6:0];
 
-  assign mio_outsel_40_we = addr_hit[213] & reg_we & !reg_error;
+  assign mio_outsel_40_we = addr_hit[217] & reg_we & !reg_error;
   assign mio_outsel_40_wd = reg_wdata[6:0];
 
-  assign mio_outsel_41_we = addr_hit[214] & reg_we & !reg_error;
+  assign mio_outsel_41_we = addr_hit[218] & reg_we & !reg_error;
   assign mio_outsel_41_wd = reg_wdata[6:0];
 
-  assign mio_outsel_42_we = addr_hit[215] & reg_we & !reg_error;
+  assign mio_outsel_42_we = addr_hit[219] & reg_we & !reg_error;
   assign mio_outsel_42_wd = reg_wdata[6:0];
 
-  assign mio_pad_attr_regwen_0_we = addr_hit[216] & reg_we & !reg_error;
+  assign mio_outsel_43_we = addr_hit[220] & reg_we & !reg_error;
+  assign mio_outsel_43_wd = reg_wdata[6:0];
+
+  assign mio_outsel_44_we = addr_hit[221] & reg_we & !reg_error;
+  assign mio_outsel_44_wd = reg_wdata[6:0];
+
+  assign mio_outsel_45_we = addr_hit[222] & reg_we & !reg_error;
+  assign mio_outsel_45_wd = reg_wdata[6:0];
+
+  assign mio_outsel_46_we = addr_hit[223] & reg_we & !reg_error;
+  assign mio_outsel_46_wd = reg_wdata[6:0];
+
+  assign mio_pad_attr_regwen_0_we = addr_hit[224] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_0_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_1_we = addr_hit[217] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_1_we = addr_hit[225] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_1_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_2_we = addr_hit[218] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_2_we = addr_hit[226] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_2_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_3_we = addr_hit[219] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_3_we = addr_hit[227] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_3_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_4_we = addr_hit[220] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_4_we = addr_hit[228] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_4_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_5_we = addr_hit[221] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_5_we = addr_hit[229] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_5_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_6_we = addr_hit[222] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_6_we = addr_hit[230] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_6_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_7_we = addr_hit[223] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_7_we = addr_hit[231] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_7_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_8_we = addr_hit[224] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_8_we = addr_hit[232] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_8_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_9_we = addr_hit[225] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_9_we = addr_hit[233] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_9_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_10_we = addr_hit[226] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_10_we = addr_hit[234] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_10_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_11_we = addr_hit[227] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_11_we = addr_hit[235] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_11_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_12_we = addr_hit[228] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_12_we = addr_hit[236] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_12_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_13_we = addr_hit[229] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_13_we = addr_hit[237] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_13_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_14_we = addr_hit[230] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_14_we = addr_hit[238] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_14_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_15_we = addr_hit[231] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_15_we = addr_hit[239] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_15_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_16_we = addr_hit[232] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_16_we = addr_hit[240] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_16_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_17_we = addr_hit[233] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_17_we = addr_hit[241] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_17_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_18_we = addr_hit[234] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_18_we = addr_hit[242] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_18_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_19_we = addr_hit[235] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_19_we = addr_hit[243] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_19_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_20_we = addr_hit[236] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_20_we = addr_hit[244] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_20_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_21_we = addr_hit[237] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_21_we = addr_hit[245] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_21_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_22_we = addr_hit[238] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_22_we = addr_hit[246] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_22_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_23_we = addr_hit[239] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_23_we = addr_hit[247] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_23_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_24_we = addr_hit[240] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_24_we = addr_hit[248] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_24_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_25_we = addr_hit[241] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_25_we = addr_hit[249] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_25_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_26_we = addr_hit[242] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_26_we = addr_hit[250] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_26_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_27_we = addr_hit[243] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_27_we = addr_hit[251] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_27_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_28_we = addr_hit[244] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_28_we = addr_hit[252] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_28_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_29_we = addr_hit[245] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_29_we = addr_hit[253] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_29_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_30_we = addr_hit[246] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_30_we = addr_hit[254] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_30_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_31_we = addr_hit[247] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_31_we = addr_hit[255] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_31_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_32_we = addr_hit[248] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_32_we = addr_hit[256] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_32_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_33_we = addr_hit[249] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_33_we = addr_hit[257] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_33_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_34_we = addr_hit[250] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_34_we = addr_hit[258] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_34_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_35_we = addr_hit[251] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_35_we = addr_hit[259] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_35_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_36_we = addr_hit[252] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_36_we = addr_hit[260] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_36_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_37_we = addr_hit[253] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_37_we = addr_hit[261] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_37_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_38_we = addr_hit[254] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_38_we = addr_hit[262] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_38_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_39_we = addr_hit[255] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_39_we = addr_hit[263] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_39_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_40_we = addr_hit[256] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_40_we = addr_hit[264] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_40_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_41_we = addr_hit[257] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_41_we = addr_hit[265] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_41_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_42_we = addr_hit[258] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_42_we = addr_hit[266] & reg_we & !reg_error;
   assign mio_pad_attr_regwen_42_wd = reg_wdata[0];
 
-  assign mio_pad_attr_0_we = addr_hit[259] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_43_we = addr_hit[267] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_43_wd = reg_wdata[0];
+
+  assign mio_pad_attr_regwen_44_we = addr_hit[268] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_44_wd = reg_wdata[0];
+
+  assign mio_pad_attr_regwen_45_we = addr_hit[269] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_45_wd = reg_wdata[0];
+
+  assign mio_pad_attr_regwen_46_we = addr_hit[270] & reg_we & !reg_error;
+  assign mio_pad_attr_regwen_46_wd = reg_wdata[0];
+
+  assign mio_pad_attr_0_we = addr_hit[271] & reg_we & !reg_error;
   assign mio_pad_attr_0_wd = reg_wdata[12:0];
-  assign mio_pad_attr_0_re = addr_hit[259] & reg_re & !reg_error;
+  assign mio_pad_attr_0_re = addr_hit[271] & reg_re & !reg_error;
 
-  assign mio_pad_attr_1_we = addr_hit[260] & reg_we & !reg_error;
+  assign mio_pad_attr_1_we = addr_hit[272] & reg_we & !reg_error;
   assign mio_pad_attr_1_wd = reg_wdata[12:0];
-  assign mio_pad_attr_1_re = addr_hit[260] & reg_re & !reg_error;
+  assign mio_pad_attr_1_re = addr_hit[272] & reg_re & !reg_error;
 
-  assign mio_pad_attr_2_we = addr_hit[261] & reg_we & !reg_error;
+  assign mio_pad_attr_2_we = addr_hit[273] & reg_we & !reg_error;
   assign mio_pad_attr_2_wd = reg_wdata[12:0];
-  assign mio_pad_attr_2_re = addr_hit[261] & reg_re & !reg_error;
+  assign mio_pad_attr_2_re = addr_hit[273] & reg_re & !reg_error;
 
-  assign mio_pad_attr_3_we = addr_hit[262] & reg_we & !reg_error;
+  assign mio_pad_attr_3_we = addr_hit[274] & reg_we & !reg_error;
   assign mio_pad_attr_3_wd = reg_wdata[12:0];
-  assign mio_pad_attr_3_re = addr_hit[262] & reg_re & !reg_error;
+  assign mio_pad_attr_3_re = addr_hit[274] & reg_re & !reg_error;
 
-  assign mio_pad_attr_4_we = addr_hit[263] & reg_we & !reg_error;
+  assign mio_pad_attr_4_we = addr_hit[275] & reg_we & !reg_error;
   assign mio_pad_attr_4_wd = reg_wdata[12:0];
-  assign mio_pad_attr_4_re = addr_hit[263] & reg_re & !reg_error;
+  assign mio_pad_attr_4_re = addr_hit[275] & reg_re & !reg_error;
 
-  assign mio_pad_attr_5_we = addr_hit[264] & reg_we & !reg_error;
+  assign mio_pad_attr_5_we = addr_hit[276] & reg_we & !reg_error;
   assign mio_pad_attr_5_wd = reg_wdata[12:0];
-  assign mio_pad_attr_5_re = addr_hit[264] & reg_re & !reg_error;
+  assign mio_pad_attr_5_re = addr_hit[276] & reg_re & !reg_error;
 
-  assign mio_pad_attr_6_we = addr_hit[265] & reg_we & !reg_error;
+  assign mio_pad_attr_6_we = addr_hit[277] & reg_we & !reg_error;
   assign mio_pad_attr_6_wd = reg_wdata[12:0];
-  assign mio_pad_attr_6_re = addr_hit[265] & reg_re & !reg_error;
+  assign mio_pad_attr_6_re = addr_hit[277] & reg_re & !reg_error;
 
-  assign mio_pad_attr_7_we = addr_hit[266] & reg_we & !reg_error;
+  assign mio_pad_attr_7_we = addr_hit[278] & reg_we & !reg_error;
   assign mio_pad_attr_7_wd = reg_wdata[12:0];
-  assign mio_pad_attr_7_re = addr_hit[266] & reg_re & !reg_error;
+  assign mio_pad_attr_7_re = addr_hit[278] & reg_re & !reg_error;
 
-  assign mio_pad_attr_8_we = addr_hit[267] & reg_we & !reg_error;
+  assign mio_pad_attr_8_we = addr_hit[279] & reg_we & !reg_error;
   assign mio_pad_attr_8_wd = reg_wdata[12:0];
-  assign mio_pad_attr_8_re = addr_hit[267] & reg_re & !reg_error;
+  assign mio_pad_attr_8_re = addr_hit[279] & reg_re & !reg_error;
 
-  assign mio_pad_attr_9_we = addr_hit[268] & reg_we & !reg_error;
+  assign mio_pad_attr_9_we = addr_hit[280] & reg_we & !reg_error;
   assign mio_pad_attr_9_wd = reg_wdata[12:0];
-  assign mio_pad_attr_9_re = addr_hit[268] & reg_re & !reg_error;
+  assign mio_pad_attr_9_re = addr_hit[280] & reg_re & !reg_error;
 
-  assign mio_pad_attr_10_we = addr_hit[269] & reg_we & !reg_error;
+  assign mio_pad_attr_10_we = addr_hit[281] & reg_we & !reg_error;
   assign mio_pad_attr_10_wd = reg_wdata[12:0];
-  assign mio_pad_attr_10_re = addr_hit[269] & reg_re & !reg_error;
+  assign mio_pad_attr_10_re = addr_hit[281] & reg_re & !reg_error;
 
-  assign mio_pad_attr_11_we = addr_hit[270] & reg_we & !reg_error;
+  assign mio_pad_attr_11_we = addr_hit[282] & reg_we & !reg_error;
   assign mio_pad_attr_11_wd = reg_wdata[12:0];
-  assign mio_pad_attr_11_re = addr_hit[270] & reg_re & !reg_error;
+  assign mio_pad_attr_11_re = addr_hit[282] & reg_re & !reg_error;
 
-  assign mio_pad_attr_12_we = addr_hit[271] & reg_we & !reg_error;
+  assign mio_pad_attr_12_we = addr_hit[283] & reg_we & !reg_error;
   assign mio_pad_attr_12_wd = reg_wdata[12:0];
-  assign mio_pad_attr_12_re = addr_hit[271] & reg_re & !reg_error;
+  assign mio_pad_attr_12_re = addr_hit[283] & reg_re & !reg_error;
 
-  assign mio_pad_attr_13_we = addr_hit[272] & reg_we & !reg_error;
+  assign mio_pad_attr_13_we = addr_hit[284] & reg_we & !reg_error;
   assign mio_pad_attr_13_wd = reg_wdata[12:0];
-  assign mio_pad_attr_13_re = addr_hit[272] & reg_re & !reg_error;
+  assign mio_pad_attr_13_re = addr_hit[284] & reg_re & !reg_error;
 
-  assign mio_pad_attr_14_we = addr_hit[273] & reg_we & !reg_error;
+  assign mio_pad_attr_14_we = addr_hit[285] & reg_we & !reg_error;
   assign mio_pad_attr_14_wd = reg_wdata[12:0];
-  assign mio_pad_attr_14_re = addr_hit[273] & reg_re & !reg_error;
+  assign mio_pad_attr_14_re = addr_hit[285] & reg_re & !reg_error;
 
-  assign mio_pad_attr_15_we = addr_hit[274] & reg_we & !reg_error;
+  assign mio_pad_attr_15_we = addr_hit[286] & reg_we & !reg_error;
   assign mio_pad_attr_15_wd = reg_wdata[12:0];
-  assign mio_pad_attr_15_re = addr_hit[274] & reg_re & !reg_error;
+  assign mio_pad_attr_15_re = addr_hit[286] & reg_re & !reg_error;
 
-  assign mio_pad_attr_16_we = addr_hit[275] & reg_we & !reg_error;
+  assign mio_pad_attr_16_we = addr_hit[287] & reg_we & !reg_error;
   assign mio_pad_attr_16_wd = reg_wdata[12:0];
-  assign mio_pad_attr_16_re = addr_hit[275] & reg_re & !reg_error;
+  assign mio_pad_attr_16_re = addr_hit[287] & reg_re & !reg_error;
 
-  assign mio_pad_attr_17_we = addr_hit[276] & reg_we & !reg_error;
+  assign mio_pad_attr_17_we = addr_hit[288] & reg_we & !reg_error;
   assign mio_pad_attr_17_wd = reg_wdata[12:0];
-  assign mio_pad_attr_17_re = addr_hit[276] & reg_re & !reg_error;
+  assign mio_pad_attr_17_re = addr_hit[288] & reg_re & !reg_error;
 
-  assign mio_pad_attr_18_we = addr_hit[277] & reg_we & !reg_error;
+  assign mio_pad_attr_18_we = addr_hit[289] & reg_we & !reg_error;
   assign mio_pad_attr_18_wd = reg_wdata[12:0];
-  assign mio_pad_attr_18_re = addr_hit[277] & reg_re & !reg_error;
+  assign mio_pad_attr_18_re = addr_hit[289] & reg_re & !reg_error;
 
-  assign mio_pad_attr_19_we = addr_hit[278] & reg_we & !reg_error;
+  assign mio_pad_attr_19_we = addr_hit[290] & reg_we & !reg_error;
   assign mio_pad_attr_19_wd = reg_wdata[12:0];
-  assign mio_pad_attr_19_re = addr_hit[278] & reg_re & !reg_error;
+  assign mio_pad_attr_19_re = addr_hit[290] & reg_re & !reg_error;
 
-  assign mio_pad_attr_20_we = addr_hit[279] & reg_we & !reg_error;
+  assign mio_pad_attr_20_we = addr_hit[291] & reg_we & !reg_error;
   assign mio_pad_attr_20_wd = reg_wdata[12:0];
-  assign mio_pad_attr_20_re = addr_hit[279] & reg_re & !reg_error;
+  assign mio_pad_attr_20_re = addr_hit[291] & reg_re & !reg_error;
 
-  assign mio_pad_attr_21_we = addr_hit[280] & reg_we & !reg_error;
+  assign mio_pad_attr_21_we = addr_hit[292] & reg_we & !reg_error;
   assign mio_pad_attr_21_wd = reg_wdata[12:0];
-  assign mio_pad_attr_21_re = addr_hit[280] & reg_re & !reg_error;
+  assign mio_pad_attr_21_re = addr_hit[292] & reg_re & !reg_error;
 
-  assign mio_pad_attr_22_we = addr_hit[281] & reg_we & !reg_error;
+  assign mio_pad_attr_22_we = addr_hit[293] & reg_we & !reg_error;
   assign mio_pad_attr_22_wd = reg_wdata[12:0];
-  assign mio_pad_attr_22_re = addr_hit[281] & reg_re & !reg_error;
+  assign mio_pad_attr_22_re = addr_hit[293] & reg_re & !reg_error;
 
-  assign mio_pad_attr_23_we = addr_hit[282] & reg_we & !reg_error;
+  assign mio_pad_attr_23_we = addr_hit[294] & reg_we & !reg_error;
   assign mio_pad_attr_23_wd = reg_wdata[12:0];
-  assign mio_pad_attr_23_re = addr_hit[282] & reg_re & !reg_error;
+  assign mio_pad_attr_23_re = addr_hit[294] & reg_re & !reg_error;
 
-  assign mio_pad_attr_24_we = addr_hit[283] & reg_we & !reg_error;
+  assign mio_pad_attr_24_we = addr_hit[295] & reg_we & !reg_error;
   assign mio_pad_attr_24_wd = reg_wdata[12:0];
-  assign mio_pad_attr_24_re = addr_hit[283] & reg_re & !reg_error;
+  assign mio_pad_attr_24_re = addr_hit[295] & reg_re & !reg_error;
 
-  assign mio_pad_attr_25_we = addr_hit[284] & reg_we & !reg_error;
+  assign mio_pad_attr_25_we = addr_hit[296] & reg_we & !reg_error;
   assign mio_pad_attr_25_wd = reg_wdata[12:0];
-  assign mio_pad_attr_25_re = addr_hit[284] & reg_re & !reg_error;
+  assign mio_pad_attr_25_re = addr_hit[296] & reg_re & !reg_error;
 
-  assign mio_pad_attr_26_we = addr_hit[285] & reg_we & !reg_error;
+  assign mio_pad_attr_26_we = addr_hit[297] & reg_we & !reg_error;
   assign mio_pad_attr_26_wd = reg_wdata[12:0];
-  assign mio_pad_attr_26_re = addr_hit[285] & reg_re & !reg_error;
+  assign mio_pad_attr_26_re = addr_hit[297] & reg_re & !reg_error;
 
-  assign mio_pad_attr_27_we = addr_hit[286] & reg_we & !reg_error;
+  assign mio_pad_attr_27_we = addr_hit[298] & reg_we & !reg_error;
   assign mio_pad_attr_27_wd = reg_wdata[12:0];
-  assign mio_pad_attr_27_re = addr_hit[286] & reg_re & !reg_error;
+  assign mio_pad_attr_27_re = addr_hit[298] & reg_re & !reg_error;
 
-  assign mio_pad_attr_28_we = addr_hit[287] & reg_we & !reg_error;
+  assign mio_pad_attr_28_we = addr_hit[299] & reg_we & !reg_error;
   assign mio_pad_attr_28_wd = reg_wdata[12:0];
-  assign mio_pad_attr_28_re = addr_hit[287] & reg_re & !reg_error;
+  assign mio_pad_attr_28_re = addr_hit[299] & reg_re & !reg_error;
 
-  assign mio_pad_attr_29_we = addr_hit[288] & reg_we & !reg_error;
+  assign mio_pad_attr_29_we = addr_hit[300] & reg_we & !reg_error;
   assign mio_pad_attr_29_wd = reg_wdata[12:0];
-  assign mio_pad_attr_29_re = addr_hit[288] & reg_re & !reg_error;
+  assign mio_pad_attr_29_re = addr_hit[300] & reg_re & !reg_error;
 
-  assign mio_pad_attr_30_we = addr_hit[289] & reg_we & !reg_error;
+  assign mio_pad_attr_30_we = addr_hit[301] & reg_we & !reg_error;
   assign mio_pad_attr_30_wd = reg_wdata[12:0];
-  assign mio_pad_attr_30_re = addr_hit[289] & reg_re & !reg_error;
+  assign mio_pad_attr_30_re = addr_hit[301] & reg_re & !reg_error;
 
-  assign mio_pad_attr_31_we = addr_hit[290] & reg_we & !reg_error;
+  assign mio_pad_attr_31_we = addr_hit[302] & reg_we & !reg_error;
   assign mio_pad_attr_31_wd = reg_wdata[12:0];
-  assign mio_pad_attr_31_re = addr_hit[290] & reg_re & !reg_error;
+  assign mio_pad_attr_31_re = addr_hit[302] & reg_re & !reg_error;
 
-  assign mio_pad_attr_32_we = addr_hit[291] & reg_we & !reg_error;
+  assign mio_pad_attr_32_we = addr_hit[303] & reg_we & !reg_error;
   assign mio_pad_attr_32_wd = reg_wdata[12:0];
-  assign mio_pad_attr_32_re = addr_hit[291] & reg_re & !reg_error;
+  assign mio_pad_attr_32_re = addr_hit[303] & reg_re & !reg_error;
 
-  assign mio_pad_attr_33_we = addr_hit[292] & reg_we & !reg_error;
+  assign mio_pad_attr_33_we = addr_hit[304] & reg_we & !reg_error;
   assign mio_pad_attr_33_wd = reg_wdata[12:0];
-  assign mio_pad_attr_33_re = addr_hit[292] & reg_re & !reg_error;
+  assign mio_pad_attr_33_re = addr_hit[304] & reg_re & !reg_error;
 
-  assign mio_pad_attr_34_we = addr_hit[293] & reg_we & !reg_error;
+  assign mio_pad_attr_34_we = addr_hit[305] & reg_we & !reg_error;
   assign mio_pad_attr_34_wd = reg_wdata[12:0];
-  assign mio_pad_attr_34_re = addr_hit[293] & reg_re & !reg_error;
+  assign mio_pad_attr_34_re = addr_hit[305] & reg_re & !reg_error;
 
-  assign mio_pad_attr_35_we = addr_hit[294] & reg_we & !reg_error;
+  assign mio_pad_attr_35_we = addr_hit[306] & reg_we & !reg_error;
   assign mio_pad_attr_35_wd = reg_wdata[12:0];
-  assign mio_pad_attr_35_re = addr_hit[294] & reg_re & !reg_error;
+  assign mio_pad_attr_35_re = addr_hit[306] & reg_re & !reg_error;
 
-  assign mio_pad_attr_36_we = addr_hit[295] & reg_we & !reg_error;
+  assign mio_pad_attr_36_we = addr_hit[307] & reg_we & !reg_error;
   assign mio_pad_attr_36_wd = reg_wdata[12:0];
-  assign mio_pad_attr_36_re = addr_hit[295] & reg_re & !reg_error;
+  assign mio_pad_attr_36_re = addr_hit[307] & reg_re & !reg_error;
 
-  assign mio_pad_attr_37_we = addr_hit[296] & reg_we & !reg_error;
+  assign mio_pad_attr_37_we = addr_hit[308] & reg_we & !reg_error;
   assign mio_pad_attr_37_wd = reg_wdata[12:0];
-  assign mio_pad_attr_37_re = addr_hit[296] & reg_re & !reg_error;
+  assign mio_pad_attr_37_re = addr_hit[308] & reg_re & !reg_error;
 
-  assign mio_pad_attr_38_we = addr_hit[297] & reg_we & !reg_error;
+  assign mio_pad_attr_38_we = addr_hit[309] & reg_we & !reg_error;
   assign mio_pad_attr_38_wd = reg_wdata[12:0];
-  assign mio_pad_attr_38_re = addr_hit[297] & reg_re & !reg_error;
+  assign mio_pad_attr_38_re = addr_hit[309] & reg_re & !reg_error;
 
-  assign mio_pad_attr_39_we = addr_hit[298] & reg_we & !reg_error;
+  assign mio_pad_attr_39_we = addr_hit[310] & reg_we & !reg_error;
   assign mio_pad_attr_39_wd = reg_wdata[12:0];
-  assign mio_pad_attr_39_re = addr_hit[298] & reg_re & !reg_error;
+  assign mio_pad_attr_39_re = addr_hit[310] & reg_re & !reg_error;
 
-  assign mio_pad_attr_40_we = addr_hit[299] & reg_we & !reg_error;
+  assign mio_pad_attr_40_we = addr_hit[311] & reg_we & !reg_error;
   assign mio_pad_attr_40_wd = reg_wdata[12:0];
-  assign mio_pad_attr_40_re = addr_hit[299] & reg_re & !reg_error;
+  assign mio_pad_attr_40_re = addr_hit[311] & reg_re & !reg_error;
 
-  assign mio_pad_attr_41_we = addr_hit[300] & reg_we & !reg_error;
+  assign mio_pad_attr_41_we = addr_hit[312] & reg_we & !reg_error;
   assign mio_pad_attr_41_wd = reg_wdata[12:0];
-  assign mio_pad_attr_41_re = addr_hit[300] & reg_re & !reg_error;
+  assign mio_pad_attr_41_re = addr_hit[312] & reg_re & !reg_error;
 
-  assign mio_pad_attr_42_we = addr_hit[301] & reg_we & !reg_error;
+  assign mio_pad_attr_42_we = addr_hit[313] & reg_we & !reg_error;
   assign mio_pad_attr_42_wd = reg_wdata[12:0];
-  assign mio_pad_attr_42_re = addr_hit[301] & reg_re & !reg_error;
+  assign mio_pad_attr_42_re = addr_hit[313] & reg_re & !reg_error;
 
-  assign dio_pad_attr_regwen_0_we = addr_hit[302] & reg_we & !reg_error;
+  assign mio_pad_attr_43_we = addr_hit[314] & reg_we & !reg_error;
+  assign mio_pad_attr_43_wd = reg_wdata[12:0];
+  assign mio_pad_attr_43_re = addr_hit[314] & reg_re & !reg_error;
+
+  assign mio_pad_attr_44_we = addr_hit[315] & reg_we & !reg_error;
+  assign mio_pad_attr_44_wd = reg_wdata[12:0];
+  assign mio_pad_attr_44_re = addr_hit[315] & reg_re & !reg_error;
+
+  assign mio_pad_attr_45_we = addr_hit[316] & reg_we & !reg_error;
+  assign mio_pad_attr_45_wd = reg_wdata[12:0];
+  assign mio_pad_attr_45_re = addr_hit[316] & reg_re & !reg_error;
+
+  assign mio_pad_attr_46_we = addr_hit[317] & reg_we & !reg_error;
+  assign mio_pad_attr_46_wd = reg_wdata[12:0];
+  assign mio_pad_attr_46_re = addr_hit[317] & reg_re & !reg_error;
+
+  assign dio_pad_attr_regwen_0_we = addr_hit[318] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_0_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_1_we = addr_hit[303] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_1_we = addr_hit[319] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_1_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_2_we = addr_hit[304] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_2_we = addr_hit[320] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_2_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_3_we = addr_hit[305] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_3_we = addr_hit[321] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_3_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_4_we = addr_hit[306] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_4_we = addr_hit[322] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_4_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_5_we = addr_hit[307] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_5_we = addr_hit[323] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_5_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_6_we = addr_hit[308] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_6_we = addr_hit[324] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_6_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_7_we = addr_hit[309] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_7_we = addr_hit[325] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_7_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_8_we = addr_hit[310] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_8_we = addr_hit[326] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_8_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_9_we = addr_hit[311] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_9_we = addr_hit[327] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_9_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_10_we = addr_hit[312] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_10_we = addr_hit[328] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_10_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_11_we = addr_hit[313] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_11_we = addr_hit[329] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_11_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_12_we = addr_hit[314] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_12_we = addr_hit[330] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_12_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_13_we = addr_hit[315] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_13_we = addr_hit[331] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_13_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_14_we = addr_hit[316] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_14_we = addr_hit[332] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_14_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_15_we = addr_hit[317] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_15_we = addr_hit[333] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_15_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_16_we = addr_hit[318] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_16_we = addr_hit[334] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_16_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_17_we = addr_hit[319] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_17_we = addr_hit[335] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_17_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_18_we = addr_hit[320] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_18_we = addr_hit[336] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_18_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_19_we = addr_hit[321] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_19_we = addr_hit[337] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_19_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_20_we = addr_hit[322] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_20_we = addr_hit[338] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_20_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_21_we = addr_hit[323] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_21_we = addr_hit[339] & reg_we & !reg_error;
   assign dio_pad_attr_regwen_21_wd = reg_wdata[0];
 
-  assign dio_pad_attr_0_we = addr_hit[324] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_22_we = addr_hit[340] & reg_we & !reg_error;
+  assign dio_pad_attr_regwen_22_wd = reg_wdata[0];
+
+  assign dio_pad_attr_0_we = addr_hit[341] & reg_we & !reg_error;
   assign dio_pad_attr_0_wd = reg_wdata[12:0];
-  assign dio_pad_attr_0_re = addr_hit[324] & reg_re & !reg_error;
+  assign dio_pad_attr_0_re = addr_hit[341] & reg_re & !reg_error;
 
-  assign dio_pad_attr_1_we = addr_hit[325] & reg_we & !reg_error;
+  assign dio_pad_attr_1_we = addr_hit[342] & reg_we & !reg_error;
   assign dio_pad_attr_1_wd = reg_wdata[12:0];
-  assign dio_pad_attr_1_re = addr_hit[325] & reg_re & !reg_error;
+  assign dio_pad_attr_1_re = addr_hit[342] & reg_re & !reg_error;
 
-  assign dio_pad_attr_2_we = addr_hit[326] & reg_we & !reg_error;
+  assign dio_pad_attr_2_we = addr_hit[343] & reg_we & !reg_error;
   assign dio_pad_attr_2_wd = reg_wdata[12:0];
-  assign dio_pad_attr_2_re = addr_hit[326] & reg_re & !reg_error;
+  assign dio_pad_attr_2_re = addr_hit[343] & reg_re & !reg_error;
 
-  assign dio_pad_attr_3_we = addr_hit[327] & reg_we & !reg_error;
+  assign dio_pad_attr_3_we = addr_hit[344] & reg_we & !reg_error;
   assign dio_pad_attr_3_wd = reg_wdata[12:0];
-  assign dio_pad_attr_3_re = addr_hit[327] & reg_re & !reg_error;
+  assign dio_pad_attr_3_re = addr_hit[344] & reg_re & !reg_error;
 
-  assign dio_pad_attr_4_we = addr_hit[328] & reg_we & !reg_error;
+  assign dio_pad_attr_4_we = addr_hit[345] & reg_we & !reg_error;
   assign dio_pad_attr_4_wd = reg_wdata[12:0];
-  assign dio_pad_attr_4_re = addr_hit[328] & reg_re & !reg_error;
+  assign dio_pad_attr_4_re = addr_hit[345] & reg_re & !reg_error;
 
-  assign dio_pad_attr_5_we = addr_hit[329] & reg_we & !reg_error;
+  assign dio_pad_attr_5_we = addr_hit[346] & reg_we & !reg_error;
   assign dio_pad_attr_5_wd = reg_wdata[12:0];
-  assign dio_pad_attr_5_re = addr_hit[329] & reg_re & !reg_error;
+  assign dio_pad_attr_5_re = addr_hit[346] & reg_re & !reg_error;
 
-  assign dio_pad_attr_6_we = addr_hit[330] & reg_we & !reg_error;
+  assign dio_pad_attr_6_we = addr_hit[347] & reg_we & !reg_error;
   assign dio_pad_attr_6_wd = reg_wdata[12:0];
-  assign dio_pad_attr_6_re = addr_hit[330] & reg_re & !reg_error;
+  assign dio_pad_attr_6_re = addr_hit[347] & reg_re & !reg_error;
 
-  assign dio_pad_attr_7_we = addr_hit[331] & reg_we & !reg_error;
+  assign dio_pad_attr_7_we = addr_hit[348] & reg_we & !reg_error;
   assign dio_pad_attr_7_wd = reg_wdata[12:0];
-  assign dio_pad_attr_7_re = addr_hit[331] & reg_re & !reg_error;
+  assign dio_pad_attr_7_re = addr_hit[348] & reg_re & !reg_error;
 
-  assign dio_pad_attr_8_we = addr_hit[332] & reg_we & !reg_error;
+  assign dio_pad_attr_8_we = addr_hit[349] & reg_we & !reg_error;
   assign dio_pad_attr_8_wd = reg_wdata[12:0];
-  assign dio_pad_attr_8_re = addr_hit[332] & reg_re & !reg_error;
+  assign dio_pad_attr_8_re = addr_hit[349] & reg_re & !reg_error;
 
-  assign dio_pad_attr_9_we = addr_hit[333] & reg_we & !reg_error;
+  assign dio_pad_attr_9_we = addr_hit[350] & reg_we & !reg_error;
   assign dio_pad_attr_9_wd = reg_wdata[12:0];
-  assign dio_pad_attr_9_re = addr_hit[333] & reg_re & !reg_error;
+  assign dio_pad_attr_9_re = addr_hit[350] & reg_re & !reg_error;
 
-  assign dio_pad_attr_10_we = addr_hit[334] & reg_we & !reg_error;
+  assign dio_pad_attr_10_we = addr_hit[351] & reg_we & !reg_error;
   assign dio_pad_attr_10_wd = reg_wdata[12:0];
-  assign dio_pad_attr_10_re = addr_hit[334] & reg_re & !reg_error;
+  assign dio_pad_attr_10_re = addr_hit[351] & reg_re & !reg_error;
 
-  assign dio_pad_attr_11_we = addr_hit[335] & reg_we & !reg_error;
+  assign dio_pad_attr_11_we = addr_hit[352] & reg_we & !reg_error;
   assign dio_pad_attr_11_wd = reg_wdata[12:0];
-  assign dio_pad_attr_11_re = addr_hit[335] & reg_re & !reg_error;
+  assign dio_pad_attr_11_re = addr_hit[352] & reg_re & !reg_error;
 
-  assign dio_pad_attr_12_we = addr_hit[336] & reg_we & !reg_error;
+  assign dio_pad_attr_12_we = addr_hit[353] & reg_we & !reg_error;
   assign dio_pad_attr_12_wd = reg_wdata[12:0];
-  assign dio_pad_attr_12_re = addr_hit[336] & reg_re & !reg_error;
+  assign dio_pad_attr_12_re = addr_hit[353] & reg_re & !reg_error;
 
-  assign dio_pad_attr_13_we = addr_hit[337] & reg_we & !reg_error;
+  assign dio_pad_attr_13_we = addr_hit[354] & reg_we & !reg_error;
   assign dio_pad_attr_13_wd = reg_wdata[12:0];
-  assign dio_pad_attr_13_re = addr_hit[337] & reg_re & !reg_error;
+  assign dio_pad_attr_13_re = addr_hit[354] & reg_re & !reg_error;
 
-  assign dio_pad_attr_14_we = addr_hit[338] & reg_we & !reg_error;
+  assign dio_pad_attr_14_we = addr_hit[355] & reg_we & !reg_error;
   assign dio_pad_attr_14_wd = reg_wdata[12:0];
-  assign dio_pad_attr_14_re = addr_hit[338] & reg_re & !reg_error;
+  assign dio_pad_attr_14_re = addr_hit[355] & reg_re & !reg_error;
 
-  assign dio_pad_attr_15_we = addr_hit[339] & reg_we & !reg_error;
+  assign dio_pad_attr_15_we = addr_hit[356] & reg_we & !reg_error;
   assign dio_pad_attr_15_wd = reg_wdata[12:0];
-  assign dio_pad_attr_15_re = addr_hit[339] & reg_re & !reg_error;
+  assign dio_pad_attr_15_re = addr_hit[356] & reg_re & !reg_error;
 
-  assign dio_pad_attr_16_we = addr_hit[340] & reg_we & !reg_error;
+  assign dio_pad_attr_16_we = addr_hit[357] & reg_we & !reg_error;
   assign dio_pad_attr_16_wd = reg_wdata[12:0];
-  assign dio_pad_attr_16_re = addr_hit[340] & reg_re & !reg_error;
+  assign dio_pad_attr_16_re = addr_hit[357] & reg_re & !reg_error;
 
-  assign dio_pad_attr_17_we = addr_hit[341] & reg_we & !reg_error;
+  assign dio_pad_attr_17_we = addr_hit[358] & reg_we & !reg_error;
   assign dio_pad_attr_17_wd = reg_wdata[12:0];
-  assign dio_pad_attr_17_re = addr_hit[341] & reg_re & !reg_error;
+  assign dio_pad_attr_17_re = addr_hit[358] & reg_re & !reg_error;
 
-  assign dio_pad_attr_18_we = addr_hit[342] & reg_we & !reg_error;
+  assign dio_pad_attr_18_we = addr_hit[359] & reg_we & !reg_error;
   assign dio_pad_attr_18_wd = reg_wdata[12:0];
-  assign dio_pad_attr_18_re = addr_hit[342] & reg_re & !reg_error;
+  assign dio_pad_attr_18_re = addr_hit[359] & reg_re & !reg_error;
 
-  assign dio_pad_attr_19_we = addr_hit[343] & reg_we & !reg_error;
+  assign dio_pad_attr_19_we = addr_hit[360] & reg_we & !reg_error;
   assign dio_pad_attr_19_wd = reg_wdata[12:0];
-  assign dio_pad_attr_19_re = addr_hit[343] & reg_re & !reg_error;
+  assign dio_pad_attr_19_re = addr_hit[360] & reg_re & !reg_error;
 
-  assign dio_pad_attr_20_we = addr_hit[344] & reg_we & !reg_error;
+  assign dio_pad_attr_20_we = addr_hit[361] & reg_we & !reg_error;
   assign dio_pad_attr_20_wd = reg_wdata[12:0];
-  assign dio_pad_attr_20_re = addr_hit[344] & reg_re & !reg_error;
+  assign dio_pad_attr_20_re = addr_hit[361] & reg_re & !reg_error;
 
-  assign dio_pad_attr_21_we = addr_hit[345] & reg_we & !reg_error;
+  assign dio_pad_attr_21_we = addr_hit[362] & reg_we & !reg_error;
   assign dio_pad_attr_21_wd = reg_wdata[12:0];
-  assign dio_pad_attr_21_re = addr_hit[345] & reg_re & !reg_error;
+  assign dio_pad_attr_21_re = addr_hit[362] & reg_re & !reg_error;
 
-  assign mio_pad_sleep_status_0_en_0_we = addr_hit[346] & reg_we & !reg_error;
+  assign dio_pad_attr_22_we = addr_hit[363] & reg_we & !reg_error;
+  assign dio_pad_attr_22_wd = reg_wdata[12:0];
+  assign dio_pad_attr_22_re = addr_hit[363] & reg_re & !reg_error;
+
+  assign mio_pad_sleep_status_0_en_0_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_0_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_status_0_en_1_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_1_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_1_wd = reg_wdata[1];
 
-  assign mio_pad_sleep_status_0_en_2_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_2_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_2_wd = reg_wdata[2];
 
-  assign mio_pad_sleep_status_0_en_3_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_3_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_3_wd = reg_wdata[3];
 
-  assign mio_pad_sleep_status_0_en_4_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_4_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_4_wd = reg_wdata[4];
 
-  assign mio_pad_sleep_status_0_en_5_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_5_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_5_wd = reg_wdata[5];
 
-  assign mio_pad_sleep_status_0_en_6_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_6_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_6_wd = reg_wdata[6];
 
-  assign mio_pad_sleep_status_0_en_7_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_7_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_7_wd = reg_wdata[7];
 
-  assign mio_pad_sleep_status_0_en_8_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_8_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_8_wd = reg_wdata[8];
 
-  assign mio_pad_sleep_status_0_en_9_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_9_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_9_wd = reg_wdata[9];
 
-  assign mio_pad_sleep_status_0_en_10_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_10_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_10_wd = reg_wdata[10];
 
-  assign mio_pad_sleep_status_0_en_11_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_11_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_11_wd = reg_wdata[11];
 
-  assign mio_pad_sleep_status_0_en_12_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_12_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_12_wd = reg_wdata[12];
 
-  assign mio_pad_sleep_status_0_en_13_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_13_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_13_wd = reg_wdata[13];
 
-  assign mio_pad_sleep_status_0_en_14_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_14_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_14_wd = reg_wdata[14];
 
-  assign mio_pad_sleep_status_0_en_15_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_15_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_15_wd = reg_wdata[15];
 
-  assign mio_pad_sleep_status_0_en_16_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_16_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_16_wd = reg_wdata[16];
 
-  assign mio_pad_sleep_status_0_en_17_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_17_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_17_wd = reg_wdata[17];
 
-  assign mio_pad_sleep_status_0_en_18_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_18_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_18_wd = reg_wdata[18];
 
-  assign mio_pad_sleep_status_0_en_19_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_19_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_19_wd = reg_wdata[19];
 
-  assign mio_pad_sleep_status_0_en_20_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_20_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_20_wd = reg_wdata[20];
 
-  assign mio_pad_sleep_status_0_en_21_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_21_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_21_wd = reg_wdata[21];
 
-  assign mio_pad_sleep_status_0_en_22_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_22_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_22_wd = reg_wdata[22];
 
-  assign mio_pad_sleep_status_0_en_23_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_23_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_23_wd = reg_wdata[23];
 
-  assign mio_pad_sleep_status_0_en_24_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_24_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_24_wd = reg_wdata[24];
 
-  assign mio_pad_sleep_status_0_en_25_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_25_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_25_wd = reg_wdata[25];
 
-  assign mio_pad_sleep_status_0_en_26_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_26_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_26_wd = reg_wdata[26];
 
-  assign mio_pad_sleep_status_0_en_27_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_27_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_27_wd = reg_wdata[27];
 
-  assign mio_pad_sleep_status_0_en_28_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_28_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_28_wd = reg_wdata[28];
 
-  assign mio_pad_sleep_status_0_en_29_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_29_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_29_wd = reg_wdata[29];
 
-  assign mio_pad_sleep_status_0_en_30_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_30_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_30_wd = reg_wdata[30];
 
-  assign mio_pad_sleep_status_0_en_31_we = addr_hit[346] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_0_en_31_we = addr_hit[364] & reg_we & !reg_error;
   assign mio_pad_sleep_status_0_en_31_wd = reg_wdata[31];
 
-  assign mio_pad_sleep_status_1_en_32_we = addr_hit[347] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_32_we = addr_hit[365] & reg_we & !reg_error;
   assign mio_pad_sleep_status_1_en_32_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_status_1_en_33_we = addr_hit[347] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_33_we = addr_hit[365] & reg_we & !reg_error;
   assign mio_pad_sleep_status_1_en_33_wd = reg_wdata[1];
 
-  assign mio_pad_sleep_status_1_en_34_we = addr_hit[347] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_34_we = addr_hit[365] & reg_we & !reg_error;
   assign mio_pad_sleep_status_1_en_34_wd = reg_wdata[2];
 
-  assign mio_pad_sleep_status_1_en_35_we = addr_hit[347] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_35_we = addr_hit[365] & reg_we & !reg_error;
   assign mio_pad_sleep_status_1_en_35_wd = reg_wdata[3];
 
-  assign mio_pad_sleep_status_1_en_36_we = addr_hit[347] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_36_we = addr_hit[365] & reg_we & !reg_error;
   assign mio_pad_sleep_status_1_en_36_wd = reg_wdata[4];
 
-  assign mio_pad_sleep_status_1_en_37_we = addr_hit[347] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_37_we = addr_hit[365] & reg_we & !reg_error;
   assign mio_pad_sleep_status_1_en_37_wd = reg_wdata[5];
 
-  assign mio_pad_sleep_status_1_en_38_we = addr_hit[347] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_38_we = addr_hit[365] & reg_we & !reg_error;
   assign mio_pad_sleep_status_1_en_38_wd = reg_wdata[6];
 
-  assign mio_pad_sleep_status_1_en_39_we = addr_hit[347] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_39_we = addr_hit[365] & reg_we & !reg_error;
   assign mio_pad_sleep_status_1_en_39_wd = reg_wdata[7];
 
-  assign mio_pad_sleep_status_1_en_40_we = addr_hit[347] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_40_we = addr_hit[365] & reg_we & !reg_error;
   assign mio_pad_sleep_status_1_en_40_wd = reg_wdata[8];
 
-  assign mio_pad_sleep_status_1_en_41_we = addr_hit[347] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_41_we = addr_hit[365] & reg_we & !reg_error;
   assign mio_pad_sleep_status_1_en_41_wd = reg_wdata[9];
 
-  assign mio_pad_sleep_status_1_en_42_we = addr_hit[347] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_42_we = addr_hit[365] & reg_we & !reg_error;
   assign mio_pad_sleep_status_1_en_42_wd = reg_wdata[10];
 
-  assign mio_pad_sleep_regwen_0_we = addr_hit[348] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_43_we = addr_hit[365] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_43_wd = reg_wdata[11];
+
+  assign mio_pad_sleep_status_1_en_44_we = addr_hit[365] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_44_wd = reg_wdata[12];
+
+  assign mio_pad_sleep_status_1_en_45_we = addr_hit[365] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_45_wd = reg_wdata[13];
+
+  assign mio_pad_sleep_status_1_en_46_we = addr_hit[365] & reg_we & !reg_error;
+  assign mio_pad_sleep_status_1_en_46_wd = reg_wdata[14];
+
+  assign mio_pad_sleep_regwen_0_we = addr_hit[366] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_0_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_1_we = addr_hit[349] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_1_we = addr_hit[367] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_1_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_2_we = addr_hit[350] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_2_we = addr_hit[368] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_2_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_3_we = addr_hit[351] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_3_we = addr_hit[369] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_3_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_4_we = addr_hit[352] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_4_we = addr_hit[370] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_4_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_5_we = addr_hit[353] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_5_we = addr_hit[371] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_5_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_6_we = addr_hit[354] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_6_we = addr_hit[372] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_6_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_7_we = addr_hit[355] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_7_we = addr_hit[373] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_7_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_8_we = addr_hit[356] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_8_we = addr_hit[374] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_8_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_9_we = addr_hit[357] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_9_we = addr_hit[375] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_9_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_10_we = addr_hit[358] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_10_we = addr_hit[376] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_10_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_11_we = addr_hit[359] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_11_we = addr_hit[377] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_11_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_12_we = addr_hit[360] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_12_we = addr_hit[378] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_12_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_13_we = addr_hit[361] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_13_we = addr_hit[379] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_13_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_14_we = addr_hit[362] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_14_we = addr_hit[380] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_14_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_15_we = addr_hit[363] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_15_we = addr_hit[381] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_15_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_16_we = addr_hit[364] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_16_we = addr_hit[382] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_16_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_17_we = addr_hit[365] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_17_we = addr_hit[383] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_17_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_18_we = addr_hit[366] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_18_we = addr_hit[384] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_18_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_19_we = addr_hit[367] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_19_we = addr_hit[385] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_19_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_20_we = addr_hit[368] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_20_we = addr_hit[386] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_20_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_21_we = addr_hit[369] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_21_we = addr_hit[387] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_21_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_22_we = addr_hit[370] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_22_we = addr_hit[388] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_22_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_23_we = addr_hit[371] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_23_we = addr_hit[389] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_23_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_24_we = addr_hit[372] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_24_we = addr_hit[390] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_24_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_25_we = addr_hit[373] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_25_we = addr_hit[391] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_25_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_26_we = addr_hit[374] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_26_we = addr_hit[392] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_26_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_27_we = addr_hit[375] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_27_we = addr_hit[393] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_27_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_28_we = addr_hit[376] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_28_we = addr_hit[394] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_28_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_29_we = addr_hit[377] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_29_we = addr_hit[395] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_29_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_30_we = addr_hit[378] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_30_we = addr_hit[396] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_30_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_31_we = addr_hit[379] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_31_we = addr_hit[397] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_31_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_32_we = addr_hit[380] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_32_we = addr_hit[398] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_32_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_33_we = addr_hit[381] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_33_we = addr_hit[399] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_33_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_34_we = addr_hit[382] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_34_we = addr_hit[400] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_34_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_35_we = addr_hit[383] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_35_we = addr_hit[401] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_35_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_36_we = addr_hit[384] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_36_we = addr_hit[402] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_36_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_37_we = addr_hit[385] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_37_we = addr_hit[403] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_37_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_38_we = addr_hit[386] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_38_we = addr_hit[404] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_38_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_39_we = addr_hit[387] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_39_we = addr_hit[405] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_39_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_40_we = addr_hit[388] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_40_we = addr_hit[406] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_40_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_41_we = addr_hit[389] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_41_we = addr_hit[407] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_41_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_42_we = addr_hit[390] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_42_we = addr_hit[408] & reg_we & !reg_error;
   assign mio_pad_sleep_regwen_42_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_0_we = addr_hit[391] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_43_we = addr_hit[409] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_43_wd = reg_wdata[0];
+
+  assign mio_pad_sleep_regwen_44_we = addr_hit[410] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_44_wd = reg_wdata[0];
+
+  assign mio_pad_sleep_regwen_45_we = addr_hit[411] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_45_wd = reg_wdata[0];
+
+  assign mio_pad_sleep_regwen_46_we = addr_hit[412] & reg_we & !reg_error;
+  assign mio_pad_sleep_regwen_46_wd = reg_wdata[0];
+
+  assign mio_pad_sleep_en_0_we = addr_hit[413] & reg_we & !reg_error;
   assign mio_pad_sleep_en_0_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_1_we = addr_hit[392] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_1_we = addr_hit[414] & reg_we & !reg_error;
   assign mio_pad_sleep_en_1_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_2_we = addr_hit[393] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_2_we = addr_hit[415] & reg_we & !reg_error;
   assign mio_pad_sleep_en_2_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_3_we = addr_hit[394] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_3_we = addr_hit[416] & reg_we & !reg_error;
   assign mio_pad_sleep_en_3_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_4_we = addr_hit[395] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_4_we = addr_hit[417] & reg_we & !reg_error;
   assign mio_pad_sleep_en_4_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_5_we = addr_hit[396] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_5_we = addr_hit[418] & reg_we & !reg_error;
   assign mio_pad_sleep_en_5_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_6_we = addr_hit[397] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_6_we = addr_hit[419] & reg_we & !reg_error;
   assign mio_pad_sleep_en_6_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_7_we = addr_hit[398] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_7_we = addr_hit[420] & reg_we & !reg_error;
   assign mio_pad_sleep_en_7_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_8_we = addr_hit[399] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_8_we = addr_hit[421] & reg_we & !reg_error;
   assign mio_pad_sleep_en_8_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_9_we = addr_hit[400] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_9_we = addr_hit[422] & reg_we & !reg_error;
   assign mio_pad_sleep_en_9_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_10_we = addr_hit[401] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_10_we = addr_hit[423] & reg_we & !reg_error;
   assign mio_pad_sleep_en_10_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_11_we = addr_hit[402] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_11_we = addr_hit[424] & reg_we & !reg_error;
   assign mio_pad_sleep_en_11_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_12_we = addr_hit[403] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_12_we = addr_hit[425] & reg_we & !reg_error;
   assign mio_pad_sleep_en_12_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_13_we = addr_hit[404] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_13_we = addr_hit[426] & reg_we & !reg_error;
   assign mio_pad_sleep_en_13_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_14_we = addr_hit[405] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_14_we = addr_hit[427] & reg_we & !reg_error;
   assign mio_pad_sleep_en_14_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_15_we = addr_hit[406] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_15_we = addr_hit[428] & reg_we & !reg_error;
   assign mio_pad_sleep_en_15_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_16_we = addr_hit[407] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_16_we = addr_hit[429] & reg_we & !reg_error;
   assign mio_pad_sleep_en_16_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_17_we = addr_hit[408] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_17_we = addr_hit[430] & reg_we & !reg_error;
   assign mio_pad_sleep_en_17_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_18_we = addr_hit[409] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_18_we = addr_hit[431] & reg_we & !reg_error;
   assign mio_pad_sleep_en_18_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_19_we = addr_hit[410] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_19_we = addr_hit[432] & reg_we & !reg_error;
   assign mio_pad_sleep_en_19_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_20_we = addr_hit[411] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_20_we = addr_hit[433] & reg_we & !reg_error;
   assign mio_pad_sleep_en_20_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_21_we = addr_hit[412] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_21_we = addr_hit[434] & reg_we & !reg_error;
   assign mio_pad_sleep_en_21_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_22_we = addr_hit[413] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_22_we = addr_hit[435] & reg_we & !reg_error;
   assign mio_pad_sleep_en_22_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_23_we = addr_hit[414] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_23_we = addr_hit[436] & reg_we & !reg_error;
   assign mio_pad_sleep_en_23_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_24_we = addr_hit[415] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_24_we = addr_hit[437] & reg_we & !reg_error;
   assign mio_pad_sleep_en_24_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_25_we = addr_hit[416] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_25_we = addr_hit[438] & reg_we & !reg_error;
   assign mio_pad_sleep_en_25_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_26_we = addr_hit[417] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_26_we = addr_hit[439] & reg_we & !reg_error;
   assign mio_pad_sleep_en_26_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_27_we = addr_hit[418] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_27_we = addr_hit[440] & reg_we & !reg_error;
   assign mio_pad_sleep_en_27_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_28_we = addr_hit[419] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_28_we = addr_hit[441] & reg_we & !reg_error;
   assign mio_pad_sleep_en_28_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_29_we = addr_hit[420] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_29_we = addr_hit[442] & reg_we & !reg_error;
   assign mio_pad_sleep_en_29_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_30_we = addr_hit[421] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_30_we = addr_hit[443] & reg_we & !reg_error;
   assign mio_pad_sleep_en_30_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_31_we = addr_hit[422] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_31_we = addr_hit[444] & reg_we & !reg_error;
   assign mio_pad_sleep_en_31_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_32_we = addr_hit[423] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_32_we = addr_hit[445] & reg_we & !reg_error;
   assign mio_pad_sleep_en_32_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_33_we = addr_hit[424] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_33_we = addr_hit[446] & reg_we & !reg_error;
   assign mio_pad_sleep_en_33_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_34_we = addr_hit[425] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_34_we = addr_hit[447] & reg_we & !reg_error;
   assign mio_pad_sleep_en_34_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_35_we = addr_hit[426] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_35_we = addr_hit[448] & reg_we & !reg_error;
   assign mio_pad_sleep_en_35_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_36_we = addr_hit[427] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_36_we = addr_hit[449] & reg_we & !reg_error;
   assign mio_pad_sleep_en_36_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_37_we = addr_hit[428] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_37_we = addr_hit[450] & reg_we & !reg_error;
   assign mio_pad_sleep_en_37_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_38_we = addr_hit[429] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_38_we = addr_hit[451] & reg_we & !reg_error;
   assign mio_pad_sleep_en_38_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_39_we = addr_hit[430] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_39_we = addr_hit[452] & reg_we & !reg_error;
   assign mio_pad_sleep_en_39_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_40_we = addr_hit[431] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_40_we = addr_hit[453] & reg_we & !reg_error;
   assign mio_pad_sleep_en_40_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_41_we = addr_hit[432] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_41_we = addr_hit[454] & reg_we & !reg_error;
   assign mio_pad_sleep_en_41_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_42_we = addr_hit[433] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_42_we = addr_hit[455] & reg_we & !reg_error;
   assign mio_pad_sleep_en_42_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_mode_0_we = addr_hit[434] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_43_we = addr_hit[456] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_43_wd = reg_wdata[0];
+
+  assign mio_pad_sleep_en_44_we = addr_hit[457] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_44_wd = reg_wdata[0];
+
+  assign mio_pad_sleep_en_45_we = addr_hit[458] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_45_wd = reg_wdata[0];
+
+  assign mio_pad_sleep_en_46_we = addr_hit[459] & reg_we & !reg_error;
+  assign mio_pad_sleep_en_46_wd = reg_wdata[0];
+
+  assign mio_pad_sleep_mode_0_we = addr_hit[460] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_0_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_1_we = addr_hit[435] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_1_we = addr_hit[461] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_1_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_2_we = addr_hit[436] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_2_we = addr_hit[462] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_2_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_3_we = addr_hit[437] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_3_we = addr_hit[463] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_3_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_4_we = addr_hit[438] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_4_we = addr_hit[464] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_4_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_5_we = addr_hit[439] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_5_we = addr_hit[465] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_5_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_6_we = addr_hit[440] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_6_we = addr_hit[466] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_6_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_7_we = addr_hit[441] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_7_we = addr_hit[467] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_7_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_8_we = addr_hit[442] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_8_we = addr_hit[468] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_8_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_9_we = addr_hit[443] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_9_we = addr_hit[469] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_9_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_10_we = addr_hit[444] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_10_we = addr_hit[470] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_10_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_11_we = addr_hit[445] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_11_we = addr_hit[471] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_11_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_12_we = addr_hit[446] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_12_we = addr_hit[472] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_12_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_13_we = addr_hit[447] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_13_we = addr_hit[473] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_13_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_14_we = addr_hit[448] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_14_we = addr_hit[474] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_14_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_15_we = addr_hit[449] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_15_we = addr_hit[475] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_15_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_16_we = addr_hit[450] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_16_we = addr_hit[476] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_16_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_17_we = addr_hit[451] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_17_we = addr_hit[477] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_17_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_18_we = addr_hit[452] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_18_we = addr_hit[478] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_18_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_19_we = addr_hit[453] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_19_we = addr_hit[479] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_19_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_20_we = addr_hit[454] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_20_we = addr_hit[480] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_20_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_21_we = addr_hit[455] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_21_we = addr_hit[481] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_21_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_22_we = addr_hit[456] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_22_we = addr_hit[482] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_22_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_23_we = addr_hit[457] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_23_we = addr_hit[483] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_23_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_24_we = addr_hit[458] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_24_we = addr_hit[484] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_24_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_25_we = addr_hit[459] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_25_we = addr_hit[485] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_25_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_26_we = addr_hit[460] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_26_we = addr_hit[486] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_26_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_27_we = addr_hit[461] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_27_we = addr_hit[487] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_27_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_28_we = addr_hit[462] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_28_we = addr_hit[488] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_28_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_29_we = addr_hit[463] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_29_we = addr_hit[489] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_29_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_30_we = addr_hit[464] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_30_we = addr_hit[490] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_30_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_31_we = addr_hit[465] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_31_we = addr_hit[491] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_31_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_32_we = addr_hit[466] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_32_we = addr_hit[492] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_32_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_33_we = addr_hit[467] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_33_we = addr_hit[493] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_33_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_34_we = addr_hit[468] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_34_we = addr_hit[494] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_34_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_35_we = addr_hit[469] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_35_we = addr_hit[495] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_35_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_36_we = addr_hit[470] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_36_we = addr_hit[496] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_36_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_37_we = addr_hit[471] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_37_we = addr_hit[497] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_37_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_38_we = addr_hit[472] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_38_we = addr_hit[498] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_38_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_39_we = addr_hit[473] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_39_we = addr_hit[499] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_39_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_40_we = addr_hit[474] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_40_we = addr_hit[500] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_40_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_41_we = addr_hit[475] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_41_we = addr_hit[501] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_41_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_42_we = addr_hit[476] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_42_we = addr_hit[502] & reg_we & !reg_error;
   assign mio_pad_sleep_mode_42_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_status_en_0_we = addr_hit[477] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_43_we = addr_hit[503] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_43_wd = reg_wdata[1:0];
+
+  assign mio_pad_sleep_mode_44_we = addr_hit[504] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_44_wd = reg_wdata[1:0];
+
+  assign mio_pad_sleep_mode_45_we = addr_hit[505] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_45_wd = reg_wdata[1:0];
+
+  assign mio_pad_sleep_mode_46_we = addr_hit[506] & reg_we & !reg_error;
+  assign mio_pad_sleep_mode_46_wd = reg_wdata[1:0];
+
+  assign dio_pad_sleep_status_en_0_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_0_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_status_en_1_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_1_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_1_wd = reg_wdata[1];
 
-  assign dio_pad_sleep_status_en_2_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_2_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_2_wd = reg_wdata[2];
 
-  assign dio_pad_sleep_status_en_3_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_3_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_3_wd = reg_wdata[3];
 
-  assign dio_pad_sleep_status_en_4_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_4_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_4_wd = reg_wdata[4];
 
-  assign dio_pad_sleep_status_en_5_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_5_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_5_wd = reg_wdata[5];
 
-  assign dio_pad_sleep_status_en_6_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_6_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_6_wd = reg_wdata[6];
 
-  assign dio_pad_sleep_status_en_7_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_7_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_7_wd = reg_wdata[7];
 
-  assign dio_pad_sleep_status_en_8_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_8_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_8_wd = reg_wdata[8];
 
-  assign dio_pad_sleep_status_en_9_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_9_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_9_wd = reg_wdata[9];
 
-  assign dio_pad_sleep_status_en_10_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_10_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_10_wd = reg_wdata[10];
 
-  assign dio_pad_sleep_status_en_11_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_11_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_11_wd = reg_wdata[11];
 
-  assign dio_pad_sleep_status_en_12_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_12_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_12_wd = reg_wdata[12];
 
-  assign dio_pad_sleep_status_en_13_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_13_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_13_wd = reg_wdata[13];
 
-  assign dio_pad_sleep_status_en_14_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_14_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_14_wd = reg_wdata[14];
 
-  assign dio_pad_sleep_status_en_15_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_15_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_15_wd = reg_wdata[15];
 
-  assign dio_pad_sleep_status_en_16_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_16_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_16_wd = reg_wdata[16];
 
-  assign dio_pad_sleep_status_en_17_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_17_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_17_wd = reg_wdata[17];
 
-  assign dio_pad_sleep_status_en_18_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_18_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_18_wd = reg_wdata[18];
 
-  assign dio_pad_sleep_status_en_19_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_19_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_19_wd = reg_wdata[19];
 
-  assign dio_pad_sleep_status_en_20_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_20_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_20_wd = reg_wdata[20];
 
-  assign dio_pad_sleep_status_en_21_we = addr_hit[477] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_21_we = addr_hit[507] & reg_we & !reg_error;
   assign dio_pad_sleep_status_en_21_wd = reg_wdata[21];
 
-  assign dio_pad_sleep_regwen_0_we = addr_hit[478] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_22_we = addr_hit[507] & reg_we & !reg_error;
+  assign dio_pad_sleep_status_en_22_wd = reg_wdata[22];
+
+  assign dio_pad_sleep_regwen_0_we = addr_hit[508] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_0_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_1_we = addr_hit[479] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_1_we = addr_hit[509] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_1_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_2_we = addr_hit[480] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_2_we = addr_hit[510] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_2_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_3_we = addr_hit[481] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_3_we = addr_hit[511] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_3_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_4_we = addr_hit[482] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_4_we = addr_hit[512] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_4_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_5_we = addr_hit[483] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_5_we = addr_hit[513] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_5_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_6_we = addr_hit[484] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_6_we = addr_hit[514] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_6_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_7_we = addr_hit[485] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_7_we = addr_hit[515] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_7_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_8_we = addr_hit[486] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_8_we = addr_hit[516] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_8_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_9_we = addr_hit[487] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_9_we = addr_hit[517] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_9_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_10_we = addr_hit[488] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_10_we = addr_hit[518] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_10_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_11_we = addr_hit[489] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_11_we = addr_hit[519] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_11_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_12_we = addr_hit[490] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_12_we = addr_hit[520] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_12_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_13_we = addr_hit[491] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_13_we = addr_hit[521] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_13_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_14_we = addr_hit[492] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_14_we = addr_hit[522] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_14_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_15_we = addr_hit[493] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_15_we = addr_hit[523] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_15_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_16_we = addr_hit[494] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_16_we = addr_hit[524] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_16_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_17_we = addr_hit[495] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_17_we = addr_hit[525] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_17_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_18_we = addr_hit[496] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_18_we = addr_hit[526] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_18_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_19_we = addr_hit[497] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_19_we = addr_hit[527] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_19_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_20_we = addr_hit[498] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_20_we = addr_hit[528] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_20_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_21_we = addr_hit[499] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_21_we = addr_hit[529] & reg_we & !reg_error;
   assign dio_pad_sleep_regwen_21_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_0_we = addr_hit[500] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_22_we = addr_hit[530] & reg_we & !reg_error;
+  assign dio_pad_sleep_regwen_22_wd = reg_wdata[0];
+
+  assign dio_pad_sleep_en_0_we = addr_hit[531] & reg_we & !reg_error;
   assign dio_pad_sleep_en_0_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_1_we = addr_hit[501] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_1_we = addr_hit[532] & reg_we & !reg_error;
   assign dio_pad_sleep_en_1_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_2_we = addr_hit[502] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_2_we = addr_hit[533] & reg_we & !reg_error;
   assign dio_pad_sleep_en_2_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_3_we = addr_hit[503] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_3_we = addr_hit[534] & reg_we & !reg_error;
   assign dio_pad_sleep_en_3_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_4_we = addr_hit[504] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_4_we = addr_hit[535] & reg_we & !reg_error;
   assign dio_pad_sleep_en_4_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_5_we = addr_hit[505] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_5_we = addr_hit[536] & reg_we & !reg_error;
   assign dio_pad_sleep_en_5_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_6_we = addr_hit[506] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_6_we = addr_hit[537] & reg_we & !reg_error;
   assign dio_pad_sleep_en_6_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_7_we = addr_hit[507] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_7_we = addr_hit[538] & reg_we & !reg_error;
   assign dio_pad_sleep_en_7_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_8_we = addr_hit[508] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_8_we = addr_hit[539] & reg_we & !reg_error;
   assign dio_pad_sleep_en_8_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_9_we = addr_hit[509] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_9_we = addr_hit[540] & reg_we & !reg_error;
   assign dio_pad_sleep_en_9_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_10_we = addr_hit[510] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_10_we = addr_hit[541] & reg_we & !reg_error;
   assign dio_pad_sleep_en_10_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_11_we = addr_hit[511] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_11_we = addr_hit[542] & reg_we & !reg_error;
   assign dio_pad_sleep_en_11_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_12_we = addr_hit[512] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_12_we = addr_hit[543] & reg_we & !reg_error;
   assign dio_pad_sleep_en_12_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_13_we = addr_hit[513] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_13_we = addr_hit[544] & reg_we & !reg_error;
   assign dio_pad_sleep_en_13_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_14_we = addr_hit[514] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_14_we = addr_hit[545] & reg_we & !reg_error;
   assign dio_pad_sleep_en_14_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_15_we = addr_hit[515] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_15_we = addr_hit[546] & reg_we & !reg_error;
   assign dio_pad_sleep_en_15_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_16_we = addr_hit[516] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_16_we = addr_hit[547] & reg_we & !reg_error;
   assign dio_pad_sleep_en_16_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_17_we = addr_hit[517] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_17_we = addr_hit[548] & reg_we & !reg_error;
   assign dio_pad_sleep_en_17_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_18_we = addr_hit[518] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_18_we = addr_hit[549] & reg_we & !reg_error;
   assign dio_pad_sleep_en_18_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_19_we = addr_hit[519] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_19_we = addr_hit[550] & reg_we & !reg_error;
   assign dio_pad_sleep_en_19_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_20_we = addr_hit[520] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_20_we = addr_hit[551] & reg_we & !reg_error;
   assign dio_pad_sleep_en_20_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_21_we = addr_hit[521] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_21_we = addr_hit[552] & reg_we & !reg_error;
   assign dio_pad_sleep_en_21_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_mode_0_we = addr_hit[522] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_22_we = addr_hit[553] & reg_we & !reg_error;
+  assign dio_pad_sleep_en_22_wd = reg_wdata[0];
+
+  assign dio_pad_sleep_mode_0_we = addr_hit[554] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_0_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_1_we = addr_hit[523] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_1_we = addr_hit[555] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_1_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_2_we = addr_hit[524] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_2_we = addr_hit[556] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_2_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_3_we = addr_hit[525] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_3_we = addr_hit[557] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_3_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_4_we = addr_hit[526] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_4_we = addr_hit[558] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_4_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_5_we = addr_hit[527] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_5_we = addr_hit[559] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_5_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_6_we = addr_hit[528] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_6_we = addr_hit[560] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_6_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_7_we = addr_hit[529] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_7_we = addr_hit[561] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_7_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_8_we = addr_hit[530] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_8_we = addr_hit[562] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_8_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_9_we = addr_hit[531] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_9_we = addr_hit[563] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_9_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_10_we = addr_hit[532] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_10_we = addr_hit[564] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_10_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_11_we = addr_hit[533] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_11_we = addr_hit[565] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_11_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_12_we = addr_hit[534] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_12_we = addr_hit[566] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_12_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_13_we = addr_hit[535] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_13_we = addr_hit[567] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_13_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_14_we = addr_hit[536] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_14_we = addr_hit[568] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_14_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_15_we = addr_hit[537] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_15_we = addr_hit[569] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_15_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_16_we = addr_hit[538] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_16_we = addr_hit[570] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_16_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_17_we = addr_hit[539] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_17_we = addr_hit[571] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_17_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_18_we = addr_hit[540] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_18_we = addr_hit[572] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_18_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_19_we = addr_hit[541] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_19_we = addr_hit[573] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_19_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_20_we = addr_hit[542] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_20_we = addr_hit[574] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_20_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_21_we = addr_hit[543] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_21_we = addr_hit[575] & reg_we & !reg_error;
   assign dio_pad_sleep_mode_21_wd = reg_wdata[1:0];
 
-  assign wkup_detector_regwen_0_we = addr_hit[544] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_22_we = addr_hit[576] & reg_we & !reg_error;
+  assign dio_pad_sleep_mode_22_wd = reg_wdata[1:0];
+
+  assign wkup_detector_regwen_0_we = addr_hit[577] & reg_we & !reg_error;
   assign wkup_detector_regwen_0_wd = reg_wdata[0];
 
-  assign wkup_detector_regwen_1_we = addr_hit[545] & reg_we & !reg_error;
+  assign wkup_detector_regwen_1_we = addr_hit[578] & reg_we & !reg_error;
   assign wkup_detector_regwen_1_wd = reg_wdata[0];
 
-  assign wkup_detector_regwen_2_we = addr_hit[546] & reg_we & !reg_error;
+  assign wkup_detector_regwen_2_we = addr_hit[579] & reg_we & !reg_error;
   assign wkup_detector_regwen_2_wd = reg_wdata[0];
 
-  assign wkup_detector_regwen_3_we = addr_hit[547] & reg_we & !reg_error;
+  assign wkup_detector_regwen_3_we = addr_hit[580] & reg_we & !reg_error;
   assign wkup_detector_regwen_3_wd = reg_wdata[0];
 
-  assign wkup_detector_regwen_4_we = addr_hit[548] & reg_we & !reg_error;
+  assign wkup_detector_regwen_4_we = addr_hit[581] & reg_we & !reg_error;
   assign wkup_detector_regwen_4_wd = reg_wdata[0];
 
-  assign wkup_detector_regwen_5_we = addr_hit[549] & reg_we & !reg_error;
+  assign wkup_detector_regwen_5_we = addr_hit[582] & reg_we & !reg_error;
   assign wkup_detector_regwen_5_wd = reg_wdata[0];
 
-  assign wkup_detector_regwen_6_we = addr_hit[550] & reg_we & !reg_error;
+  assign wkup_detector_regwen_6_we = addr_hit[583] & reg_we & !reg_error;
   assign wkup_detector_regwen_6_wd = reg_wdata[0];
 
-  assign wkup_detector_regwen_7_we = addr_hit[551] & reg_we & !reg_error;
+  assign wkup_detector_regwen_7_we = addr_hit[584] & reg_we & !reg_error;
   assign wkup_detector_regwen_7_wd = reg_wdata[0];
 
-  assign wkup_detector_en_0_we = addr_hit[552] & reg_we & !reg_error;
+  assign wkup_detector_en_0_we = addr_hit[585] & reg_we & !reg_error;
   assign wkup_detector_en_0_wd = reg_wdata[0];
 
-  assign wkup_detector_en_1_we = addr_hit[553] & reg_we & !reg_error;
+  assign wkup_detector_en_1_we = addr_hit[586] & reg_we & !reg_error;
   assign wkup_detector_en_1_wd = reg_wdata[0];
 
-  assign wkup_detector_en_2_we = addr_hit[554] & reg_we & !reg_error;
+  assign wkup_detector_en_2_we = addr_hit[587] & reg_we & !reg_error;
   assign wkup_detector_en_2_wd = reg_wdata[0];
 
-  assign wkup_detector_en_3_we = addr_hit[555] & reg_we & !reg_error;
+  assign wkup_detector_en_3_we = addr_hit[588] & reg_we & !reg_error;
   assign wkup_detector_en_3_wd = reg_wdata[0];
 
-  assign wkup_detector_en_4_we = addr_hit[556] & reg_we & !reg_error;
+  assign wkup_detector_en_4_we = addr_hit[589] & reg_we & !reg_error;
   assign wkup_detector_en_4_wd = reg_wdata[0];
 
-  assign wkup_detector_en_5_we = addr_hit[557] & reg_we & !reg_error;
+  assign wkup_detector_en_5_we = addr_hit[590] & reg_we & !reg_error;
   assign wkup_detector_en_5_wd = reg_wdata[0];
 
-  assign wkup_detector_en_6_we = addr_hit[558] & reg_we & !reg_error;
+  assign wkup_detector_en_6_we = addr_hit[591] & reg_we & !reg_error;
   assign wkup_detector_en_6_wd = reg_wdata[0];
 
-  assign wkup_detector_en_7_we = addr_hit[559] & reg_we & !reg_error;
+  assign wkup_detector_en_7_we = addr_hit[592] & reg_we & !reg_error;
   assign wkup_detector_en_7_wd = reg_wdata[0];
 
-  assign wkup_detector_0_mode_0_we = addr_hit[560] & reg_we & !reg_error;
+  assign wkup_detector_0_mode_0_we = addr_hit[593] & reg_we & !reg_error;
   assign wkup_detector_0_mode_0_wd = reg_wdata[2:0];
 
-  assign wkup_detector_0_filter_0_we = addr_hit[560] & reg_we & !reg_error;
+  assign wkup_detector_0_filter_0_we = addr_hit[593] & reg_we & !reg_error;
   assign wkup_detector_0_filter_0_wd = reg_wdata[3];
 
-  assign wkup_detector_0_miodio_0_we = addr_hit[560] & reg_we & !reg_error;
+  assign wkup_detector_0_miodio_0_we = addr_hit[593] & reg_we & !reg_error;
   assign wkup_detector_0_miodio_0_wd = reg_wdata[4];
 
-  assign wkup_detector_1_mode_1_we = addr_hit[561] & reg_we & !reg_error;
+  assign wkup_detector_1_mode_1_we = addr_hit[594] & reg_we & !reg_error;
   assign wkup_detector_1_mode_1_wd = reg_wdata[2:0];
 
-  assign wkup_detector_1_filter_1_we = addr_hit[561] & reg_we & !reg_error;
+  assign wkup_detector_1_filter_1_we = addr_hit[594] & reg_we & !reg_error;
   assign wkup_detector_1_filter_1_wd = reg_wdata[3];
 
-  assign wkup_detector_1_miodio_1_we = addr_hit[561] & reg_we & !reg_error;
+  assign wkup_detector_1_miodio_1_we = addr_hit[594] & reg_we & !reg_error;
   assign wkup_detector_1_miodio_1_wd = reg_wdata[4];
 
-  assign wkup_detector_2_mode_2_we = addr_hit[562] & reg_we & !reg_error;
+  assign wkup_detector_2_mode_2_we = addr_hit[595] & reg_we & !reg_error;
   assign wkup_detector_2_mode_2_wd = reg_wdata[2:0];
 
-  assign wkup_detector_2_filter_2_we = addr_hit[562] & reg_we & !reg_error;
+  assign wkup_detector_2_filter_2_we = addr_hit[595] & reg_we & !reg_error;
   assign wkup_detector_2_filter_2_wd = reg_wdata[3];
 
-  assign wkup_detector_2_miodio_2_we = addr_hit[562] & reg_we & !reg_error;
+  assign wkup_detector_2_miodio_2_we = addr_hit[595] & reg_we & !reg_error;
   assign wkup_detector_2_miodio_2_wd = reg_wdata[4];
 
-  assign wkup_detector_3_mode_3_we = addr_hit[563] & reg_we & !reg_error;
+  assign wkup_detector_3_mode_3_we = addr_hit[596] & reg_we & !reg_error;
   assign wkup_detector_3_mode_3_wd = reg_wdata[2:0];
 
-  assign wkup_detector_3_filter_3_we = addr_hit[563] & reg_we & !reg_error;
+  assign wkup_detector_3_filter_3_we = addr_hit[596] & reg_we & !reg_error;
   assign wkup_detector_3_filter_3_wd = reg_wdata[3];
 
-  assign wkup_detector_3_miodio_3_we = addr_hit[563] & reg_we & !reg_error;
+  assign wkup_detector_3_miodio_3_we = addr_hit[596] & reg_we & !reg_error;
   assign wkup_detector_3_miodio_3_wd = reg_wdata[4];
 
-  assign wkup_detector_4_mode_4_we = addr_hit[564] & reg_we & !reg_error;
+  assign wkup_detector_4_mode_4_we = addr_hit[597] & reg_we & !reg_error;
   assign wkup_detector_4_mode_4_wd = reg_wdata[2:0];
 
-  assign wkup_detector_4_filter_4_we = addr_hit[564] & reg_we & !reg_error;
+  assign wkup_detector_4_filter_4_we = addr_hit[597] & reg_we & !reg_error;
   assign wkup_detector_4_filter_4_wd = reg_wdata[3];
 
-  assign wkup_detector_4_miodio_4_we = addr_hit[564] & reg_we & !reg_error;
+  assign wkup_detector_4_miodio_4_we = addr_hit[597] & reg_we & !reg_error;
   assign wkup_detector_4_miodio_4_wd = reg_wdata[4];
 
-  assign wkup_detector_5_mode_5_we = addr_hit[565] & reg_we & !reg_error;
+  assign wkup_detector_5_mode_5_we = addr_hit[598] & reg_we & !reg_error;
   assign wkup_detector_5_mode_5_wd = reg_wdata[2:0];
 
-  assign wkup_detector_5_filter_5_we = addr_hit[565] & reg_we & !reg_error;
+  assign wkup_detector_5_filter_5_we = addr_hit[598] & reg_we & !reg_error;
   assign wkup_detector_5_filter_5_wd = reg_wdata[3];
 
-  assign wkup_detector_5_miodio_5_we = addr_hit[565] & reg_we & !reg_error;
+  assign wkup_detector_5_miodio_5_we = addr_hit[598] & reg_we & !reg_error;
   assign wkup_detector_5_miodio_5_wd = reg_wdata[4];
 
-  assign wkup_detector_6_mode_6_we = addr_hit[566] & reg_we & !reg_error;
+  assign wkup_detector_6_mode_6_we = addr_hit[599] & reg_we & !reg_error;
   assign wkup_detector_6_mode_6_wd = reg_wdata[2:0];
 
-  assign wkup_detector_6_filter_6_we = addr_hit[566] & reg_we & !reg_error;
+  assign wkup_detector_6_filter_6_we = addr_hit[599] & reg_we & !reg_error;
   assign wkup_detector_6_filter_6_wd = reg_wdata[3];
 
-  assign wkup_detector_6_miodio_6_we = addr_hit[566] & reg_we & !reg_error;
+  assign wkup_detector_6_miodio_6_we = addr_hit[599] & reg_we & !reg_error;
   assign wkup_detector_6_miodio_6_wd = reg_wdata[4];
 
-  assign wkup_detector_7_mode_7_we = addr_hit[567] & reg_we & !reg_error;
+  assign wkup_detector_7_mode_7_we = addr_hit[600] & reg_we & !reg_error;
   assign wkup_detector_7_mode_7_wd = reg_wdata[2:0];
 
-  assign wkup_detector_7_filter_7_we = addr_hit[567] & reg_we & !reg_error;
+  assign wkup_detector_7_filter_7_we = addr_hit[600] & reg_we & !reg_error;
   assign wkup_detector_7_filter_7_wd = reg_wdata[3];
 
-  assign wkup_detector_7_miodio_7_we = addr_hit[567] & reg_we & !reg_error;
+  assign wkup_detector_7_miodio_7_we = addr_hit[600] & reg_we & !reg_error;
   assign wkup_detector_7_miodio_7_wd = reg_wdata[4];
 
-  assign wkup_detector_cnt_th_0_we = addr_hit[568] & reg_we & !reg_error;
+  assign wkup_detector_cnt_th_0_we = addr_hit[601] & reg_we & !reg_error;
   assign wkup_detector_cnt_th_0_wd = reg_wdata[7:0];
 
-  assign wkup_detector_cnt_th_1_we = addr_hit[569] & reg_we & !reg_error;
+  assign wkup_detector_cnt_th_1_we = addr_hit[602] & reg_we & !reg_error;
   assign wkup_detector_cnt_th_1_wd = reg_wdata[7:0];
 
-  assign wkup_detector_cnt_th_2_we = addr_hit[570] & reg_we & !reg_error;
+  assign wkup_detector_cnt_th_2_we = addr_hit[603] & reg_we & !reg_error;
   assign wkup_detector_cnt_th_2_wd = reg_wdata[7:0];
 
-  assign wkup_detector_cnt_th_3_we = addr_hit[571] & reg_we & !reg_error;
+  assign wkup_detector_cnt_th_3_we = addr_hit[604] & reg_we & !reg_error;
   assign wkup_detector_cnt_th_3_wd = reg_wdata[7:0];
 
-  assign wkup_detector_cnt_th_4_we = addr_hit[572] & reg_we & !reg_error;
+  assign wkup_detector_cnt_th_4_we = addr_hit[605] & reg_we & !reg_error;
   assign wkup_detector_cnt_th_4_wd = reg_wdata[7:0];
 
-  assign wkup_detector_cnt_th_5_we = addr_hit[573] & reg_we & !reg_error;
+  assign wkup_detector_cnt_th_5_we = addr_hit[606] & reg_we & !reg_error;
   assign wkup_detector_cnt_th_5_wd = reg_wdata[7:0];
 
-  assign wkup_detector_cnt_th_6_we = addr_hit[574] & reg_we & !reg_error;
+  assign wkup_detector_cnt_th_6_we = addr_hit[607] & reg_we & !reg_error;
   assign wkup_detector_cnt_th_6_wd = reg_wdata[7:0];
 
-  assign wkup_detector_cnt_th_7_we = addr_hit[575] & reg_we & !reg_error;
+  assign wkup_detector_cnt_th_7_we = addr_hit[608] & reg_we & !reg_error;
   assign wkup_detector_cnt_th_7_wd = reg_wdata[7:0];
 
-  assign wkup_detector_padsel_0_we = addr_hit[576] & reg_we & !reg_error;
+  assign wkup_detector_padsel_0_we = addr_hit[609] & reg_we & !reg_error;
   assign wkup_detector_padsel_0_wd = reg_wdata[5:0];
 
-  assign wkup_detector_padsel_1_we = addr_hit[577] & reg_we & !reg_error;
+  assign wkup_detector_padsel_1_we = addr_hit[610] & reg_we & !reg_error;
   assign wkup_detector_padsel_1_wd = reg_wdata[5:0];
 
-  assign wkup_detector_padsel_2_we = addr_hit[578] & reg_we & !reg_error;
+  assign wkup_detector_padsel_2_we = addr_hit[611] & reg_we & !reg_error;
   assign wkup_detector_padsel_2_wd = reg_wdata[5:0];
 
-  assign wkup_detector_padsel_3_we = addr_hit[579] & reg_we & !reg_error;
+  assign wkup_detector_padsel_3_we = addr_hit[612] & reg_we & !reg_error;
   assign wkup_detector_padsel_3_wd = reg_wdata[5:0];
 
-  assign wkup_detector_padsel_4_we = addr_hit[580] & reg_we & !reg_error;
+  assign wkup_detector_padsel_4_we = addr_hit[613] & reg_we & !reg_error;
   assign wkup_detector_padsel_4_wd = reg_wdata[5:0];
 
-  assign wkup_detector_padsel_5_we = addr_hit[581] & reg_we & !reg_error;
+  assign wkup_detector_padsel_5_we = addr_hit[614] & reg_we & !reg_error;
   assign wkup_detector_padsel_5_wd = reg_wdata[5:0];
 
-  assign wkup_detector_padsel_6_we = addr_hit[582] & reg_we & !reg_error;
+  assign wkup_detector_padsel_6_we = addr_hit[615] & reg_we & !reg_error;
   assign wkup_detector_padsel_6_wd = reg_wdata[5:0];
 
-  assign wkup_detector_padsel_7_we = addr_hit[583] & reg_we & !reg_error;
+  assign wkup_detector_padsel_7_we = addr_hit[616] & reg_we & !reg_error;
   assign wkup_detector_padsel_7_wd = reg_wdata[5:0];
 
-  assign wkup_cause_cause_0_we = addr_hit[584] & reg_we & !reg_error;
+  assign wkup_cause_cause_0_we = addr_hit[617] & reg_we & !reg_error;
   assign wkup_cause_cause_0_wd = reg_wdata[0];
-  assign wkup_cause_cause_0_re = addr_hit[584] & reg_re & !reg_error;
+  assign wkup_cause_cause_0_re = addr_hit[617] & reg_re & !reg_error;
 
-  assign wkup_cause_cause_1_we = addr_hit[584] & reg_we & !reg_error;
+  assign wkup_cause_cause_1_we = addr_hit[617] & reg_we & !reg_error;
   assign wkup_cause_cause_1_wd = reg_wdata[1];
-  assign wkup_cause_cause_1_re = addr_hit[584] & reg_re & !reg_error;
+  assign wkup_cause_cause_1_re = addr_hit[617] & reg_re & !reg_error;
 
-  assign wkup_cause_cause_2_we = addr_hit[584] & reg_we & !reg_error;
+  assign wkup_cause_cause_2_we = addr_hit[617] & reg_we & !reg_error;
   assign wkup_cause_cause_2_wd = reg_wdata[2];
-  assign wkup_cause_cause_2_re = addr_hit[584] & reg_re & !reg_error;
+  assign wkup_cause_cause_2_re = addr_hit[617] & reg_re & !reg_error;
 
-  assign wkup_cause_cause_3_we = addr_hit[584] & reg_we & !reg_error;
+  assign wkup_cause_cause_3_we = addr_hit[617] & reg_we & !reg_error;
   assign wkup_cause_cause_3_wd = reg_wdata[3];
-  assign wkup_cause_cause_3_re = addr_hit[584] & reg_re & !reg_error;
+  assign wkup_cause_cause_3_re = addr_hit[617] & reg_re & !reg_error;
 
-  assign wkup_cause_cause_4_we = addr_hit[584] & reg_we & !reg_error;
+  assign wkup_cause_cause_4_we = addr_hit[617] & reg_we & !reg_error;
   assign wkup_cause_cause_4_wd = reg_wdata[4];
-  assign wkup_cause_cause_4_re = addr_hit[584] & reg_re & !reg_error;
+  assign wkup_cause_cause_4_re = addr_hit[617] & reg_re & !reg_error;
 
-  assign wkup_cause_cause_5_we = addr_hit[584] & reg_we & !reg_error;
+  assign wkup_cause_cause_5_we = addr_hit[617] & reg_we & !reg_error;
   assign wkup_cause_cause_5_wd = reg_wdata[5];
-  assign wkup_cause_cause_5_re = addr_hit[584] & reg_re & !reg_error;
+  assign wkup_cause_cause_5_re = addr_hit[617] & reg_re & !reg_error;
 
-  assign wkup_cause_cause_6_we = addr_hit[584] & reg_we & !reg_error;
+  assign wkup_cause_cause_6_we = addr_hit[617] & reg_we & !reg_error;
   assign wkup_cause_cause_6_wd = reg_wdata[6];
-  assign wkup_cause_cause_6_re = addr_hit[584] & reg_re & !reg_error;
+  assign wkup_cause_cause_6_re = addr_hit[617] & reg_re & !reg_error;
 
-  assign wkup_cause_cause_7_we = addr_hit[584] & reg_we & !reg_error;
+  assign wkup_cause_cause_7_we = addr_hit[617] & reg_we & !reg_error;
   assign wkup_cause_cause_7_wd = reg_wdata[7];
-  assign wkup_cause_cause_7_re = addr_hit[584] & reg_re & !reg_error;
+  assign wkup_cause_cause_7_re = addr_hit[617] & reg_re & !reg_error;
 
   // Read data return
   always_comb begin
@@ -23488,698 +24763,770 @@
       end
 
       addr_hit[173]: begin
-        reg_rdata_next[6:0] = mio_outsel_0_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_43_qs;
       end
 
       addr_hit[174]: begin
-        reg_rdata_next[6:0] = mio_outsel_1_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_44_qs;
       end
 
       addr_hit[175]: begin
-        reg_rdata_next[6:0] = mio_outsel_2_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_45_qs;
       end
 
       addr_hit[176]: begin
-        reg_rdata_next[6:0] = mio_outsel_3_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_46_qs;
       end
 
       addr_hit[177]: begin
-        reg_rdata_next[6:0] = mio_outsel_4_qs;
+        reg_rdata_next[6:0] = mio_outsel_0_qs;
       end
 
       addr_hit[178]: begin
-        reg_rdata_next[6:0] = mio_outsel_5_qs;
+        reg_rdata_next[6:0] = mio_outsel_1_qs;
       end
 
       addr_hit[179]: begin
-        reg_rdata_next[6:0] = mio_outsel_6_qs;
+        reg_rdata_next[6:0] = mio_outsel_2_qs;
       end
 
       addr_hit[180]: begin
-        reg_rdata_next[6:0] = mio_outsel_7_qs;
+        reg_rdata_next[6:0] = mio_outsel_3_qs;
       end
 
       addr_hit[181]: begin
-        reg_rdata_next[6:0] = mio_outsel_8_qs;
+        reg_rdata_next[6:0] = mio_outsel_4_qs;
       end
 
       addr_hit[182]: begin
-        reg_rdata_next[6:0] = mio_outsel_9_qs;
+        reg_rdata_next[6:0] = mio_outsel_5_qs;
       end
 
       addr_hit[183]: begin
-        reg_rdata_next[6:0] = mio_outsel_10_qs;
+        reg_rdata_next[6:0] = mio_outsel_6_qs;
       end
 
       addr_hit[184]: begin
-        reg_rdata_next[6:0] = mio_outsel_11_qs;
+        reg_rdata_next[6:0] = mio_outsel_7_qs;
       end
 
       addr_hit[185]: begin
-        reg_rdata_next[6:0] = mio_outsel_12_qs;
+        reg_rdata_next[6:0] = mio_outsel_8_qs;
       end
 
       addr_hit[186]: begin
-        reg_rdata_next[6:0] = mio_outsel_13_qs;
+        reg_rdata_next[6:0] = mio_outsel_9_qs;
       end
 
       addr_hit[187]: begin
-        reg_rdata_next[6:0] = mio_outsel_14_qs;
+        reg_rdata_next[6:0] = mio_outsel_10_qs;
       end
 
       addr_hit[188]: begin
-        reg_rdata_next[6:0] = mio_outsel_15_qs;
+        reg_rdata_next[6:0] = mio_outsel_11_qs;
       end
 
       addr_hit[189]: begin
-        reg_rdata_next[6:0] = mio_outsel_16_qs;
+        reg_rdata_next[6:0] = mio_outsel_12_qs;
       end
 
       addr_hit[190]: begin
-        reg_rdata_next[6:0] = mio_outsel_17_qs;
+        reg_rdata_next[6:0] = mio_outsel_13_qs;
       end
 
       addr_hit[191]: begin
-        reg_rdata_next[6:0] = mio_outsel_18_qs;
+        reg_rdata_next[6:0] = mio_outsel_14_qs;
       end
 
       addr_hit[192]: begin
-        reg_rdata_next[6:0] = mio_outsel_19_qs;
+        reg_rdata_next[6:0] = mio_outsel_15_qs;
       end
 
       addr_hit[193]: begin
-        reg_rdata_next[6:0] = mio_outsel_20_qs;
+        reg_rdata_next[6:0] = mio_outsel_16_qs;
       end
 
       addr_hit[194]: begin
-        reg_rdata_next[6:0] = mio_outsel_21_qs;
+        reg_rdata_next[6:0] = mio_outsel_17_qs;
       end
 
       addr_hit[195]: begin
-        reg_rdata_next[6:0] = mio_outsel_22_qs;
+        reg_rdata_next[6:0] = mio_outsel_18_qs;
       end
 
       addr_hit[196]: begin
-        reg_rdata_next[6:0] = mio_outsel_23_qs;
+        reg_rdata_next[6:0] = mio_outsel_19_qs;
       end
 
       addr_hit[197]: begin
-        reg_rdata_next[6:0] = mio_outsel_24_qs;
+        reg_rdata_next[6:0] = mio_outsel_20_qs;
       end
 
       addr_hit[198]: begin
-        reg_rdata_next[6:0] = mio_outsel_25_qs;
+        reg_rdata_next[6:0] = mio_outsel_21_qs;
       end
 
       addr_hit[199]: begin
-        reg_rdata_next[6:0] = mio_outsel_26_qs;
+        reg_rdata_next[6:0] = mio_outsel_22_qs;
       end
 
       addr_hit[200]: begin
-        reg_rdata_next[6:0] = mio_outsel_27_qs;
+        reg_rdata_next[6:0] = mio_outsel_23_qs;
       end
 
       addr_hit[201]: begin
-        reg_rdata_next[6:0] = mio_outsel_28_qs;
+        reg_rdata_next[6:0] = mio_outsel_24_qs;
       end
 
       addr_hit[202]: begin
-        reg_rdata_next[6:0] = mio_outsel_29_qs;
+        reg_rdata_next[6:0] = mio_outsel_25_qs;
       end
 
       addr_hit[203]: begin
-        reg_rdata_next[6:0] = mio_outsel_30_qs;
+        reg_rdata_next[6:0] = mio_outsel_26_qs;
       end
 
       addr_hit[204]: begin
-        reg_rdata_next[6:0] = mio_outsel_31_qs;
+        reg_rdata_next[6:0] = mio_outsel_27_qs;
       end
 
       addr_hit[205]: begin
-        reg_rdata_next[6:0] = mio_outsel_32_qs;
+        reg_rdata_next[6:0] = mio_outsel_28_qs;
       end
 
       addr_hit[206]: begin
-        reg_rdata_next[6:0] = mio_outsel_33_qs;
+        reg_rdata_next[6:0] = mio_outsel_29_qs;
       end
 
       addr_hit[207]: begin
-        reg_rdata_next[6:0] = mio_outsel_34_qs;
+        reg_rdata_next[6:0] = mio_outsel_30_qs;
       end
 
       addr_hit[208]: begin
-        reg_rdata_next[6:0] = mio_outsel_35_qs;
+        reg_rdata_next[6:0] = mio_outsel_31_qs;
       end
 
       addr_hit[209]: begin
-        reg_rdata_next[6:0] = mio_outsel_36_qs;
+        reg_rdata_next[6:0] = mio_outsel_32_qs;
       end
 
       addr_hit[210]: begin
-        reg_rdata_next[6:0] = mio_outsel_37_qs;
+        reg_rdata_next[6:0] = mio_outsel_33_qs;
       end
 
       addr_hit[211]: begin
-        reg_rdata_next[6:0] = mio_outsel_38_qs;
+        reg_rdata_next[6:0] = mio_outsel_34_qs;
       end
 
       addr_hit[212]: begin
-        reg_rdata_next[6:0] = mio_outsel_39_qs;
+        reg_rdata_next[6:0] = mio_outsel_35_qs;
       end
 
       addr_hit[213]: begin
-        reg_rdata_next[6:0] = mio_outsel_40_qs;
+        reg_rdata_next[6:0] = mio_outsel_36_qs;
       end
 
       addr_hit[214]: begin
-        reg_rdata_next[6:0] = mio_outsel_41_qs;
+        reg_rdata_next[6:0] = mio_outsel_37_qs;
       end
 
       addr_hit[215]: begin
-        reg_rdata_next[6:0] = mio_outsel_42_qs;
+        reg_rdata_next[6:0] = mio_outsel_38_qs;
       end
 
       addr_hit[216]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_0_qs;
+        reg_rdata_next[6:0] = mio_outsel_39_qs;
       end
 
       addr_hit[217]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_1_qs;
+        reg_rdata_next[6:0] = mio_outsel_40_qs;
       end
 
       addr_hit[218]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_2_qs;
+        reg_rdata_next[6:0] = mio_outsel_41_qs;
       end
 
       addr_hit[219]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_3_qs;
+        reg_rdata_next[6:0] = mio_outsel_42_qs;
       end
 
       addr_hit[220]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_4_qs;
+        reg_rdata_next[6:0] = mio_outsel_43_qs;
       end
 
       addr_hit[221]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_5_qs;
+        reg_rdata_next[6:0] = mio_outsel_44_qs;
       end
 
       addr_hit[222]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_6_qs;
+        reg_rdata_next[6:0] = mio_outsel_45_qs;
       end
 
       addr_hit[223]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_7_qs;
+        reg_rdata_next[6:0] = mio_outsel_46_qs;
       end
 
       addr_hit[224]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_8_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_0_qs;
       end
 
       addr_hit[225]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_9_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_1_qs;
       end
 
       addr_hit[226]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_10_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_2_qs;
       end
 
       addr_hit[227]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_11_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_3_qs;
       end
 
       addr_hit[228]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_12_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_4_qs;
       end
 
       addr_hit[229]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_13_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_5_qs;
       end
 
       addr_hit[230]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_14_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_6_qs;
       end
 
       addr_hit[231]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_15_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_7_qs;
       end
 
       addr_hit[232]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_16_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_8_qs;
       end
 
       addr_hit[233]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_17_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_9_qs;
       end
 
       addr_hit[234]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_18_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_10_qs;
       end
 
       addr_hit[235]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_19_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_11_qs;
       end
 
       addr_hit[236]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_20_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_12_qs;
       end
 
       addr_hit[237]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_21_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_13_qs;
       end
 
       addr_hit[238]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_22_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_14_qs;
       end
 
       addr_hit[239]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_23_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_15_qs;
       end
 
       addr_hit[240]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_24_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_16_qs;
       end
 
       addr_hit[241]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_25_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_17_qs;
       end
 
       addr_hit[242]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_26_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_18_qs;
       end
 
       addr_hit[243]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_27_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_19_qs;
       end
 
       addr_hit[244]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_28_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_20_qs;
       end
 
       addr_hit[245]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_29_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_21_qs;
       end
 
       addr_hit[246]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_30_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_22_qs;
       end
 
       addr_hit[247]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_31_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_23_qs;
       end
 
       addr_hit[248]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_32_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_24_qs;
       end
 
       addr_hit[249]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_33_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_25_qs;
       end
 
       addr_hit[250]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_34_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_26_qs;
       end
 
       addr_hit[251]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_35_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_27_qs;
       end
 
       addr_hit[252]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_36_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_28_qs;
       end
 
       addr_hit[253]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_37_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_29_qs;
       end
 
       addr_hit[254]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_38_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_30_qs;
       end
 
       addr_hit[255]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_39_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_31_qs;
       end
 
       addr_hit[256]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_40_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_32_qs;
       end
 
       addr_hit[257]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_41_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_33_qs;
       end
 
       addr_hit[258]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_42_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_34_qs;
       end
 
       addr_hit[259]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_0_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_35_qs;
       end
 
       addr_hit[260]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_1_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_36_qs;
       end
 
       addr_hit[261]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_2_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_37_qs;
       end
 
       addr_hit[262]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_3_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_38_qs;
       end
 
       addr_hit[263]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_4_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_39_qs;
       end
 
       addr_hit[264]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_5_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_40_qs;
       end
 
       addr_hit[265]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_6_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_41_qs;
       end
 
       addr_hit[266]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_7_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_42_qs;
       end
 
       addr_hit[267]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_8_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_43_qs;
       end
 
       addr_hit[268]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_9_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_44_qs;
       end
 
       addr_hit[269]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_10_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_45_qs;
       end
 
       addr_hit[270]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_11_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_46_qs;
       end
 
       addr_hit[271]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_12_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_0_qs;
       end
 
       addr_hit[272]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_13_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_1_qs;
       end
 
       addr_hit[273]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_14_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_2_qs;
       end
 
       addr_hit[274]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_15_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_3_qs;
       end
 
       addr_hit[275]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_16_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_4_qs;
       end
 
       addr_hit[276]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_17_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_5_qs;
       end
 
       addr_hit[277]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_18_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_6_qs;
       end
 
       addr_hit[278]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_19_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_7_qs;
       end
 
       addr_hit[279]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_20_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_8_qs;
       end
 
       addr_hit[280]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_21_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_9_qs;
       end
 
       addr_hit[281]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_22_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_10_qs;
       end
 
       addr_hit[282]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_23_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_11_qs;
       end
 
       addr_hit[283]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_24_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_12_qs;
       end
 
       addr_hit[284]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_25_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_13_qs;
       end
 
       addr_hit[285]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_26_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_14_qs;
       end
 
       addr_hit[286]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_27_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_15_qs;
       end
 
       addr_hit[287]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_28_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_16_qs;
       end
 
       addr_hit[288]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_29_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_17_qs;
       end
 
       addr_hit[289]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_30_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_18_qs;
       end
 
       addr_hit[290]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_31_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_19_qs;
       end
 
       addr_hit[291]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_32_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_20_qs;
       end
 
       addr_hit[292]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_33_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_21_qs;
       end
 
       addr_hit[293]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_34_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_22_qs;
       end
 
       addr_hit[294]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_35_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_23_qs;
       end
 
       addr_hit[295]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_36_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_24_qs;
       end
 
       addr_hit[296]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_37_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_25_qs;
       end
 
       addr_hit[297]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_38_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_26_qs;
       end
 
       addr_hit[298]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_39_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_27_qs;
       end
 
       addr_hit[299]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_40_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_28_qs;
       end
 
       addr_hit[300]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_41_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_29_qs;
       end
 
       addr_hit[301]: begin
-        reg_rdata_next[12:0] = mio_pad_attr_42_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_30_qs;
       end
 
       addr_hit[302]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_0_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_31_qs;
       end
 
       addr_hit[303]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_1_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_32_qs;
       end
 
       addr_hit[304]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_2_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_33_qs;
       end
 
       addr_hit[305]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_3_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_34_qs;
       end
 
       addr_hit[306]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_4_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_35_qs;
       end
 
       addr_hit[307]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_5_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_36_qs;
       end
 
       addr_hit[308]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_6_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_37_qs;
       end
 
       addr_hit[309]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_7_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_38_qs;
       end
 
       addr_hit[310]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_8_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_39_qs;
       end
 
       addr_hit[311]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_9_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_40_qs;
       end
 
       addr_hit[312]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_10_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_41_qs;
       end
 
       addr_hit[313]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_11_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_42_qs;
       end
 
       addr_hit[314]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_12_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_43_qs;
       end
 
       addr_hit[315]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_13_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_44_qs;
       end
 
       addr_hit[316]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_14_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_45_qs;
       end
 
       addr_hit[317]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_15_qs;
+        reg_rdata_next[12:0] = mio_pad_attr_46_qs;
       end
 
       addr_hit[318]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_16_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_0_qs;
       end
 
       addr_hit[319]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_17_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_1_qs;
       end
 
       addr_hit[320]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_18_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_2_qs;
       end
 
       addr_hit[321]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_19_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_3_qs;
       end
 
       addr_hit[322]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_20_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_4_qs;
       end
 
       addr_hit[323]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_21_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_5_qs;
       end
 
       addr_hit[324]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_0_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_6_qs;
       end
 
       addr_hit[325]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_1_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_7_qs;
       end
 
       addr_hit[326]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_2_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_8_qs;
       end
 
       addr_hit[327]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_3_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_9_qs;
       end
 
       addr_hit[328]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_4_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_10_qs;
       end
 
       addr_hit[329]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_5_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_11_qs;
       end
 
       addr_hit[330]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_6_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_12_qs;
       end
 
       addr_hit[331]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_7_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_13_qs;
       end
 
       addr_hit[332]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_8_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_14_qs;
       end
 
       addr_hit[333]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_9_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_15_qs;
       end
 
       addr_hit[334]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_10_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_16_qs;
       end
 
       addr_hit[335]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_11_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_17_qs;
       end
 
       addr_hit[336]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_12_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_18_qs;
       end
 
       addr_hit[337]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_13_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_19_qs;
       end
 
       addr_hit[338]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_14_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_20_qs;
       end
 
       addr_hit[339]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_15_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_21_qs;
       end
 
       addr_hit[340]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_16_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_22_qs;
       end
 
       addr_hit[341]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_17_qs;
+        reg_rdata_next[12:0] = dio_pad_attr_0_qs;
       end
 
       addr_hit[342]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_18_qs;
+        reg_rdata_next[12:0] = dio_pad_attr_1_qs;
       end
 
       addr_hit[343]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_19_qs;
+        reg_rdata_next[12:0] = dio_pad_attr_2_qs;
       end
 
       addr_hit[344]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_20_qs;
+        reg_rdata_next[12:0] = dio_pad_attr_3_qs;
       end
 
       addr_hit[345]: begin
-        reg_rdata_next[12:0] = dio_pad_attr_21_qs;
+        reg_rdata_next[12:0] = dio_pad_attr_4_qs;
       end
 
       addr_hit[346]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_5_qs;
+      end
+
+      addr_hit[347]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_6_qs;
+      end
+
+      addr_hit[348]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_7_qs;
+      end
+
+      addr_hit[349]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_8_qs;
+      end
+
+      addr_hit[350]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_9_qs;
+      end
+
+      addr_hit[351]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_10_qs;
+      end
+
+      addr_hit[352]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_11_qs;
+      end
+
+      addr_hit[353]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_12_qs;
+      end
+
+      addr_hit[354]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_13_qs;
+      end
+
+      addr_hit[355]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_14_qs;
+      end
+
+      addr_hit[356]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_15_qs;
+      end
+
+      addr_hit[357]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_16_qs;
+      end
+
+      addr_hit[358]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_17_qs;
+      end
+
+      addr_hit[359]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_18_qs;
+      end
+
+      addr_hit[360]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_19_qs;
+      end
+
+      addr_hit[361]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_20_qs;
+      end
+
+      addr_hit[362]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_21_qs;
+      end
+
+      addr_hit[363]: begin
+        reg_rdata_next[12:0] = dio_pad_attr_22_qs;
+      end
+
+      addr_hit[364]: begin
         reg_rdata_next[0] = mio_pad_sleep_status_0_en_0_qs;
         reg_rdata_next[1] = mio_pad_sleep_status_0_en_1_qs;
         reg_rdata_next[2] = mio_pad_sleep_status_0_en_2_qs;
@@ -24214,7 +25561,7 @@
         reg_rdata_next[31] = mio_pad_sleep_status_0_en_31_qs;
       end
 
-      addr_hit[347]: begin
+      addr_hit[365]: begin
         reg_rdata_next[0] = mio_pad_sleep_status_1_en_32_qs;
         reg_rdata_next[1] = mio_pad_sleep_status_1_en_33_qs;
         reg_rdata_next[2] = mio_pad_sleep_status_1_en_34_qs;
@@ -24226,525 +25573,577 @@
         reg_rdata_next[8] = mio_pad_sleep_status_1_en_40_qs;
         reg_rdata_next[9] = mio_pad_sleep_status_1_en_41_qs;
         reg_rdata_next[10] = mio_pad_sleep_status_1_en_42_qs;
-      end
-
-      addr_hit[348]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs;
-      end
-
-      addr_hit[349]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs;
-      end
-
-      addr_hit[350]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs;
-      end
-
-      addr_hit[351]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs;
-      end
-
-      addr_hit[352]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs;
-      end
-
-      addr_hit[353]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs;
-      end
-
-      addr_hit[354]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs;
-      end
-
-      addr_hit[355]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs;
-      end
-
-      addr_hit[356]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs;
-      end
-
-      addr_hit[357]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs;
-      end
-
-      addr_hit[358]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs;
-      end
-
-      addr_hit[359]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs;
-      end
-
-      addr_hit[360]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_12_qs;
-      end
-
-      addr_hit[361]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_13_qs;
-      end
-
-      addr_hit[362]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_14_qs;
-      end
-
-      addr_hit[363]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_15_qs;
-      end
-
-      addr_hit[364]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_16_qs;
-      end
-
-      addr_hit[365]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_17_qs;
+        reg_rdata_next[11] = mio_pad_sleep_status_1_en_43_qs;
+        reg_rdata_next[12] = mio_pad_sleep_status_1_en_44_qs;
+        reg_rdata_next[13] = mio_pad_sleep_status_1_en_45_qs;
+        reg_rdata_next[14] = mio_pad_sleep_status_1_en_46_qs;
       end
 
       addr_hit[366]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_18_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs;
       end
 
       addr_hit[367]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_19_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs;
       end
 
       addr_hit[368]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_20_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs;
       end
 
       addr_hit[369]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_21_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs;
       end
 
       addr_hit[370]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_22_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs;
       end
 
       addr_hit[371]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_23_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs;
       end
 
       addr_hit[372]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_24_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs;
       end
 
       addr_hit[373]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_25_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs;
       end
 
       addr_hit[374]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_26_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs;
       end
 
       addr_hit[375]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_27_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs;
       end
 
       addr_hit[376]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_28_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs;
       end
 
       addr_hit[377]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_29_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs;
       end
 
       addr_hit[378]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_30_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_12_qs;
       end
 
       addr_hit[379]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_31_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_13_qs;
       end
 
       addr_hit[380]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_32_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_14_qs;
       end
 
       addr_hit[381]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_33_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_15_qs;
       end
 
       addr_hit[382]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_34_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_16_qs;
       end
 
       addr_hit[383]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_35_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_17_qs;
       end
 
       addr_hit[384]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_36_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_18_qs;
       end
 
       addr_hit[385]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_37_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_19_qs;
       end
 
       addr_hit[386]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_38_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_20_qs;
       end
 
       addr_hit[387]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_39_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_21_qs;
       end
 
       addr_hit[388]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_40_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_22_qs;
       end
 
       addr_hit[389]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_41_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_23_qs;
       end
 
       addr_hit[390]: begin
-        reg_rdata_next[0] = mio_pad_sleep_regwen_42_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_24_qs;
       end
 
       addr_hit[391]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_0_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_25_qs;
       end
 
       addr_hit[392]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_1_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_26_qs;
       end
 
       addr_hit[393]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_2_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_27_qs;
       end
 
       addr_hit[394]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_3_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_28_qs;
       end
 
       addr_hit[395]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_4_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_29_qs;
       end
 
       addr_hit[396]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_5_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_30_qs;
       end
 
       addr_hit[397]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_6_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_31_qs;
       end
 
       addr_hit[398]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_7_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_32_qs;
       end
 
       addr_hit[399]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_8_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_33_qs;
       end
 
       addr_hit[400]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_9_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_34_qs;
       end
 
       addr_hit[401]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_10_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_35_qs;
       end
 
       addr_hit[402]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_11_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_36_qs;
       end
 
       addr_hit[403]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_12_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_37_qs;
       end
 
       addr_hit[404]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_13_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_38_qs;
       end
 
       addr_hit[405]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_14_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_39_qs;
       end
 
       addr_hit[406]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_15_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_40_qs;
       end
 
       addr_hit[407]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_16_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_41_qs;
       end
 
       addr_hit[408]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_17_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_42_qs;
       end
 
       addr_hit[409]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_18_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_43_qs;
       end
 
       addr_hit[410]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_19_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_44_qs;
       end
 
       addr_hit[411]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_20_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_45_qs;
       end
 
       addr_hit[412]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_21_qs;
+        reg_rdata_next[0] = mio_pad_sleep_regwen_46_qs;
       end
 
       addr_hit[413]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_22_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_0_qs;
       end
 
       addr_hit[414]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_23_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_1_qs;
       end
 
       addr_hit[415]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_24_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_2_qs;
       end
 
       addr_hit[416]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_25_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_3_qs;
       end
 
       addr_hit[417]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_26_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_4_qs;
       end
 
       addr_hit[418]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_27_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_5_qs;
       end
 
       addr_hit[419]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_28_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_6_qs;
       end
 
       addr_hit[420]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_29_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_7_qs;
       end
 
       addr_hit[421]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_30_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_8_qs;
       end
 
       addr_hit[422]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_31_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_9_qs;
       end
 
       addr_hit[423]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_32_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_10_qs;
       end
 
       addr_hit[424]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_33_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_11_qs;
       end
 
       addr_hit[425]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_34_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_12_qs;
       end
 
       addr_hit[426]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_35_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_13_qs;
       end
 
       addr_hit[427]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_36_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_14_qs;
       end
 
       addr_hit[428]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_37_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_15_qs;
       end
 
       addr_hit[429]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_38_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_16_qs;
       end
 
       addr_hit[430]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_39_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_17_qs;
       end
 
       addr_hit[431]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_40_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_18_qs;
       end
 
       addr_hit[432]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_41_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_19_qs;
       end
 
       addr_hit[433]: begin
-        reg_rdata_next[0] = mio_pad_sleep_en_42_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_20_qs;
       end
 
       addr_hit[434]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_21_qs;
       end
 
       addr_hit[435]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_22_qs;
       end
 
       addr_hit[436]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_23_qs;
       end
 
       addr_hit[437]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_24_qs;
       end
 
       addr_hit[438]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_25_qs;
       end
 
       addr_hit[439]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_26_qs;
       end
 
       addr_hit[440]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_27_qs;
       end
 
       addr_hit[441]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_28_qs;
       end
 
       addr_hit[442]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_29_qs;
       end
 
       addr_hit[443]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_30_qs;
       end
 
       addr_hit[444]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_31_qs;
       end
 
       addr_hit[445]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_32_qs;
       end
 
       addr_hit[446]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_12_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_33_qs;
       end
 
       addr_hit[447]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_13_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_34_qs;
       end
 
       addr_hit[448]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_14_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_35_qs;
       end
 
       addr_hit[449]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_15_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_36_qs;
       end
 
       addr_hit[450]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_16_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_37_qs;
       end
 
       addr_hit[451]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_17_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_38_qs;
       end
 
       addr_hit[452]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_18_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_39_qs;
       end
 
       addr_hit[453]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_19_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_40_qs;
       end
 
       addr_hit[454]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_20_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_41_qs;
       end
 
       addr_hit[455]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_21_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_42_qs;
       end
 
       addr_hit[456]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_22_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_43_qs;
       end
 
       addr_hit[457]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_23_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_44_qs;
       end
 
       addr_hit[458]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_24_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_45_qs;
       end
 
       addr_hit[459]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_25_qs;
+        reg_rdata_next[0] = mio_pad_sleep_en_46_qs;
       end
 
       addr_hit[460]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_26_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs;
       end
 
       addr_hit[461]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_27_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs;
       end
 
       addr_hit[462]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_28_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs;
       end
 
       addr_hit[463]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_29_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs;
       end
 
       addr_hit[464]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_30_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs;
       end
 
       addr_hit[465]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_31_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs;
       end
 
       addr_hit[466]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_32_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs;
       end
 
       addr_hit[467]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_33_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs;
       end
 
       addr_hit[468]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_34_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs;
       end
 
       addr_hit[469]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_35_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs;
       end
 
       addr_hit[470]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_36_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs;
       end
 
       addr_hit[471]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_37_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs;
       end
 
       addr_hit[472]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_38_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_12_qs;
       end
 
       addr_hit[473]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_39_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_13_qs;
       end
 
       addr_hit[474]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_40_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_14_qs;
       end
 
       addr_hit[475]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_41_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_15_qs;
       end
 
       addr_hit[476]: begin
-        reg_rdata_next[1:0] = mio_pad_sleep_mode_42_qs;
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_16_qs;
       end
 
       addr_hit[477]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_17_qs;
+      end
+
+      addr_hit[478]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_18_qs;
+      end
+
+      addr_hit[479]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_19_qs;
+      end
+
+      addr_hit[480]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_20_qs;
+      end
+
+      addr_hit[481]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_21_qs;
+      end
+
+      addr_hit[482]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_22_qs;
+      end
+
+      addr_hit[483]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_23_qs;
+      end
+
+      addr_hit[484]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_24_qs;
+      end
+
+      addr_hit[485]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_25_qs;
+      end
+
+      addr_hit[486]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_26_qs;
+      end
+
+      addr_hit[487]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_27_qs;
+      end
+
+      addr_hit[488]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_28_qs;
+      end
+
+      addr_hit[489]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_29_qs;
+      end
+
+      addr_hit[490]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_30_qs;
+      end
+
+      addr_hit[491]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_31_qs;
+      end
+
+      addr_hit[492]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_32_qs;
+      end
+
+      addr_hit[493]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_33_qs;
+      end
+
+      addr_hit[494]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_34_qs;
+      end
+
+      addr_hit[495]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_35_qs;
+      end
+
+      addr_hit[496]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_36_qs;
+      end
+
+      addr_hit[497]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_37_qs;
+      end
+
+      addr_hit[498]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_38_qs;
+      end
+
+      addr_hit[499]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_39_qs;
+      end
+
+      addr_hit[500]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_40_qs;
+      end
+
+      addr_hit[501]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_41_qs;
+      end
+
+      addr_hit[502]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_42_qs;
+      end
+
+      addr_hit[503]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_43_qs;
+      end
+
+      addr_hit[504]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_44_qs;
+      end
+
+      addr_hit[505]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_45_qs;
+      end
+
+      addr_hit[506]: begin
+        reg_rdata_next[1:0] = mio_pad_sleep_mode_46_qs;
+      end
+
+      addr_hit[507]: begin
         reg_rdata_next[0] = dio_pad_sleep_status_en_0_qs;
         reg_rdata_next[1] = dio_pad_sleep_status_en_1_qs;
         reg_rdata_next[2] = dio_pad_sleep_status_en_2_qs;
@@ -24767,449 +26166,462 @@
         reg_rdata_next[19] = dio_pad_sleep_status_en_19_qs;
         reg_rdata_next[20] = dio_pad_sleep_status_en_20_qs;
         reg_rdata_next[21] = dio_pad_sleep_status_en_21_qs;
-      end
-
-      addr_hit[478]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs;
-      end
-
-      addr_hit[479]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs;
-      end
-
-      addr_hit[480]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs;
-      end
-
-      addr_hit[481]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs;
-      end
-
-      addr_hit[482]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs;
-      end
-
-      addr_hit[483]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs;
-      end
-
-      addr_hit[484]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs;
-      end
-
-      addr_hit[485]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs;
-      end
-
-      addr_hit[486]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs;
-      end
-
-      addr_hit[487]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs;
-      end
-
-      addr_hit[488]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs;
-      end
-
-      addr_hit[489]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs;
-      end
-
-      addr_hit[490]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs;
-      end
-
-      addr_hit[491]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs;
-      end
-
-      addr_hit[492]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs;
-      end
-
-      addr_hit[493]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_15_qs;
-      end
-
-      addr_hit[494]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_16_qs;
-      end
-
-      addr_hit[495]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_17_qs;
-      end
-
-      addr_hit[496]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_18_qs;
-      end
-
-      addr_hit[497]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_19_qs;
-      end
-
-      addr_hit[498]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_20_qs;
-      end
-
-      addr_hit[499]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_21_qs;
-      end
-
-      addr_hit[500]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_0_qs;
-      end
-
-      addr_hit[501]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_1_qs;
-      end
-
-      addr_hit[502]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_2_qs;
-      end
-
-      addr_hit[503]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_3_qs;
-      end
-
-      addr_hit[504]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_4_qs;
-      end
-
-      addr_hit[505]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_5_qs;
-      end
-
-      addr_hit[506]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_6_qs;
-      end
-
-      addr_hit[507]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_7_qs;
+        reg_rdata_next[22] = dio_pad_sleep_status_en_22_qs;
       end
 
       addr_hit[508]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_8_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs;
       end
 
       addr_hit[509]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_9_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs;
       end
 
       addr_hit[510]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_10_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs;
       end
 
       addr_hit[511]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_11_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs;
       end
 
       addr_hit[512]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_12_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs;
       end
 
       addr_hit[513]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_13_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs;
       end
 
       addr_hit[514]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_14_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs;
       end
 
       addr_hit[515]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_15_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs;
       end
 
       addr_hit[516]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_16_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs;
       end
 
       addr_hit[517]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_17_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs;
       end
 
       addr_hit[518]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_18_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs;
       end
 
       addr_hit[519]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_19_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs;
       end
 
       addr_hit[520]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_20_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs;
       end
 
       addr_hit[521]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_21_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs;
       end
 
       addr_hit[522]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs;
       end
 
       addr_hit[523]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_15_qs;
       end
 
       addr_hit[524]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_16_qs;
       end
 
       addr_hit[525]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_17_qs;
       end
 
       addr_hit[526]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_18_qs;
       end
 
       addr_hit[527]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_19_qs;
       end
 
       addr_hit[528]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_20_qs;
       end
 
       addr_hit[529]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_21_qs;
       end
 
       addr_hit[530]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_22_qs;
       end
 
       addr_hit[531]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_0_qs;
       end
 
       addr_hit[532]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_1_qs;
       end
 
       addr_hit[533]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_2_qs;
       end
 
       addr_hit[534]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_3_qs;
       end
 
       addr_hit[535]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_4_qs;
       end
 
       addr_hit[536]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_5_qs;
       end
 
       addr_hit[537]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_15_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_6_qs;
       end
 
       addr_hit[538]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_16_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_7_qs;
       end
 
       addr_hit[539]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_17_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_8_qs;
       end
 
       addr_hit[540]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_18_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_9_qs;
       end
 
       addr_hit[541]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_19_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_10_qs;
       end
 
       addr_hit[542]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_20_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_11_qs;
       end
 
       addr_hit[543]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_21_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_12_qs;
       end
 
       addr_hit[544]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_0_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_13_qs;
       end
 
       addr_hit[545]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_1_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_14_qs;
       end
 
       addr_hit[546]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_2_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_15_qs;
       end
 
       addr_hit[547]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_3_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_16_qs;
       end
 
       addr_hit[548]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_4_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_17_qs;
       end
 
       addr_hit[549]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_5_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_18_qs;
       end
 
       addr_hit[550]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_6_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_19_qs;
       end
 
       addr_hit[551]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_7_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_20_qs;
       end
 
       addr_hit[552]: begin
-        reg_rdata_next[0] = wkup_detector_en_0_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_21_qs;
       end
 
       addr_hit[553]: begin
-        reg_rdata_next[0] = wkup_detector_en_1_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_22_qs;
       end
 
       addr_hit[554]: begin
-        reg_rdata_next[0] = wkup_detector_en_2_qs;
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs;
       end
 
       addr_hit[555]: begin
-        reg_rdata_next[0] = wkup_detector_en_3_qs;
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs;
       end
 
       addr_hit[556]: begin
-        reg_rdata_next[0] = wkup_detector_en_4_qs;
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs;
       end
 
       addr_hit[557]: begin
-        reg_rdata_next[0] = wkup_detector_en_5_qs;
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs;
       end
 
       addr_hit[558]: begin
-        reg_rdata_next[0] = wkup_detector_en_6_qs;
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs;
       end
 
       addr_hit[559]: begin
-        reg_rdata_next[0] = wkup_detector_en_7_qs;
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs;
       end
 
       addr_hit[560]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs;
+      end
+
+      addr_hit[561]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs;
+      end
+
+      addr_hit[562]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs;
+      end
+
+      addr_hit[563]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs;
+      end
+
+      addr_hit[564]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs;
+      end
+
+      addr_hit[565]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs;
+      end
+
+      addr_hit[566]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs;
+      end
+
+      addr_hit[567]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs;
+      end
+
+      addr_hit[568]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs;
+      end
+
+      addr_hit[569]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_15_qs;
+      end
+
+      addr_hit[570]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_16_qs;
+      end
+
+      addr_hit[571]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_17_qs;
+      end
+
+      addr_hit[572]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_18_qs;
+      end
+
+      addr_hit[573]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_19_qs;
+      end
+
+      addr_hit[574]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_20_qs;
+      end
+
+      addr_hit[575]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_21_qs;
+      end
+
+      addr_hit[576]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_22_qs;
+      end
+
+      addr_hit[577]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_0_qs;
+      end
+
+      addr_hit[578]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_1_qs;
+      end
+
+      addr_hit[579]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_2_qs;
+      end
+
+      addr_hit[580]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_3_qs;
+      end
+
+      addr_hit[581]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_4_qs;
+      end
+
+      addr_hit[582]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_5_qs;
+      end
+
+      addr_hit[583]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_6_qs;
+      end
+
+      addr_hit[584]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_7_qs;
+      end
+
+      addr_hit[585]: begin
+        reg_rdata_next[0] = wkup_detector_en_0_qs;
+      end
+
+      addr_hit[586]: begin
+        reg_rdata_next[0] = wkup_detector_en_1_qs;
+      end
+
+      addr_hit[587]: begin
+        reg_rdata_next[0] = wkup_detector_en_2_qs;
+      end
+
+      addr_hit[588]: begin
+        reg_rdata_next[0] = wkup_detector_en_3_qs;
+      end
+
+      addr_hit[589]: begin
+        reg_rdata_next[0] = wkup_detector_en_4_qs;
+      end
+
+      addr_hit[590]: begin
+        reg_rdata_next[0] = wkup_detector_en_5_qs;
+      end
+
+      addr_hit[591]: begin
+        reg_rdata_next[0] = wkup_detector_en_6_qs;
+      end
+
+      addr_hit[592]: begin
+        reg_rdata_next[0] = wkup_detector_en_7_qs;
+      end
+
+      addr_hit[593]: begin
         reg_rdata_next[2:0] = wkup_detector_0_mode_0_qs;
         reg_rdata_next[3] = wkup_detector_0_filter_0_qs;
         reg_rdata_next[4] = wkup_detector_0_miodio_0_qs;
       end
 
-      addr_hit[561]: begin
+      addr_hit[594]: begin
         reg_rdata_next[2:0] = wkup_detector_1_mode_1_qs;
         reg_rdata_next[3] = wkup_detector_1_filter_1_qs;
         reg_rdata_next[4] = wkup_detector_1_miodio_1_qs;
       end
 
-      addr_hit[562]: begin
+      addr_hit[595]: begin
         reg_rdata_next[2:0] = wkup_detector_2_mode_2_qs;
         reg_rdata_next[3] = wkup_detector_2_filter_2_qs;
         reg_rdata_next[4] = wkup_detector_2_miodio_2_qs;
       end
 
-      addr_hit[563]: begin
+      addr_hit[596]: begin
         reg_rdata_next[2:0] = wkup_detector_3_mode_3_qs;
         reg_rdata_next[3] = wkup_detector_3_filter_3_qs;
         reg_rdata_next[4] = wkup_detector_3_miodio_3_qs;
       end
 
-      addr_hit[564]: begin
+      addr_hit[597]: begin
         reg_rdata_next[2:0] = wkup_detector_4_mode_4_qs;
         reg_rdata_next[3] = wkup_detector_4_filter_4_qs;
         reg_rdata_next[4] = wkup_detector_4_miodio_4_qs;
       end
 
-      addr_hit[565]: begin
+      addr_hit[598]: begin
         reg_rdata_next[2:0] = wkup_detector_5_mode_5_qs;
         reg_rdata_next[3] = wkup_detector_5_filter_5_qs;
         reg_rdata_next[4] = wkup_detector_5_miodio_5_qs;
       end
 
-      addr_hit[566]: begin
+      addr_hit[599]: begin
         reg_rdata_next[2:0] = wkup_detector_6_mode_6_qs;
         reg_rdata_next[3] = wkup_detector_6_filter_6_qs;
         reg_rdata_next[4] = wkup_detector_6_miodio_6_qs;
       end
 
-      addr_hit[567]: begin
+      addr_hit[600]: begin
         reg_rdata_next[2:0] = wkup_detector_7_mode_7_qs;
         reg_rdata_next[3] = wkup_detector_7_filter_7_qs;
         reg_rdata_next[4] = wkup_detector_7_miodio_7_qs;
       end
 
-      addr_hit[568]: begin
+      addr_hit[601]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_0_qs;
       end
 
-      addr_hit[569]: begin
+      addr_hit[602]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_1_qs;
       end
 
-      addr_hit[570]: begin
+      addr_hit[603]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_2_qs;
       end
 
-      addr_hit[571]: begin
+      addr_hit[604]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_3_qs;
       end
 
-      addr_hit[572]: begin
+      addr_hit[605]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_4_qs;
       end
 
-      addr_hit[573]: begin
+      addr_hit[606]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_5_qs;
       end
 
-      addr_hit[574]: begin
+      addr_hit[607]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_6_qs;
       end
 
-      addr_hit[575]: begin
+      addr_hit[608]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_7_qs;
       end
 
-      addr_hit[576]: begin
+      addr_hit[609]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_0_qs;
       end
 
-      addr_hit[577]: begin
+      addr_hit[610]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_1_qs;
       end
 
-      addr_hit[578]: begin
+      addr_hit[611]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_2_qs;
       end
 
-      addr_hit[579]: begin
+      addr_hit[612]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_3_qs;
       end
 
-      addr_hit[580]: begin
+      addr_hit[613]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_4_qs;
       end
 
-      addr_hit[581]: begin
+      addr_hit[614]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_5_qs;
       end
 
-      addr_hit[582]: begin
+      addr_hit[615]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_6_qs;
       end
 
-      addr_hit[583]: begin
+      addr_hit[616]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_7_qs;
       end
 
-      addr_hit[584]: begin
+      addr_hit[617]: begin
         reg_rdata_next[0] = wkup_cause_cause_0_qs;
         reg_rdata_next[1] = wkup_cause_cause_1_qs;
         reg_rdata_next[2] = wkup_cause_cause_2_qs;
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
index 7f70786..1bff316 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
@@ -34,6 +34,7 @@
   inout FLASH_TEST_MODE3, // Manual Pad
   inout FLASH_TEST_VOLT, // Manual Pad
   inout IOR8, // Dedicated Pad for sysrst_ctrl_aon_ec_rst_out_l
+  inout IOR9, // Dedicated Pad for sysrst_ctrl_aon_pwrb_out
 
   // Muxed Pads
   inout IOA0, // MIO Pad 0
@@ -42,43 +43,47 @@
   inout IOA3, // MIO Pad 3
   inout IOA4, // MIO Pad 4
   inout IOA5, // MIO Pad 5
-  inout IOB0, // MIO Pad 6
-  inout IOB1, // MIO Pad 7
-  inout IOB2, // MIO Pad 8
-  inout IOB3, // MIO Pad 9
-  inout IOB4, // MIO Pad 10
-  inout IOB5, // MIO Pad 11
-  inout IOB6, // MIO Pad 12
-  inout IOB7, // MIO Pad 13
-  inout IOB8, // MIO Pad 14
-  inout IOB9, // MIO Pad 15
-  inout IOB10, // MIO Pad 16
-  inout IOB11, // MIO Pad 17
-  inout IOC0, // MIO Pad 18
-  inout IOC1, // MIO Pad 19
-  inout IOC2, // MIO Pad 20
-  inout IOC3, // MIO Pad 21
-  inout IOC4, // MIO Pad 22
-  inout IOC5, // MIO Pad 23
-  inout IOC6, // MIO Pad 24
-  inout IOC7, // MIO Pad 25
-  inout IOC8, // MIO Pad 26
-  inout IOC9, // MIO Pad 27
-  inout IOC10, // MIO Pad 28
-  inout IOC11, // MIO Pad 29
-  inout IOR0, // MIO Pad 30
-  inout IOR1, // MIO Pad 31
-  inout IOR2, // MIO Pad 32
-  inout IOR3, // MIO Pad 33
-  inout IOR4, // MIO Pad 34
-  inout IOR5, // MIO Pad 35
-  inout IOR6, // MIO Pad 36
-  inout IOR7, // MIO Pad 37
-  inout IOR9, // MIO Pad 38
-  inout IOR10, // MIO Pad 39
-  inout IOR11, // MIO Pad 40
-  inout IOR12, // MIO Pad 41
-  inout IOR13  // MIO Pad 42
+  inout IOA6, // MIO Pad 6
+  inout IOA7, // MIO Pad 7
+  inout IOA8, // MIO Pad 8
+  inout IOB0, // MIO Pad 9
+  inout IOB1, // MIO Pad 10
+  inout IOB2, // MIO Pad 11
+  inout IOB3, // MIO Pad 12
+  inout IOB4, // MIO Pad 13
+  inout IOB5, // MIO Pad 14
+  inout IOB6, // MIO Pad 15
+  inout IOB7, // MIO Pad 16
+  inout IOB8, // MIO Pad 17
+  inout IOB9, // MIO Pad 18
+  inout IOB10, // MIO Pad 19
+  inout IOB11, // MIO Pad 20
+  inout IOB12, // MIO Pad 21
+  inout IOC0, // MIO Pad 22
+  inout IOC1, // MIO Pad 23
+  inout IOC2, // MIO Pad 24
+  inout IOC3, // MIO Pad 25
+  inout IOC4, // MIO Pad 26
+  inout IOC5, // MIO Pad 27
+  inout IOC6, // MIO Pad 28
+  inout IOC7, // MIO Pad 29
+  inout IOC8, // MIO Pad 30
+  inout IOC9, // MIO Pad 31
+  inout IOC10, // MIO Pad 32
+  inout IOC11, // MIO Pad 33
+  inout IOC12, // MIO Pad 34
+  inout IOR0, // MIO Pad 35
+  inout IOR1, // MIO Pad 36
+  inout IOR2, // MIO Pad 37
+  inout IOR3, // MIO Pad 38
+  inout IOR4, // MIO Pad 39
+  inout IOR5, // MIO Pad 40
+  inout IOR6, // MIO Pad 41
+  inout IOR7, // MIO Pad 42
+  inout IOR10, // MIO Pad 43
+  inout IOR11, // MIO Pad 44
+  inout IOR12, // MIO Pad 45
+  inout IOR13  // MIO Pad 46
 );
 
   import top_earlgrey_pkg::*;
@@ -88,15 +93,15 @@
   // Special Signal Indices //
   ////////////////////////////
 
-  parameter int Tap0PadIdx = 26;
-  parameter int Tap1PadIdx = 23;
-  parameter int Dft0PadIdx = 21;
-  parameter int Dft1PadIdx = 22;
-  parameter int TckPadIdx = 54;
-  parameter int TmsPadIdx = 55;
-  parameter int TrstNPadIdx = 18;
-  parameter int TdiPadIdx = 47;
-  parameter int TdoPadIdx = 48;
+  parameter int Tap0PadIdx = 30;
+  parameter int Tap1PadIdx = 27;
+  parameter int Dft0PadIdx = 25;
+  parameter int Dft1PadIdx = 26;
+  parameter int TckPadIdx = 38;
+  parameter int TmsPadIdx = 35;
+  parameter int TrstNPadIdx = 39;
+  parameter int TdiPadIdx = 37;
+  parameter int TdoPadIdx = 36;
 
   // TODO: this is temporary and will be removed in the future.
   // This specifies the tie-off values of the muxed MIO/DIOs
@@ -173,12 +178,13 @@
   padring #(
     // Padring specific counts may differ from pinmux config due
     // to custom, stubbed or added pads.
-    .NDioPads(23),
-    .NMioPads(43),
+    .NDioPads(24),
+    .NMioPads(47),
     // TODO: need to add ScanRole parameters
     .PhysicalPads(1),
     .NIoBanks(IoBankCount),
     .DioPadBank ({
+      IoBankVcc, // IOR9
       IoBankVcc, // IOR8
       IoBankVcc, // FLASH_TEST_VOLT
       IoBankVcc, // FLASH_TEST_MODE3
@@ -208,7 +214,6 @@
       IoBankVcc, // IOR12
       IoBankVcc, // IOR11
       IoBankVcc, // IOR10
-      IoBankVcc, // IOR9
       IoBankVcc, // IOR7
       IoBankVcc, // IOR6
       IoBankVcc, // IOR5
@@ -217,6 +222,7 @@
       IoBankVcc, // IOR2
       IoBankVcc, // IOR1
       IoBankVcc, // IOR0
+      IoBankVcc, // IOC12
       IoBankVcc, // IOC11
       IoBankVcc, // IOC10
       IoBankVcc, // IOC9
@@ -229,6 +235,7 @@
       IoBankVcc, // IOC2
       IoBankVcc, // IOC1
       IoBankVcc, // IOC0
+      IoBankViob, // IOB12
       IoBankViob, // IOB11
       IoBankViob, // IOB10
       IoBankViob, // IOB9
@@ -241,6 +248,9 @@
       IoBankViob, // IOB2
       IoBankViob, // IOB1
       IoBankViob, // IOB0
+      IoBankVioa, // IOA8
+      IoBankVioa, // IOA7
+      IoBankVioa, // IOA6
       IoBankVioa, // IOA5
       IoBankVioa, // IOA4
       IoBankVioa, // IOA3
@@ -249,6 +259,7 @@
       IoBankVioa  // IOA0
     }),
     .DioPadType ({
+      BidirOd, // IOR9
       BidirOd, // IOR8
       InputStd, // FLASH_TEST_VOLT
       InputStd, // FLASH_TEST_MODE3
@@ -278,45 +289,49 @@
       BidirOd, // IOR12
       BidirOd, // IOR11
       BidirOd, // IOR10
-      BidirOd, // IOR9
-      InputStd, // IOR7
-      InputStd, // IOR6
-      InputStd, // IOR5
-      InputStd, // IOR4
-      InputStd, // IOR3
-      InputStd, // IOR2
-      InputStd, // IOR1
-      InputStd, // IOR0
+      BidirStd, // IOR7
+      BidirStd, // IOR6
+      BidirStd, // IOR5
+      BidirStd, // IOR4
+      BidirStd, // IOR3
+      BidirStd, // IOR2
+      BidirStd, // IOR1
+      BidirStd, // IOR0
+      BidirOd, // IOC12
       BidirOd, // IOC11
       BidirOd, // IOC10
-      BidirOd, // IOC9
-      BidirOd, // IOC8
-      InputStd, // IOC7
-      InputStd, // IOC6
-      InputStd, // IOC5
-      InputStd, // IOC4
-      InputStd, // IOC3
-      InputStd, // IOC2
-      InputStd, // IOC1
-      InputStd, // IOC0
-      InputStd, // IOB11
-      InputStd, // IOB10
+      BidirStd, // IOC9
+      BidirStd, // IOC8
+      BidirStd, // IOC7
+      BidirStd, // IOC6
+      BidirStd, // IOC5
+      BidirStd, // IOC4
+      BidirStd, // IOC3
+      BidirStd, // IOC2
+      BidirStd, // IOC1
+      BidirStd, // IOC0
+      BidirOd, // IOB12
+      BidirOd, // IOB11
+      BidirOd, // IOB10
       BidirOd, // IOB9
-      BidirOd, // IOB8
-      InputStd, // IOB7
-      InputStd, // IOB6
-      InputStd, // IOB5
-      InputStd, // IOB4
-      InputStd, // IOB3
-      InputStd, // IOB2
-      InputStd, // IOB1
-      InputStd, // IOB0
-      BidirOd, // IOA5
-      BidirOd, // IOA4
-      InputStd, // IOA3
-      InputStd, // IOA2
-      InputStd, // IOA1
-      InputStd  // IOA0
+      BidirStd, // IOB8
+      BidirStd, // IOB7
+      BidirStd, // IOB6
+      BidirStd, // IOB5
+      BidirStd, // IOB4
+      BidirStd, // IOB3
+      BidirStd, // IOB2
+      BidirStd, // IOB1
+      BidirStd, // IOB0
+      BidirOd, // IOA8
+      BidirOd, // IOA7
+      BidirOd, // IOA6
+      BidirStd, // IOA5
+      BidirStd, // IOA4
+      BidirStd, // IOA3
+      BidirStd, // IOA2
+      BidirStd, // IOA1
+      BidirStd  // IOA0
     })
   ) u_padring (
   // This is only used for scan and DFT purposes
@@ -328,6 +343,7 @@
     .mio_in_raw_o ( ),
     // Chip IOs
     .dio_pad_io ({
+      IOR9,
       IOR8,
       FLASH_TEST_VOLT,
       FLASH_TEST_MODE3,
@@ -358,7 +374,6 @@
       IOR12,
       IOR11,
       IOR10,
-      IOR9,
       IOR7,
       IOR6,
       IOR5,
@@ -367,6 +382,7 @@
       IOR2,
       IOR1,
       IOR0,
+      IOC12,
       IOC11,
       IOC10,
       IOC9,
@@ -379,6 +395,7 @@
       IOC2,
       IOC1,
       IOC0,
+      IOB12,
       IOB11,
       IOB10,
       IOB9,
@@ -391,6 +408,9 @@
       IOB2,
       IOB1,
       IOB0,
+      IOA8,
+      IOA7,
+      IOA6,
       IOA5,
       IOA4,
       IOA3,
@@ -401,6 +421,7 @@
 
     // Core-facing
     .dio_in_o ({
+        dio_in[DioSysrstCtrlAonPwrbOut],
         dio_in[DioSysrstCtrlAonEcRstOutL],
         manual_in_flash_test_volt,
         manual_in_flash_test_mode3,
@@ -426,6 +447,7 @@
         manual_in_por_n
       }),
     .dio_out_i ({
+        dio_out[DioSysrstCtrlAonPwrbOut],
         dio_out[DioSysrstCtrlAonEcRstOutL],
         manual_out_flash_test_volt,
         manual_out_flash_test_mode3,
@@ -451,6 +473,7 @@
         manual_out_por_n
       }),
     .dio_oe_i ({
+        dio_oe[DioSysrstCtrlAonPwrbOut],
         dio_oe[DioSysrstCtrlAonEcRstOutL],
         manual_oe_flash_test_volt,
         manual_oe_flash_test_mode3,
@@ -476,6 +499,7 @@
         manual_oe_por_n
       }),
     .dio_attr_i ({
+        dio_attr[DioSysrstCtrlAonPwrbOut],
         dio_attr[DioSysrstCtrlAonEcRstOutL],
         manual_attr_flash_test_volt,
         manual_attr_flash_test_mode3,
@@ -502,6 +526,10 @@
       }),
 
     .mio_in_o ({
+        mio_in[46],
+        mio_in[45],
+        mio_in[44],
+        mio_in[43],
         mio_in[42],
         mio_in[41],
         mio_in[40],
@@ -547,6 +575,10 @@
         mio_in[0]
       }),
     .mio_out_i ({
+        mio_out[46],
+        mio_out[45],
+        mio_out[44],
+        mio_out[43],
         mio_out[42],
         mio_out[41],
         mio_out[40],
@@ -592,6 +624,10 @@
         mio_out[0]
       }),
     .mio_oe_i ({
+        mio_oe[46],
+        mio_oe[45],
+        mio_oe[44],
+        mio_oe[43],
         mio_oe[42],
         mio_oe[41],
         mio_oe[40],
@@ -637,6 +673,10 @@
         mio_oe[0]
       }),
     .mio_attr_i ({
+        mio_attr[46],
+        mio_attr[45],
+        mio_attr[44],
+        mio_attr[43],
         mio_attr[42],
         mio_attr[41],
         mio_attr[40],
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
index 9e5a49d..98f3667 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
@@ -46,29 +46,29 @@
   inout IOA3, // MIO Pad 3
   inout IOA4, // MIO Pad 4
   inout IOA5, // MIO Pad 5
-  inout IOB0, // MIO Pad 6
-  inout IOB1, // MIO Pad 7
-  inout IOB2, // MIO Pad 8
-  inout IOB3, // MIO Pad 9
-  inout IOB4, // MIO Pad 10
-  inout IOB5, // MIO Pad 11
-  inout IOB6, // MIO Pad 12
-  inout IOB7, // MIO Pad 13
-  inout IOB8, // MIO Pad 14
-  inout IOB9, // MIO Pad 15
-  inout IOB10, // MIO Pad 16
-  inout IOB11, // MIO Pad 17
-  inout IOC0, // MIO Pad 18
-  inout IOC6, // MIO Pad 24
-  inout IOC7, // MIO Pad 25
-  inout IOC8, // MIO Pad 26
-  inout IOC9, // MIO Pad 27
-  inout IOC10, // MIO Pad 28
-  inout IOC11, // MIO Pad 29
-  inout IOR0, // MIO Pad 30
-  inout IOR1, // MIO Pad 31
-  inout IOR2, // MIO Pad 32
-  inout IOR3  // MIO Pad 33
+  inout IOA6, // MIO Pad 6
+  inout IOA7, // MIO Pad 7
+  inout IOA8, // MIO Pad 8
+  inout IOB0, // MIO Pad 9
+  inout IOB1, // MIO Pad 10
+  inout IOB2, // MIO Pad 11
+  inout IOB3, // MIO Pad 12
+  inout IOB4, // MIO Pad 13
+  inout IOB5, // MIO Pad 14
+  inout IOB6, // MIO Pad 15
+  inout IOB7, // MIO Pad 16
+  inout IOB8, // MIO Pad 17
+  inout IOB9, // MIO Pad 18
+  inout IOC2, // MIO Pad 24
+  inout IOC3, // MIO Pad 25
+  inout IOC4, // MIO Pad 26
+  inout IOC5, // MIO Pad 27
+  inout IOC6, // MIO Pad 28
+  inout IOC7, // MIO Pad 29
+  inout IOC8, // MIO Pad 30
+  inout IOC9, // MIO Pad 31
+  inout IOC10, // MIO Pad 32
+  inout IOC11  // MIO Pad 33
 );
 
   import top_earlgrey_pkg::*;
@@ -78,15 +78,15 @@
   // Special Signal Indices //
   ////////////////////////////
 
-  parameter int Tap0PadIdx = 20;
+  parameter int Tap0PadIdx = 22;
   parameter int Tap1PadIdx = 16;
-  parameter int Dft0PadIdx = 21;
-  parameter int Dft1PadIdx = 22;
-  parameter int TckPadIdx = 54;
-  parameter int TmsPadIdx = 55;
+  parameter int Dft0PadIdx = 23;
+  parameter int Dft1PadIdx = 34;
+  parameter int TckPadIdx = 58;
+  parameter int TmsPadIdx = 59;
   parameter int TrstNPadIdx = 18;
-  parameter int TdiPadIdx = 47;
-  parameter int TdoPadIdx = 48;
+  parameter int TdiPadIdx = 51;
+  parameter int TdoPadIdx = 52;
 
   // TODO: this is temporary and will be removed in the future.
   // This specifies the tie-off values of the muxed MIO/DIOs
@@ -167,7 +167,7 @@
   /////////////////////////
 
   // Only signals going to non-custom pads need to be tied off.
-  logic [65:0] unused_sig;
+  logic [70:0] unused_sig;
   assign dio_in[DioSpiHost0Sd0] = 1'b0;
   assign unused_sig[1] = dio_out[DioSpiHost0Sd0] ^ dio_oe[DioSpiHost0Sd0];
   assign dio_in[DioSpiHost0Sd1] = 1'b0;
@@ -202,18 +202,28 @@
   assign unused_sig[58] = mio_out[36] ^ mio_oe[36];
   assign mio_in[37] = 1'b0;
   assign unused_sig[59] = mio_out[37] ^ mio_oe[37];
-  assign dio_in[DioSysrstCtrlAonEcRstOutL] = 1'b0;
-  assign unused_sig[60] = dio_out[DioSysrstCtrlAonEcRstOutL] ^ dio_oe[DioSysrstCtrlAonEcRstOutL];
   assign mio_in[38] = 1'b0;
-  assign unused_sig[61] = mio_out[38] ^ mio_oe[38];
+  assign unused_sig[60] = mio_out[38] ^ mio_oe[38];
   assign mio_in[39] = 1'b0;
-  assign unused_sig[62] = mio_out[39] ^ mio_oe[39];
+  assign unused_sig[61] = mio_out[39] ^ mio_oe[39];
   assign mio_in[40] = 1'b0;
-  assign unused_sig[63] = mio_out[40] ^ mio_oe[40];
+  assign unused_sig[62] = mio_out[40] ^ mio_oe[40];
   assign mio_in[41] = 1'b0;
-  assign unused_sig[64] = mio_out[41] ^ mio_oe[41];
+  assign unused_sig[63] = mio_out[41] ^ mio_oe[41];
   assign mio_in[42] = 1'b0;
-  assign unused_sig[65] = mio_out[42] ^ mio_oe[42];
+  assign unused_sig[64] = mio_out[42] ^ mio_oe[42];
+  assign dio_in[DioSysrstCtrlAonEcRstOutL] = 1'b0;
+  assign unused_sig[65] = dio_out[DioSysrstCtrlAonEcRstOutL] ^ dio_oe[DioSysrstCtrlAonEcRstOutL];
+  assign dio_in[DioSysrstCtrlAonPwrbOut] = 1'b0;
+  assign unused_sig[66] = dio_out[DioSysrstCtrlAonPwrbOut] ^ dio_oe[DioSysrstCtrlAonPwrbOut];
+  assign mio_in[43] = 1'b0;
+  assign unused_sig[67] = mio_out[43] ^ mio_oe[43];
+  assign mio_in[44] = 1'b0;
+  assign unused_sig[68] = mio_out[44] ^ mio_oe[44];
+  assign mio_in[45] = 1'b0;
+  assign unused_sig[69] = mio_out[45] ^ mio_oe[45];
+  assign mio_in[46] = 1'b0;
+  assign unused_sig[70] = mio_out[46] ^ mio_oe[46];
 
   //////////////////////
   // Padring Instance //
@@ -248,35 +258,35 @@
       InputStd  // POR_N
     }),
     .MioPadType ({
-      InputStd, // IOR3
-      InputStd, // IOR2
-      InputStd, // IOR1
-      InputStd, // IOR0
       BidirOd, // IOC11
       BidirOd, // IOC10
-      BidirOd, // IOC9
-      BidirOd, // IOC8
-      InputStd, // IOC7
-      InputStd, // IOC6
-      InputStd, // IOC0
-      InputStd, // IOB11
-      InputStd, // IOB10
+      BidirStd, // IOC9
+      BidirStd, // IOC8
+      BidirStd, // IOC7
+      BidirStd, // IOC6
+      BidirStd, // IOC5
+      BidirStd, // IOC4
+      BidirStd, // IOC3
+      BidirStd, // IOC2
       BidirOd, // IOB9
-      BidirOd, // IOB8
-      InputStd, // IOB7
-      InputStd, // IOB6
-      InputStd, // IOB5
-      InputStd, // IOB4
-      InputStd, // IOB3
-      InputStd, // IOB2
-      InputStd, // IOB1
-      InputStd, // IOB0
-      BidirOd, // IOA5
-      BidirOd, // IOA4
-      InputStd, // IOA3
-      InputStd, // IOA2
-      InputStd, // IOA1
-      InputStd  // IOA0
+      BidirStd, // IOB8
+      BidirStd, // IOB7
+      BidirStd, // IOB6
+      BidirStd, // IOB5
+      BidirStd, // IOB4
+      BidirStd, // IOB3
+      BidirStd, // IOB2
+      BidirStd, // IOB1
+      BidirStd, // IOB0
+      BidirOd, // IOA8
+      BidirOd, // IOA7
+      BidirOd, // IOA6
+      BidirStd, // IOA5
+      BidirStd, // IOA4
+      BidirStd, // IOA3
+      BidirStd, // IOA2
+      BidirStd, // IOA1
+      BidirStd  // IOA0
     })
   ) u_padring (
   // This is only used for scan and DFT purposes
@@ -311,19 +321,16 @@
     }),
 
     .mio_pad_io ({
-      IOR3,
-      IOR2,
-      IOR1,
-      IOR0,
       IOC11,
       IOC10,
       IOC9,
       IOC8,
       IOC7,
       IOC6,
-      IOC0,
-      IOB11,
-      IOB10,
+      IOC5,
+      IOC4,
+      IOC3,
+      IOC2,
       IOB9,
       IOB8,
       IOB7,
@@ -334,6 +341,9 @@
       IOB2,
       IOB1,
       IOB0,
+      IOA8,
+      IOA7,
+      IOA6,
       IOA5,
       IOA4,
       IOA3,
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 3d2a58b..9785357 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -35,13 +35,13 @@
   input               rst_ni,
 
   // Multiplexed I/O
-  input        [42:0] mio_in_i,
-  output logic [42:0] mio_out_o,
-  output logic [42:0] mio_oe_o,
+  input        [46:0] mio_in_i,
+  output logic [46:0] mio_out_o,
+  output logic [46:0] mio_oe_o,
   // Dedicated I/O
-  input        [21:0] dio_in_i,
-  output logic [21:0] dio_out_o,
-  output logic [21:0] dio_oe_o,
+  input        [22:0] dio_in_i,
+  output logic [22:0] dio_out_o,
+  output logic [22:0] dio_oe_o,
 
   // pad attributes to padring
   output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr_o,
@@ -117,11 +117,11 @@
 
   // Signals
   logic [64:0] mio_p2d;
-  logic [67:0] mio_d2p;
-  logic [67:0] mio_en_d2p;
-  logic [21:0] dio_p2d;
-  logic [21:0] dio_d2p;
-  logic [21:0] dio_en_d2p;
+  logic [66:0] mio_d2p;
+  logic [66:0] mio_en_d2p;
+  logic [22:0] dio_p2d;
+  logic [22:0] dio_d2p;
+  logic [22:0] dio_en_d2p;
   // uart0
   logic        cio_uart0_rx_p2d;
   logic        cio_uart0_tx_d2p;
@@ -2776,7 +2776,6 @@
   assign mio_d2p[MioOutSysrstCtrlAonKey0Out] = cio_sysrst_ctrl_aon_key0_out_d2p;
   assign mio_d2p[MioOutSysrstCtrlAonKey1Out] = cio_sysrst_ctrl_aon_key1_out_d2p;
   assign mio_d2p[MioOutSysrstCtrlAonKey2Out] = cio_sysrst_ctrl_aon_key2_out_d2p;
-  assign mio_d2p[MioOutSysrstCtrlAonPwrbOut] = cio_sysrst_ctrl_aon_pwrb_out_d2p;
 
   // All muxed output enables
   assign mio_en_d2p[MioOutGpioGpio0] = cio_gpio_gpio_en_d2p[0];
@@ -2846,10 +2845,9 @@
   assign mio_en_d2p[MioOutSysrstCtrlAonKey0Out] = cio_sysrst_ctrl_aon_key0_out_en_d2p;
   assign mio_en_d2p[MioOutSysrstCtrlAonKey1Out] = cio_sysrst_ctrl_aon_key1_out_en_d2p;
   assign mio_en_d2p[MioOutSysrstCtrlAonKey2Out] = cio_sysrst_ctrl_aon_key2_out_en_d2p;
-  assign mio_en_d2p[MioOutSysrstCtrlAonPwrbOut] = cio_sysrst_ctrl_aon_pwrb_out_en_d2p;
 
   // All dedicated inputs
-  logic [21:0] unused_dio_p2d;
+  logic [22:0] unused_dio_p2d;
   assign cio_spi_host0_sd_p2d[0] = dio_p2d[DioSpiHost0Sd0];
   assign cio_spi_host0_sd_p2d[1] = dio_p2d[DioSpiHost0Sd1];
   assign cio_spi_host0_sd_p2d[2] = dio_p2d[DioSpiHost0Sd2];
@@ -2872,6 +2870,7 @@
   assign unused_dio_p2d[5] = dio_p2d[DioUsbdevTxModeSe];
   assign unused_dio_p2d[6] = dio_p2d[DioUsbdevSuspend];
   assign unused_dio_p2d[7] = dio_p2d[DioSysrstCtrlAonEcRstOutL];
+  assign unused_dio_p2d[8] = dio_p2d[DioSysrstCtrlAonPwrbOut];
 
     // All dedicated outputs
   assign dio_d2p[DioSpiHost0Sd0] = cio_spi_host0_sd_d2p[0];
@@ -2896,6 +2895,7 @@
   assign dio_d2p[DioUsbdevTxModeSe] = cio_usbdev_tx_mode_se_d2p;
   assign dio_d2p[DioUsbdevSuspend] = cio_usbdev_suspend_d2p;
   assign dio_d2p[DioSysrstCtrlAonEcRstOutL] = cio_sysrst_ctrl_aon_ec_rst_out_l_d2p;
+  assign dio_d2p[DioSysrstCtrlAonPwrbOut] = cio_sysrst_ctrl_aon_pwrb_out_d2p;
 
   // All dedicated output enables
   assign dio_en_d2p[DioSpiHost0Sd0] = cio_spi_host0_sd_en_d2p[0];
@@ -2920,6 +2920,7 @@
   assign dio_en_d2p[DioUsbdevTxModeSe] = cio_usbdev_tx_mode_se_en_d2p;
   assign dio_en_d2p[DioUsbdevSuspend] = cio_usbdev_suspend_en_d2p;
   assign dio_en_d2p[DioSysrstCtrlAonEcRstOutL] = cio_sysrst_ctrl_aon_ec_rst_out_l_en_d2p;
+  assign dio_en_d2p[DioSysrstCtrlAonPwrbOut] = cio_sysrst_ctrl_aon_pwrb_out_en_d2p;
 
 
   // make sure scanmode_i is never X (including during reset)
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
index db8ec70..067b5e6 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -609,8 +609,7 @@
     MioOutSysrstCtrlAonKey0Out = 64,
     MioOutSysrstCtrlAonKey1Out = 65,
     MioOutSysrstCtrlAonKey2Out = 66,
-    MioOutSysrstCtrlAonPwrbOut = 67,
-    MioOutCount = 68
+    MioOutCount = 67
   } mio_out_e;
 
   // Enumeration for DIO signals, used on both the top and chip-levels.
@@ -637,7 +636,8 @@
     DioUsbdevTxModeSe = 19,
     DioUsbdevSuspend = 20,
     DioSysrstCtrlAonEcRstOutL = 21,
-    DioCount = 22
+    DioSysrstCtrlAonPwrbOut = 22,
+    DioCount = 23
   } dio_e;
 
   // Raw MIO/DIO input array indices on chip-level.
@@ -650,43 +650,47 @@
     MioPadIoa3 = 3,
     MioPadIoa4 = 4,
     MioPadIoa5 = 5,
-    MioPadIob0 = 6,
-    MioPadIob1 = 7,
-    MioPadIob2 = 8,
-    MioPadIob3 = 9,
-    MioPadIob4 = 10,
-    MioPadIob5 = 11,
-    MioPadIob6 = 12,
-    MioPadIob7 = 13,
-    MioPadIob8 = 14,
-    MioPadIob9 = 15,
-    MioPadIob10 = 16,
-    MioPadIob11 = 17,
-    MioPadIoc0 = 18,
-    MioPadIoc1 = 19,
-    MioPadIoc2 = 20,
-    MioPadIoc3 = 21,
-    MioPadIoc4 = 22,
-    MioPadIoc5 = 23,
-    MioPadIoc6 = 24,
-    MioPadIoc7 = 25,
-    MioPadIoc8 = 26,
-    MioPadIoc9 = 27,
-    MioPadIoc10 = 28,
-    MioPadIoc11 = 29,
-    MioPadIor0 = 30,
-    MioPadIor1 = 31,
-    MioPadIor2 = 32,
-    MioPadIor3 = 33,
-    MioPadIor4 = 34,
-    MioPadIor5 = 35,
-    MioPadIor6 = 36,
-    MioPadIor7 = 37,
-    MioPadIor9 = 38,
-    MioPadIor10 = 39,
-    MioPadIor11 = 40,
-    MioPadIor12 = 41,
-    MioPadIor13 = 42,
+    MioPadIoa6 = 6,
+    MioPadIoa7 = 7,
+    MioPadIoa8 = 8,
+    MioPadIob0 = 9,
+    MioPadIob1 = 10,
+    MioPadIob2 = 11,
+    MioPadIob3 = 12,
+    MioPadIob4 = 13,
+    MioPadIob5 = 14,
+    MioPadIob6 = 15,
+    MioPadIob7 = 16,
+    MioPadIob8 = 17,
+    MioPadIob9 = 18,
+    MioPadIob10 = 19,
+    MioPadIob11 = 20,
+    MioPadIob12 = 21,
+    MioPadIoc0 = 22,
+    MioPadIoc1 = 23,
+    MioPadIoc2 = 24,
+    MioPadIoc3 = 25,
+    MioPadIoc4 = 26,
+    MioPadIoc5 = 27,
+    MioPadIoc6 = 28,
+    MioPadIoc7 = 29,
+    MioPadIoc8 = 30,
+    MioPadIoc9 = 31,
+    MioPadIoc10 = 32,
+    MioPadIoc11 = 33,
+    MioPadIoc12 = 34,
+    MioPadIor0 = 35,
+    MioPadIor1 = 36,
+    MioPadIor2 = 37,
+    MioPadIor3 = 38,
+    MioPadIor4 = 39,
+    MioPadIor5 = 40,
+    MioPadIor6 = 41,
+    MioPadIor7 = 42,
+    MioPadIor10 = 43,
+    MioPadIor11 = 44,
+    MioPadIor12 = 45,
+    MioPadIor13 = 46,
     MioPadCount
   } mio_pad_e;
 
@@ -714,6 +718,7 @@
     DioPadFlashTestMode3 = 20,
     DioPadFlashTestVolt = 21,
     DioPadIor8 = 22,
+    DioPadIor9 = 23,
     DioPadCount
   } dio_pad_e;
 
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index fc675c3..148d141 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -1139,8 +1139,8 @@
 
 // PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
 //  0 and 1 are tied to value 0 and 1
-#define NUM_MIO_PADS 43
-#define NUM_DIO_PADS 22
+#define NUM_MIO_PADS 47
+#define NUM_DIO_PADS 23
 
 #define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
 
@@ -1228,44 +1228,48 @@
   kTopEarlgreyPinmuxInselIoa3 = 5, /**< MIO Pad 3 */
   kTopEarlgreyPinmuxInselIoa4 = 6, /**< MIO Pad 4 */
   kTopEarlgreyPinmuxInselIoa5 = 7, /**< MIO Pad 5 */
-  kTopEarlgreyPinmuxInselIob0 = 8, /**< MIO Pad 6 */
-  kTopEarlgreyPinmuxInselIob1 = 9, /**< MIO Pad 7 */
-  kTopEarlgreyPinmuxInselIob2 = 10, /**< MIO Pad 8 */
-  kTopEarlgreyPinmuxInselIob3 = 11, /**< MIO Pad 9 */
-  kTopEarlgreyPinmuxInselIob4 = 12, /**< MIO Pad 10 */
-  kTopEarlgreyPinmuxInselIob5 = 13, /**< MIO Pad 11 */
-  kTopEarlgreyPinmuxInselIob6 = 14, /**< MIO Pad 12 */
-  kTopEarlgreyPinmuxInselIob7 = 15, /**< MIO Pad 13 */
-  kTopEarlgreyPinmuxInselIob8 = 16, /**< MIO Pad 14 */
-  kTopEarlgreyPinmuxInselIob9 = 17, /**< MIO Pad 15 */
-  kTopEarlgreyPinmuxInselIob10 = 18, /**< MIO Pad 16 */
-  kTopEarlgreyPinmuxInselIob11 = 19, /**< MIO Pad 17 */
-  kTopEarlgreyPinmuxInselIoc0 = 20, /**< MIO Pad 18 */
-  kTopEarlgreyPinmuxInselIoc1 = 21, /**< MIO Pad 19 */
-  kTopEarlgreyPinmuxInselIoc2 = 22, /**< MIO Pad 20 */
-  kTopEarlgreyPinmuxInselIoc3 = 23, /**< MIO Pad 21 */
-  kTopEarlgreyPinmuxInselIoc4 = 24, /**< MIO Pad 22 */
-  kTopEarlgreyPinmuxInselIoc5 = 25, /**< MIO Pad 23 */
-  kTopEarlgreyPinmuxInselIoc6 = 26, /**< MIO Pad 24 */
-  kTopEarlgreyPinmuxInselIoc7 = 27, /**< MIO Pad 25 */
-  kTopEarlgreyPinmuxInselIoc8 = 28, /**< MIO Pad 26 */
-  kTopEarlgreyPinmuxInselIoc9 = 29, /**< MIO Pad 27 */
-  kTopEarlgreyPinmuxInselIoc10 = 30, /**< MIO Pad 28 */
-  kTopEarlgreyPinmuxInselIoc11 = 31, /**< MIO Pad 29 */
-  kTopEarlgreyPinmuxInselIor0 = 32, /**< MIO Pad 30 */
-  kTopEarlgreyPinmuxInselIor1 = 33, /**< MIO Pad 31 */
-  kTopEarlgreyPinmuxInselIor2 = 34, /**< MIO Pad 32 */
-  kTopEarlgreyPinmuxInselIor3 = 35, /**< MIO Pad 33 */
-  kTopEarlgreyPinmuxInselIor4 = 36, /**< MIO Pad 34 */
-  kTopEarlgreyPinmuxInselIor5 = 37, /**< MIO Pad 35 */
-  kTopEarlgreyPinmuxInselIor6 = 38, /**< MIO Pad 36 */
-  kTopEarlgreyPinmuxInselIor7 = 39, /**< MIO Pad 37 */
-  kTopEarlgreyPinmuxInselIor9 = 40, /**< MIO Pad 38 */
-  kTopEarlgreyPinmuxInselIor10 = 41, /**< MIO Pad 39 */
-  kTopEarlgreyPinmuxInselIor11 = 42, /**< MIO Pad 40 */
-  kTopEarlgreyPinmuxInselIor12 = 43, /**< MIO Pad 41 */
-  kTopEarlgreyPinmuxInselIor13 = 44, /**< MIO Pad 42 */
-  kTopEarlgreyPinmuxInselLast = 44, /**< \internal Last valid insel value */
+  kTopEarlgreyPinmuxInselIoa6 = 8, /**< MIO Pad 6 */
+  kTopEarlgreyPinmuxInselIoa7 = 9, /**< MIO Pad 7 */
+  kTopEarlgreyPinmuxInselIoa8 = 10, /**< MIO Pad 8 */
+  kTopEarlgreyPinmuxInselIob0 = 11, /**< MIO Pad 9 */
+  kTopEarlgreyPinmuxInselIob1 = 12, /**< MIO Pad 10 */
+  kTopEarlgreyPinmuxInselIob2 = 13, /**< MIO Pad 11 */
+  kTopEarlgreyPinmuxInselIob3 = 14, /**< MIO Pad 12 */
+  kTopEarlgreyPinmuxInselIob4 = 15, /**< MIO Pad 13 */
+  kTopEarlgreyPinmuxInselIob5 = 16, /**< MIO Pad 14 */
+  kTopEarlgreyPinmuxInselIob6 = 17, /**< MIO Pad 15 */
+  kTopEarlgreyPinmuxInselIob7 = 18, /**< MIO Pad 16 */
+  kTopEarlgreyPinmuxInselIob8 = 19, /**< MIO Pad 17 */
+  kTopEarlgreyPinmuxInselIob9 = 20, /**< MIO Pad 18 */
+  kTopEarlgreyPinmuxInselIob10 = 21, /**< MIO Pad 19 */
+  kTopEarlgreyPinmuxInselIob11 = 22, /**< MIO Pad 20 */
+  kTopEarlgreyPinmuxInselIob12 = 23, /**< MIO Pad 21 */
+  kTopEarlgreyPinmuxInselIoc0 = 24, /**< MIO Pad 22 */
+  kTopEarlgreyPinmuxInselIoc1 = 25, /**< MIO Pad 23 */
+  kTopEarlgreyPinmuxInselIoc2 = 26, /**< MIO Pad 24 */
+  kTopEarlgreyPinmuxInselIoc3 = 27, /**< MIO Pad 25 */
+  kTopEarlgreyPinmuxInselIoc4 = 28, /**< MIO Pad 26 */
+  kTopEarlgreyPinmuxInselIoc5 = 29, /**< MIO Pad 27 */
+  kTopEarlgreyPinmuxInselIoc6 = 30, /**< MIO Pad 28 */
+  kTopEarlgreyPinmuxInselIoc7 = 31, /**< MIO Pad 29 */
+  kTopEarlgreyPinmuxInselIoc8 = 32, /**< MIO Pad 30 */
+  kTopEarlgreyPinmuxInselIoc9 = 33, /**< MIO Pad 31 */
+  kTopEarlgreyPinmuxInselIoc10 = 34, /**< MIO Pad 32 */
+  kTopEarlgreyPinmuxInselIoc11 = 35, /**< MIO Pad 33 */
+  kTopEarlgreyPinmuxInselIoc12 = 36, /**< MIO Pad 34 */
+  kTopEarlgreyPinmuxInselIor0 = 37, /**< MIO Pad 35 */
+  kTopEarlgreyPinmuxInselIor1 = 38, /**< MIO Pad 36 */
+  kTopEarlgreyPinmuxInselIor2 = 39, /**< MIO Pad 37 */
+  kTopEarlgreyPinmuxInselIor3 = 40, /**< MIO Pad 38 */
+  kTopEarlgreyPinmuxInselIor4 = 41, /**< MIO Pad 39 */
+  kTopEarlgreyPinmuxInselIor5 = 42, /**< MIO Pad 40 */
+  kTopEarlgreyPinmuxInselIor6 = 43, /**< MIO Pad 41 */
+  kTopEarlgreyPinmuxInselIor7 = 44, /**< MIO Pad 42 */
+  kTopEarlgreyPinmuxInselIor10 = 45, /**< MIO Pad 43 */
+  kTopEarlgreyPinmuxInselIor11 = 46, /**< MIO Pad 44 */
+  kTopEarlgreyPinmuxInselIor12 = 47, /**< MIO Pad 45 */
+  kTopEarlgreyPinmuxInselIor13 = 48, /**< MIO Pad 46 */
+  kTopEarlgreyPinmuxInselLast = 48, /**< \internal Last valid insel value */
 } top_earlgrey_pinmux_insel_t;
 
 /**
@@ -1278,44 +1282,48 @@
   kTopEarlgreyPinmuxMioOutIoa3 = 3, /**< MIO Pad 3 */
   kTopEarlgreyPinmuxMioOutIoa4 = 4, /**< MIO Pad 4 */
   kTopEarlgreyPinmuxMioOutIoa5 = 5, /**< MIO Pad 5 */
-  kTopEarlgreyPinmuxMioOutIob0 = 6, /**< MIO Pad 6 */
-  kTopEarlgreyPinmuxMioOutIob1 = 7, /**< MIO Pad 7 */
-  kTopEarlgreyPinmuxMioOutIob2 = 8, /**< MIO Pad 8 */
-  kTopEarlgreyPinmuxMioOutIob3 = 9, /**< MIO Pad 9 */
-  kTopEarlgreyPinmuxMioOutIob4 = 10, /**< MIO Pad 10 */
-  kTopEarlgreyPinmuxMioOutIob5 = 11, /**< MIO Pad 11 */
-  kTopEarlgreyPinmuxMioOutIob6 = 12, /**< MIO Pad 12 */
-  kTopEarlgreyPinmuxMioOutIob7 = 13, /**< MIO Pad 13 */
-  kTopEarlgreyPinmuxMioOutIob8 = 14, /**< MIO Pad 14 */
-  kTopEarlgreyPinmuxMioOutIob9 = 15, /**< MIO Pad 15 */
-  kTopEarlgreyPinmuxMioOutIob10 = 16, /**< MIO Pad 16 */
-  kTopEarlgreyPinmuxMioOutIob11 = 17, /**< MIO Pad 17 */
-  kTopEarlgreyPinmuxMioOutIoc0 = 18, /**< MIO Pad 18 */
-  kTopEarlgreyPinmuxMioOutIoc1 = 19, /**< MIO Pad 19 */
-  kTopEarlgreyPinmuxMioOutIoc2 = 20, /**< MIO Pad 20 */
-  kTopEarlgreyPinmuxMioOutIoc3 = 21, /**< MIO Pad 21 */
-  kTopEarlgreyPinmuxMioOutIoc4 = 22, /**< MIO Pad 22 */
-  kTopEarlgreyPinmuxMioOutIoc5 = 23, /**< MIO Pad 23 */
-  kTopEarlgreyPinmuxMioOutIoc6 = 24, /**< MIO Pad 24 */
-  kTopEarlgreyPinmuxMioOutIoc7 = 25, /**< MIO Pad 25 */
-  kTopEarlgreyPinmuxMioOutIoc8 = 26, /**< MIO Pad 26 */
-  kTopEarlgreyPinmuxMioOutIoc9 = 27, /**< MIO Pad 27 */
-  kTopEarlgreyPinmuxMioOutIoc10 = 28, /**< MIO Pad 28 */
-  kTopEarlgreyPinmuxMioOutIoc11 = 29, /**< MIO Pad 29 */
-  kTopEarlgreyPinmuxMioOutIor0 = 30, /**< MIO Pad 30 */
-  kTopEarlgreyPinmuxMioOutIor1 = 31, /**< MIO Pad 31 */
-  kTopEarlgreyPinmuxMioOutIor2 = 32, /**< MIO Pad 32 */
-  kTopEarlgreyPinmuxMioOutIor3 = 33, /**< MIO Pad 33 */
-  kTopEarlgreyPinmuxMioOutIor4 = 34, /**< MIO Pad 34 */
-  kTopEarlgreyPinmuxMioOutIor5 = 35, /**< MIO Pad 35 */
-  kTopEarlgreyPinmuxMioOutIor6 = 36, /**< MIO Pad 36 */
-  kTopEarlgreyPinmuxMioOutIor7 = 37, /**< MIO Pad 37 */
-  kTopEarlgreyPinmuxMioOutIor9 = 38, /**< MIO Pad 38 */
-  kTopEarlgreyPinmuxMioOutIor10 = 39, /**< MIO Pad 39 */
-  kTopEarlgreyPinmuxMioOutIor11 = 40, /**< MIO Pad 40 */
-  kTopEarlgreyPinmuxMioOutIor12 = 41, /**< MIO Pad 41 */
-  kTopEarlgreyPinmuxMioOutIor13 = 42, /**< MIO Pad 42 */
-  kTopEarlgreyPinmuxMioOutLast = 42, /**< \internal Last valid mio output */
+  kTopEarlgreyPinmuxMioOutIoa6 = 6, /**< MIO Pad 6 */
+  kTopEarlgreyPinmuxMioOutIoa7 = 7, /**< MIO Pad 7 */
+  kTopEarlgreyPinmuxMioOutIoa8 = 8, /**< MIO Pad 8 */
+  kTopEarlgreyPinmuxMioOutIob0 = 9, /**< MIO Pad 9 */
+  kTopEarlgreyPinmuxMioOutIob1 = 10, /**< MIO Pad 10 */
+  kTopEarlgreyPinmuxMioOutIob2 = 11, /**< MIO Pad 11 */
+  kTopEarlgreyPinmuxMioOutIob3 = 12, /**< MIO Pad 12 */
+  kTopEarlgreyPinmuxMioOutIob4 = 13, /**< MIO Pad 13 */
+  kTopEarlgreyPinmuxMioOutIob5 = 14, /**< MIO Pad 14 */
+  kTopEarlgreyPinmuxMioOutIob6 = 15, /**< MIO Pad 15 */
+  kTopEarlgreyPinmuxMioOutIob7 = 16, /**< MIO Pad 16 */
+  kTopEarlgreyPinmuxMioOutIob8 = 17, /**< MIO Pad 17 */
+  kTopEarlgreyPinmuxMioOutIob9 = 18, /**< MIO Pad 18 */
+  kTopEarlgreyPinmuxMioOutIob10 = 19, /**< MIO Pad 19 */
+  kTopEarlgreyPinmuxMioOutIob11 = 20, /**< MIO Pad 20 */
+  kTopEarlgreyPinmuxMioOutIob12 = 21, /**< MIO Pad 21 */
+  kTopEarlgreyPinmuxMioOutIoc0 = 22, /**< MIO Pad 22 */
+  kTopEarlgreyPinmuxMioOutIoc1 = 23, /**< MIO Pad 23 */
+  kTopEarlgreyPinmuxMioOutIoc2 = 24, /**< MIO Pad 24 */
+  kTopEarlgreyPinmuxMioOutIoc3 = 25, /**< MIO Pad 25 */
+  kTopEarlgreyPinmuxMioOutIoc4 = 26, /**< MIO Pad 26 */
+  kTopEarlgreyPinmuxMioOutIoc5 = 27, /**< MIO Pad 27 */
+  kTopEarlgreyPinmuxMioOutIoc6 = 28, /**< MIO Pad 28 */
+  kTopEarlgreyPinmuxMioOutIoc7 = 29, /**< MIO Pad 29 */
+  kTopEarlgreyPinmuxMioOutIoc8 = 30, /**< MIO Pad 30 */
+  kTopEarlgreyPinmuxMioOutIoc9 = 31, /**< MIO Pad 31 */
+  kTopEarlgreyPinmuxMioOutIoc10 = 32, /**< MIO Pad 32 */
+  kTopEarlgreyPinmuxMioOutIoc11 = 33, /**< MIO Pad 33 */
+  kTopEarlgreyPinmuxMioOutIoc12 = 34, /**< MIO Pad 34 */
+  kTopEarlgreyPinmuxMioOutIor0 = 35, /**< MIO Pad 35 */
+  kTopEarlgreyPinmuxMioOutIor1 = 36, /**< MIO Pad 36 */
+  kTopEarlgreyPinmuxMioOutIor2 = 37, /**< MIO Pad 37 */
+  kTopEarlgreyPinmuxMioOutIor3 = 38, /**< MIO Pad 38 */
+  kTopEarlgreyPinmuxMioOutIor4 = 39, /**< MIO Pad 39 */
+  kTopEarlgreyPinmuxMioOutIor5 = 40, /**< MIO Pad 40 */
+  kTopEarlgreyPinmuxMioOutIor6 = 41, /**< MIO Pad 41 */
+  kTopEarlgreyPinmuxMioOutIor7 = 42, /**< MIO Pad 42 */
+  kTopEarlgreyPinmuxMioOutIor10 = 43, /**< MIO Pad 43 */
+  kTopEarlgreyPinmuxMioOutIor11 = 44, /**< MIO Pad 44 */
+  kTopEarlgreyPinmuxMioOutIor12 = 45, /**< MIO Pad 45 */
+  kTopEarlgreyPinmuxMioOutIor13 = 46, /**< MIO Pad 46 */
+  kTopEarlgreyPinmuxMioOutLast = 46, /**< \internal Last valid mio output */
 } top_earlgrey_pinmux_mio_out_t;
 
 /**
@@ -1392,8 +1400,7 @@
   kTopEarlgreyPinmuxOutselSysrstCtrlAonKey0Out = 67, /**< Peripheral Output 64 */
   kTopEarlgreyPinmuxOutselSysrstCtrlAonKey1Out = 68, /**< Peripheral Output 65 */
   kTopEarlgreyPinmuxOutselSysrstCtrlAonKey2Out = 69, /**< Peripheral Output 66 */
-  kTopEarlgreyPinmuxOutselSysrstCtrlAonPwrbOut = 70, /**< Peripheral Output 67 */
-  kTopEarlgreyPinmuxOutselLast = 70, /**< \internal Last valid outsel value */
+  kTopEarlgreyPinmuxOutselLast = 69, /**< \internal Last valid outsel value */
 } top_earlgrey_pinmux_outsel_t;
 
 /**
diff --git a/hw/top_englishbreakfast/data/pins_cw305.xdc b/hw/top_englishbreakfast/data/pins_cw305.xdc
index a6d678a..ad5bcd2 100644
--- a/hw/top_englishbreakfast/data/pins_cw305.xdc
+++ b/hw/top_englishbreakfast/data/pins_cw305.xdc
@@ -8,9 +8,9 @@
 ## set via clocks.xdc
 
 ## LEDs
-set_property -dict { PACKAGE_PIN T2  DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOB2 }]
-set_property -dict { PACKAGE_PIN T3  DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOB3 }]
-set_property -dict { PACKAGE_PIN T4  DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOB4 }]
+set_property -dict { PACKAGE_PIN T2  DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOA8 }]
+set_property -dict { PACKAGE_PIN T3  DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOB0 }]
+set_property -dict { PACKAGE_PIN T4  DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOB1 }]
 
 ## Buttons
 set_property -dict { PACKAGE_PIN R1 IOSTANDARD LVCMOS33 } [get_ports { POR_N }]; #pushbutton
@@ -26,20 +26,20 @@
 set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_D0 }]; #SDI (USB_A14)
 set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_D1 }]; #SDO (USB_A15)
 set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_CS_L }]; #CSB (USB_A16)
-set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { IOC0 }]; #JTAG TRST (USB_A17)
+set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { IOB9 }]; #JTAG TRST (USB_A17)
 set_property -dict { PACKAGE_PIN D6 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { IO_JSRST_N }]; #JTAG SRST (USB_A18)
-set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB10 }]; #JTAG/SPI (USB_A19)
-set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB11 }]; #Bootstrap (USB_A20)
+set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB7 }]; #JTAG/SPI (USB_A19)
+set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB8 }]; #Bootstrap (USB_A20)
 
 ## OTHER IO
 set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { IOA4 }]; #JP3.B16
 set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports { IOA5 }]; #JP3.C13
-set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { IOB0 }]; #JP3.D15
-set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { IOB1 }]; #JP3.E15
-set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { IOB5 }]; #JP3.E13
-set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { IOB6 }]; #JP3.F15
-set_property -dict { PACKAGE_PIN E11 IOSTANDARD LVCMOS33 } [get_ports { IOB7 }]; #JP3.E11
-set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { IOB8 }]; #JP3.F13
+set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { IOA6 }]; #JP3.D15
+set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { IOA7 }]; #JP3.E15
+set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { IOB2 }]; #JP3.E13
+set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { IOB3 }]; #JP3.F15
+set_property -dict { PACKAGE_PIN E11 IOSTANDARD LVCMOS33 } [get_ports { IOB4 }]; #JP3.E11
+set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { IOB5 }]; #JP3.F13
 
 set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { USB_P }]; #JP3.C16
 set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { USB_N }]; #JP3.D13
@@ -53,9 +53,9 @@
 
 ## 20-Pin Connector (JP1)
 
-set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { IOR3 }];     #JP1 PIN 10 (UART)
-set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { IOR2 }];     #JP1 PIN 12 (UART)
-set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { IOB9 }];    #JP1 PIN 16 TIO4 (Trigger)
+set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { IOC11 }];     #JP1 PIN 10 (UART)
+set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { IOC10 }];     #JP1 PIN 12 (UART)
+set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { IOB6 }];    #JP1 PIN 16 TIO4 (Trigger)
 set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { TIO_CLKOUT }]; #JP1 PIN 4 TIO_HS1. Clock sync capture board.
 
 
diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
index c26ad14..5b6c531 100644
--- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
+++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -801,7 +801,6 @@
     //
     // Optionally, each pad can also have a 'desc' field for further description.
     pads: [
-      // TODO: this needs to be updated to the latest ASIC pinout.
       // Dedicated
       { name: 'POR_N'           , type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'System reset'},
       { name: 'SPI_HOST_D0'     , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
@@ -826,49 +825,52 @@
       { name: 'FLASH_TEST_MODE3', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'},
       { name: 'FLASH_TEST_VOLT' , type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test voltage input'},
       // IOA
-      { name: 'IOA0'            , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOA1'            , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOA2'            , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOA3'            , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOA4'            , type: 'BidirOd' , bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOA5'            , type: 'BidirOd' , bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA0'            , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA1'            , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA2'            , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA3'            , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA4'            , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA5'            , type: 'BidirStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA6'            , type: 'BidirOd',  bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA7'            , type: 'BidirOd',  bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOA8'            , type: 'BidirOd',  bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
       // IOB
-      { name: 'IOB0'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB1'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB2'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB3'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB4'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB5'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB6'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB7'            , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB8'            , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB0'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB1'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB2'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB3'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB4'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB5'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB6'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB7'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB8'            , type: 'BidirStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
       { name: 'IOB9'            , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB10'           , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOB11'           , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB10'           , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB11'           , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOB12'           , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
       // IOC
-      { name: 'IOC0'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC1'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC2'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC3'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC4'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC5'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC6'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC7'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC8'            , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOC9'            , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC0'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC1'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC2'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC3'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC4'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC5'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC6'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC7'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC8'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC9'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
       { name: 'IOC10'           , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
       { name: 'IOC11'           , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOC12'           , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
       // IOR
-      { name: 'IOR0'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR1'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR2'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR3'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR4'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR5'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR6'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR7'            , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR8'            , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
-      { name: 'IOR9'            , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR0'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR1'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR2'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR3'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR4'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR5'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR6'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+      { name: 'IOR7'            , type: 'BidirStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
       { name: 'IOR10'           , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
       { name: 'IOR11'           , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
       { name: 'IOR12'           , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
@@ -953,13 +955,14 @@
       pinout: {
         remove_pads: [
           'CC1', 'CC2',
-          'IOC1', 'IOC2','IOC3','IOC4','IOC5','IOC6','IOC7','IOC8','IOC9','IOC10','IOC11',
           'SPI_DEV_D2', 'SPI_DEV_D3'
           'SPI_HOST_CLK', 'SPI_HOST_CS_L',
           'SPI_HOST_D0', 'SPI_HOST_D1', 'SPI_HOST_D2', 'SPI_HOST_D3',
           'FLASH_TEST_VOLT',
           'FLASH_TEST_MODE0', 'FLASH_TEST_MODE1', 'FLASH_TEST_MODE2', 'FLASH_TEST_MODE3',
-          'IOR0','IOR1','IOR4', 'IOR5', 'IOR6', 'IOR7', 'IOR8', 'IOR9', 'IOR10', 'IOR11', 'IOR12', 'IOR13'
+          'IOB10', 'IOB11', 'IOB12',
+          'IOC0', 'IOC1', 'IOC2', 'IOC3', 'IOC4', 'IOC5', 'IOC6', 'IOC7', 'IOC8', 'IOC9', 'IOC12',
+          'IOR0', 'IOR1', 'IOR2', 'IOR3', 'IOR4', 'IOR5', 'IOR6', 'IOR7', 'IOR10', 'IOR11', 'IOR12', 'IOR13'
         ],
 
         add_pads: [
@@ -979,14 +982,14 @@
       pinmux: {
         special_signals: [
           // Straps
-          { name: 'tap0',   pad: 'IOC2' ,        desc: 'TAP strap signal, maps to a stubbed-off MIO.'  },
-          { name: 'tap1',   pad: 'IOB10',        desc: 'TAP strap signal, maps to MIO pad 16.'         },
-          { name: 'dft0',   pad: 'IOC3' ,        desc: 'DFT strap signal, maps to a stubbed-off MIO.'  },
-          { name: 'dft1',   pad: 'IOC4' ,        desc: 'DFT strap signal, maps to a stubbed-off MIO.'  },
+          { name: 'tap0',   pad: 'IOC0' ,        desc: 'TAP strap signal, maps to a stubbed-off MIO.'  },
+          { name: 'tap1',   pad: 'IOB7',         desc: 'TAP strap signal, maps to MIO pad 16.'         },
+          { name: 'dft0',   pad: 'IOC1' ,        desc: 'DFT strap signal, maps to a stubbed-off MIO.'  },
+          { name: 'dft1',   pad: 'IOC12',        desc: 'DFT strap signal, maps to a stubbed-off MIO.'  },
           // JTAG
           { name: 'tck',    pad: 'SPI_DEV_CLK' , desc: 'JTAG tck signal, overlaid on SPI_DEV.'   },
           { name: 'tms',    pad: 'SPI_DEV_CS_L', desc: 'JTAG tms signal, overlaid on SPI_DEV.'   },
-          { name: 'trst_n', pad: 'IOC0'        , desc: 'JTAG trst_n signal, maps to MIO pad 18.' },
+          { name: 'trst_n', pad: 'IOB9'        , desc: 'JTAG trst_n signal, maps to MIO pad 18.' },
           { name: 'tdi',    pad: 'SPI_DEV_D0'  , desc: 'JTAG tdi signal, overlaid on SPI_DEV.'   },
           { name: 'tdo',    pad: 'SPI_DEV_D1'  , desc: 'JTAG tdo signal, overlaid on SPI_DEV.'   },
         ],
diff --git a/hw/top_englishbreakfast/rtl/chip_englishbreakfast_verilator.sv b/hw/top_englishbreakfast/rtl/chip_englishbreakfast_verilator.sv
index 64893c7..0c94c5e 100644
--- a/hw/top_englishbreakfast/rtl/chip_englishbreakfast_verilator.sv
+++ b/hw/top_englishbreakfast/rtl/chip_englishbreakfast_verilator.sv
@@ -30,9 +30,9 @@
   logic IO_JTCK, IO_JTMS, IO_JTRST_N, IO_JTDI, IO_JTDO;
 
   // TODO: instantiate padring and route these signals through that module
-  logic [20:0] dio_in;
-  logic [20:0] dio_out;
-  logic [20:0] dio_oe;
+  logic [pinmux_pkg::NDioPads-1:0] dio_in;
+  logic [pinmux_pkg::NDioPads-1:0] dio_out;
+  logic [pinmux_pkg::NDioPads-1:0] dio_oe;
 
   always_comb begin : assign_dio_in
     dio_in = '0;
@@ -65,13 +65,15 @@
   assign cio_usbdev_se0_en_d2p = dio_oe[DioUsbdevSe0];
   assign cio_spi_device_sdo_en_d2p = dio_oe[DioSpiDeviceSd1];
 
-  logic [43:0] mio_in;
-  logic [43:0] mio_out;
-  logic [43:0] mio_oe;
+  logic [pinmux_pkg::NMioPads-1:0] mio_in;
+  logic [pinmux_pkg::NMioPads-1:0] mio_out;
+  logic [pinmux_pkg::NMioPads-1:0] mio_oe;
 
-  assign mio_in = {11'h0,
-                   cio_uart_rx_p2d,
-                   cio_gpio_p2d};
+  always_comb begin : assign_mio_in
+    mio_in = '0;
+    mio_in[32] = cio_uart_rx_p2d;
+    mio_in[31:0] = cio_gpio_p2d;
+  end
 
   assign cio_gpio_d2p       = mio_out[31:0];
   assign cio_gpio_en_d2p    = mio_oe[31:0];