)]}'
{
  "commit": "3a6f696c88521bd334c508222cdf28de72416f86",
  "tree": "09f987e320f908590f6497842d6576db998fb371",
  "parents": [
    "84f7b4c15f037168261b52c838418ba4d69d5c96"
  ],
  "author": {
    "name": "Eunchan Kim",
    "email": "eunchan@opentitan.org",
    "time": "Wed Apr 07 10:53:10 2021 -0700"
  },
  "committer": {
    "name": "Eunchan Kim",
    "email": "eunchan@opentitan.org",
    "time": "Wed Apr 07 13:21:42 2021 -0700"
  },
  "message": "[spi_dev] Revise SDC for generated clocks in SPI_DEVICE\n\nBased on the feedbacks from Tim Chen and Don Sanders, the generated\nclocks are added to SPI_DEV_CLK clock group and as async to IO_DIV4.\n\nThe SRAM clock definition is removed so DC will check timing for IO_DIV4\nand SPI_DEV_IN_CLK separately.\n\nSigned-off-by: Eunchan Kim \u003ceunchan@opentitan.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "84ac04b67796f58d7ff0e1ec45f5dc644fc21f30",
      "old_mode": 33188,
      "old_path": "hw/top_earlgrey/syn/asic.constraints.sdc",
      "new_id": "94794cea2f34aa7f2622b9124d69b89e2d2940e4",
      "new_mode": 33188,
      "new_path": "hw/top_earlgrey/syn/asic.constraints.sdc"
    }
  ]
}