| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // Register Top module auto-generated by `reggen` |
| |
| `include "prim_assert.sv" |
| |
| module sensor_ctrl_reg_top ( |
| input clk_i, |
| input rst_ni, |
| input tlul_pkg::tl_h2d_t tl_i, |
| output tlul_pkg::tl_d2h_t tl_o, |
| // To HW |
| output sensor_ctrl_reg_pkg::sensor_ctrl_reg2hw_t reg2hw, // Write |
| input sensor_ctrl_reg_pkg::sensor_ctrl_hw2reg_t hw2reg, // Read |
| |
| // Integrity check errors |
| output logic intg_err_o, |
| |
| // Config |
| input devmode_i // If 1, explicit error return for unmapped register access |
| ); |
| |
| import sensor_ctrl_reg_pkg::* ; |
| |
| localparam int AW = 6; |
| localparam int DW = 32; |
| localparam int DBW = DW/8; // Byte Width |
| |
| // register signals |
| logic reg_we; |
| logic reg_re; |
| logic [AW-1:0] reg_addr; |
| logic [DW-1:0] reg_wdata; |
| logic [DBW-1:0] reg_be; |
| logic [DW-1:0] reg_rdata; |
| logic reg_error; |
| |
| logic addrmiss, wr_err; |
| |
| logic [DW-1:0] reg_rdata_next; |
| logic reg_busy; |
| |
| tlul_pkg::tl_h2d_t tl_reg_h2d; |
| tlul_pkg::tl_d2h_t tl_reg_d2h; |
| |
| |
| // incoming payload check |
| logic intg_err; |
| tlul_cmd_intg_chk u_chk ( |
| .tl_i(tl_i), |
| .err_o(intg_err) |
| ); |
| |
| // also check for spurious write enables |
| logic reg_we_err; |
| logic [9:0] reg_we_check; |
| prim_reg_we_check #( |
| .OneHotWidth(10) |
| ) u_prim_reg_we_check ( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .oh_i (reg_we_check), |
| .en_i (reg_we && !addrmiss), |
| .err_o (reg_we_err) |
| ); |
| |
| logic err_q; |
| always_ff @(posedge clk_i or negedge rst_ni) begin |
| if (!rst_ni) begin |
| err_q <= '0; |
| end else if (intg_err || reg_we_err) begin |
| err_q <= 1'b1; |
| end |
| end |
| |
| // integrity error output is permanent and should be used for alert generation |
| // register errors are transactional |
| assign intg_err_o = err_q | intg_err | reg_we_err; |
| |
| // outgoing integrity generation |
| tlul_pkg::tl_d2h_t tl_o_pre; |
| tlul_rsp_intg_gen #( |
| .EnableRspIntgGen(1), |
| .EnableDataIntgGen(1) |
| ) u_rsp_intg_gen ( |
| .tl_i(tl_o_pre), |
| .tl_o(tl_o) |
| ); |
| |
| assign tl_reg_h2d = tl_i; |
| assign tl_o_pre = tl_reg_d2h; |
| |
| tlul_adapter_reg #( |
| .RegAw(AW), |
| .RegDw(DW), |
| .EnableDataIntgGen(0) |
| ) u_reg_if ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| .tl_i (tl_reg_h2d), |
| .tl_o (tl_reg_d2h), |
| |
| .en_ifetch_i(prim_mubi_pkg::MuBi4False), |
| .intg_error_o(), |
| |
| .we_o (reg_we), |
| .re_o (reg_re), |
| .addr_o (reg_addr), |
| .wdata_o (reg_wdata), |
| .be_o (reg_be), |
| .busy_i (reg_busy), |
| .rdata_i (reg_rdata), |
| .error_i (reg_error) |
| ); |
| |
| // cdc oversampling signals |
| |
| assign reg_rdata = reg_rdata_next ; |
| assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err; |
| |
| // Define SW related signals |
| // Format: <reg>_<field>_{wd|we|qs} |
| // or <reg>_{wd|we|qs} if field == 1 or 0 |
| logic intr_state_we; |
| logic intr_state_io_status_change_qs; |
| logic intr_state_io_status_change_wd; |
| logic intr_state_init_status_change_qs; |
| logic intr_state_init_status_change_wd; |
| logic intr_enable_we; |
| logic intr_enable_io_status_change_qs; |
| logic intr_enable_io_status_change_wd; |
| logic intr_enable_init_status_change_qs; |
| logic intr_enable_init_status_change_wd; |
| logic intr_test_we; |
| logic intr_test_io_status_change_wd; |
| logic intr_test_init_status_change_wd; |
| logic alert_test_we; |
| logic alert_test_recov_alert_wd; |
| logic alert_test_fatal_alert_wd; |
| logic cfg_regwen_we; |
| logic cfg_regwen_qs; |
| logic cfg_regwen_wd; |
| logic alert_trig_we; |
| logic alert_trig_val_0_qs; |
| logic alert_trig_val_0_wd; |
| logic alert_trig_val_1_qs; |
| logic alert_trig_val_1_wd; |
| logic alert_trig_val_2_qs; |
| logic alert_trig_val_2_wd; |
| logic alert_trig_val_3_qs; |
| logic alert_trig_val_3_wd; |
| logic alert_trig_val_4_qs; |
| logic alert_trig_val_4_wd; |
| logic alert_trig_val_5_qs; |
| logic alert_trig_val_5_wd; |
| logic alert_trig_val_6_qs; |
| logic alert_trig_val_6_wd; |
| logic alert_trig_val_7_qs; |
| logic alert_trig_val_7_wd; |
| logic alert_trig_val_8_qs; |
| logic alert_trig_val_8_wd; |
| logic alert_trig_val_9_qs; |
| logic alert_trig_val_9_wd; |
| logic alert_trig_val_10_qs; |
| logic alert_trig_val_10_wd; |
| logic fatal_alert_en_we; |
| logic fatal_alert_en_val_0_qs; |
| logic fatal_alert_en_val_0_wd; |
| logic fatal_alert_en_val_1_qs; |
| logic fatal_alert_en_val_1_wd; |
| logic fatal_alert_en_val_2_qs; |
| logic fatal_alert_en_val_2_wd; |
| logic fatal_alert_en_val_3_qs; |
| logic fatal_alert_en_val_3_wd; |
| logic fatal_alert_en_val_4_qs; |
| logic fatal_alert_en_val_4_wd; |
| logic fatal_alert_en_val_5_qs; |
| logic fatal_alert_en_val_5_wd; |
| logic fatal_alert_en_val_6_qs; |
| logic fatal_alert_en_val_6_wd; |
| logic fatal_alert_en_val_7_qs; |
| logic fatal_alert_en_val_7_wd; |
| logic fatal_alert_en_val_8_qs; |
| logic fatal_alert_en_val_8_wd; |
| logic fatal_alert_en_val_9_qs; |
| logic fatal_alert_en_val_9_wd; |
| logic fatal_alert_en_val_10_qs; |
| logic fatal_alert_en_val_10_wd; |
| logic recov_alert_we; |
| logic recov_alert_val_0_qs; |
| logic recov_alert_val_0_wd; |
| logic recov_alert_val_1_qs; |
| logic recov_alert_val_1_wd; |
| logic recov_alert_val_2_qs; |
| logic recov_alert_val_2_wd; |
| logic recov_alert_val_3_qs; |
| logic recov_alert_val_3_wd; |
| logic recov_alert_val_4_qs; |
| logic recov_alert_val_4_wd; |
| logic recov_alert_val_5_qs; |
| logic recov_alert_val_5_wd; |
| logic recov_alert_val_6_qs; |
| logic recov_alert_val_6_wd; |
| logic recov_alert_val_7_qs; |
| logic recov_alert_val_7_wd; |
| logic recov_alert_val_8_qs; |
| logic recov_alert_val_8_wd; |
| logic recov_alert_val_9_qs; |
| logic recov_alert_val_9_wd; |
| logic recov_alert_val_10_qs; |
| logic recov_alert_val_10_wd; |
| logic fatal_alert_val_0_qs; |
| logic fatal_alert_val_1_qs; |
| logic fatal_alert_val_2_qs; |
| logic fatal_alert_val_3_qs; |
| logic fatal_alert_val_4_qs; |
| logic fatal_alert_val_5_qs; |
| logic fatal_alert_val_6_qs; |
| logic fatal_alert_val_7_qs; |
| logic fatal_alert_val_8_qs; |
| logic fatal_alert_val_9_qs; |
| logic fatal_alert_val_10_qs; |
| logic fatal_alert_val_11_qs; |
| logic status_ast_init_done_qs; |
| logic [1:0] status_io_pok_qs; |
| |
| // Register instances |
| // R[intr_state]: V(False) |
| // F[io_status_change]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_io_status_change ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_io_status_change_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.io_status_change.de), |
| .d (hw2reg.intr_state.io_status_change.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.io_status_change.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_io_status_change_qs) |
| ); |
| |
| // F[init_status_change]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_intr_state_init_status_change ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_state_we), |
| .wd (intr_state_init_status_change_wd), |
| |
| // from internal hardware |
| .de (hw2reg.intr_state.init_status_change.de), |
| .d (hw2reg.intr_state.init_status_change.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_state.init_status_change.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_state_init_status_change_qs) |
| ); |
| |
| |
| // R[intr_enable]: V(False) |
| // F[io_status_change]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_io_status_change ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_io_status_change_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.io_status_change.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_io_status_change_qs) |
| ); |
| |
| // F[init_status_change]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_intr_enable_init_status_change ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (intr_enable_we), |
| .wd (intr_enable_init_status_change_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.intr_enable.init_status_change.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (intr_enable_init_status_change_qs) |
| ); |
| |
| |
| // R[intr_test]: V(True) |
| logic intr_test_qe; |
| logic [1:0] intr_test_flds_we; |
| assign intr_test_qe = &intr_test_flds_we; |
| // F[io_status_change]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_io_status_change ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_io_status_change_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[0]), |
| .q (reg2hw.intr_test.io_status_change.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.io_status_change.qe = intr_test_qe; |
| |
| // F[init_status_change]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_intr_test_init_status_change ( |
| .re (1'b0), |
| .we (intr_test_we), |
| .wd (intr_test_init_status_change_wd), |
| .d ('0), |
| .qre (), |
| .qe (intr_test_flds_we[1]), |
| .q (reg2hw.intr_test.init_status_change.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.intr_test.init_status_change.qe = intr_test_qe; |
| |
| |
| // R[alert_test]: V(True) |
| logic alert_test_qe; |
| logic [1:0] alert_test_flds_we; |
| assign alert_test_qe = &alert_test_flds_we; |
| // F[recov_alert]: 0:0 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_alert_test_recov_alert ( |
| .re (1'b0), |
| .we (alert_test_we), |
| .wd (alert_test_recov_alert_wd), |
| .d ('0), |
| .qre (), |
| .qe (alert_test_flds_we[0]), |
| .q (reg2hw.alert_test.recov_alert.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.alert_test.recov_alert.qe = alert_test_qe; |
| |
| // F[fatal_alert]: 1:1 |
| prim_subreg_ext #( |
| .DW (1) |
| ) u_alert_test_fatal_alert ( |
| .re (1'b0), |
| .we (alert_test_we), |
| .wd (alert_test_fatal_alert_wd), |
| .d ('0), |
| .qre (), |
| .qe (alert_test_flds_we[1]), |
| .q (reg2hw.alert_test.fatal_alert.q), |
| .ds (), |
| .qs () |
| ); |
| assign reg2hw.alert_test.fatal_alert.qe = alert_test_qe; |
| |
| |
| // R[cfg_regwen]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW0C), |
| .RESVAL (1'h1) |
| ) u_cfg_regwen ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (cfg_regwen_we), |
| .wd (cfg_regwen_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (cfg_regwen_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg alert_trig |
| // R[alert_trig]: V(False) |
| // F[val_0]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_alert_trig_val_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (alert_trig_we), |
| .wd (alert_trig_val_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.alert_trig[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (alert_trig_val_0_qs) |
| ); |
| |
| // F[val_1]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_alert_trig_val_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (alert_trig_we), |
| .wd (alert_trig_val_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.alert_trig[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (alert_trig_val_1_qs) |
| ); |
| |
| // F[val_2]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_alert_trig_val_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (alert_trig_we), |
| .wd (alert_trig_val_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.alert_trig[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (alert_trig_val_2_qs) |
| ); |
| |
| // F[val_3]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_alert_trig_val_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (alert_trig_we), |
| .wd (alert_trig_val_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.alert_trig[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (alert_trig_val_3_qs) |
| ); |
| |
| // F[val_4]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_alert_trig_val_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (alert_trig_we), |
| .wd (alert_trig_val_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.alert_trig[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (alert_trig_val_4_qs) |
| ); |
| |
| // F[val_5]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_alert_trig_val_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (alert_trig_we), |
| .wd (alert_trig_val_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.alert_trig[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (alert_trig_val_5_qs) |
| ); |
| |
| // F[val_6]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_alert_trig_val_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (alert_trig_we), |
| .wd (alert_trig_val_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.alert_trig[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (alert_trig_val_6_qs) |
| ); |
| |
| // F[val_7]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_alert_trig_val_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (alert_trig_we), |
| .wd (alert_trig_val_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.alert_trig[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (alert_trig_val_7_qs) |
| ); |
| |
| // F[val_8]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_alert_trig_val_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (alert_trig_we), |
| .wd (alert_trig_val_8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.alert_trig[8].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (alert_trig_val_8_qs) |
| ); |
| |
| // F[val_9]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_alert_trig_val_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (alert_trig_we), |
| .wd (alert_trig_val_9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.alert_trig[9].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (alert_trig_val_9_qs) |
| ); |
| |
| // F[val_10]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_alert_trig_val_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (alert_trig_we), |
| .wd (alert_trig_val_10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.alert_trig[10].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (alert_trig_val_10_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg fatal_alert_en |
| // R[fatal_alert_en]: V(False) |
| // Create REGWEN-gated WE signal |
| logic fatal_alert_en_gated_we; |
| assign fatal_alert_en_gated_we = fatal_alert_en_we & cfg_regwen_qs; |
| // F[val_0]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_en_val_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fatal_alert_en_gated_we), |
| .wd (fatal_alert_en_val_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert_en[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_en_val_0_qs) |
| ); |
| |
| // F[val_1]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_en_val_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fatal_alert_en_gated_we), |
| .wd (fatal_alert_en_val_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert_en[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_en_val_1_qs) |
| ); |
| |
| // F[val_2]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_en_val_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fatal_alert_en_gated_we), |
| .wd (fatal_alert_en_val_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert_en[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_en_val_2_qs) |
| ); |
| |
| // F[val_3]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_en_val_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fatal_alert_en_gated_we), |
| .wd (fatal_alert_en_val_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert_en[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_en_val_3_qs) |
| ); |
| |
| // F[val_4]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_en_val_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fatal_alert_en_gated_we), |
| .wd (fatal_alert_en_val_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert_en[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_en_val_4_qs) |
| ); |
| |
| // F[val_5]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_en_val_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fatal_alert_en_gated_we), |
| .wd (fatal_alert_en_val_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert_en[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_en_val_5_qs) |
| ); |
| |
| // F[val_6]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_en_val_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fatal_alert_en_gated_we), |
| .wd (fatal_alert_en_val_6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert_en[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_en_val_6_qs) |
| ); |
| |
| // F[val_7]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_en_val_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fatal_alert_en_gated_we), |
| .wd (fatal_alert_en_val_7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert_en[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_en_val_7_qs) |
| ); |
| |
| // F[val_8]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_en_val_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fatal_alert_en_gated_we), |
| .wd (fatal_alert_en_val_8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert_en[8].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_en_val_8_qs) |
| ); |
| |
| // F[val_9]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_en_val_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fatal_alert_en_gated_we), |
| .wd (fatal_alert_en_val_9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert_en[9].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_en_val_9_qs) |
| ); |
| |
| // F[val_10]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_en_val_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (fatal_alert_en_gated_we), |
| .wd (fatal_alert_en_val_10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert_en[10].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_en_val_10_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg recov_alert |
| // R[recov_alert]: V(False) |
| // F[val_0]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_recov_alert_val_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (recov_alert_we), |
| .wd (recov_alert_val_0_wd), |
| |
| // from internal hardware |
| .de (hw2reg.recov_alert[0].de), |
| .d (hw2reg.recov_alert[0].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.recov_alert[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (recov_alert_val_0_qs) |
| ); |
| |
| // F[val_1]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_recov_alert_val_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (recov_alert_we), |
| .wd (recov_alert_val_1_wd), |
| |
| // from internal hardware |
| .de (hw2reg.recov_alert[1].de), |
| .d (hw2reg.recov_alert[1].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.recov_alert[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (recov_alert_val_1_qs) |
| ); |
| |
| // F[val_2]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_recov_alert_val_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (recov_alert_we), |
| .wd (recov_alert_val_2_wd), |
| |
| // from internal hardware |
| .de (hw2reg.recov_alert[2].de), |
| .d (hw2reg.recov_alert[2].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.recov_alert[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (recov_alert_val_2_qs) |
| ); |
| |
| // F[val_3]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_recov_alert_val_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (recov_alert_we), |
| .wd (recov_alert_val_3_wd), |
| |
| // from internal hardware |
| .de (hw2reg.recov_alert[3].de), |
| .d (hw2reg.recov_alert[3].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.recov_alert[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (recov_alert_val_3_qs) |
| ); |
| |
| // F[val_4]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_recov_alert_val_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (recov_alert_we), |
| .wd (recov_alert_val_4_wd), |
| |
| // from internal hardware |
| .de (hw2reg.recov_alert[4].de), |
| .d (hw2reg.recov_alert[4].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.recov_alert[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (recov_alert_val_4_qs) |
| ); |
| |
| // F[val_5]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_recov_alert_val_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (recov_alert_we), |
| .wd (recov_alert_val_5_wd), |
| |
| // from internal hardware |
| .de (hw2reg.recov_alert[5].de), |
| .d (hw2reg.recov_alert[5].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.recov_alert[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (recov_alert_val_5_qs) |
| ); |
| |
| // F[val_6]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_recov_alert_val_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (recov_alert_we), |
| .wd (recov_alert_val_6_wd), |
| |
| // from internal hardware |
| .de (hw2reg.recov_alert[6].de), |
| .d (hw2reg.recov_alert[6].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.recov_alert[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (recov_alert_val_6_qs) |
| ); |
| |
| // F[val_7]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_recov_alert_val_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (recov_alert_we), |
| .wd (recov_alert_val_7_wd), |
| |
| // from internal hardware |
| .de (hw2reg.recov_alert[7].de), |
| .d (hw2reg.recov_alert[7].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.recov_alert[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (recov_alert_val_7_qs) |
| ); |
| |
| // F[val_8]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_recov_alert_val_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (recov_alert_we), |
| .wd (recov_alert_val_8_wd), |
| |
| // from internal hardware |
| .de (hw2reg.recov_alert[8].de), |
| .d (hw2reg.recov_alert[8].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.recov_alert[8].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (recov_alert_val_8_qs) |
| ); |
| |
| // F[val_9]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_recov_alert_val_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (recov_alert_we), |
| .wd (recov_alert_val_9_wd), |
| |
| // from internal hardware |
| .de (hw2reg.recov_alert[9].de), |
| .d (hw2reg.recov_alert[9].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.recov_alert[9].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (recov_alert_val_9_qs) |
| ); |
| |
| // F[val_10]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessW1C), |
| .RESVAL (1'h0) |
| ) u_recov_alert_val_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (recov_alert_we), |
| .wd (recov_alert_val_10_wd), |
| |
| // from internal hardware |
| .de (hw2reg.recov_alert[10].de), |
| .d (hw2reg.recov_alert[10].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.recov_alert[10].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (recov_alert_val_10_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg fatal_alert |
| // R[fatal_alert]: V(False) |
| // F[val_0]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_val_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.fatal_alert[0].de), |
| .d (hw2reg.fatal_alert[0].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_val_0_qs) |
| ); |
| |
| // F[val_1]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_val_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.fatal_alert[1].de), |
| .d (hw2reg.fatal_alert[1].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_val_1_qs) |
| ); |
| |
| // F[val_2]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_val_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.fatal_alert[2].de), |
| .d (hw2reg.fatal_alert[2].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_val_2_qs) |
| ); |
| |
| // F[val_3]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_val_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.fatal_alert[3].de), |
| .d (hw2reg.fatal_alert[3].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_val_3_qs) |
| ); |
| |
| // F[val_4]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_val_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.fatal_alert[4].de), |
| .d (hw2reg.fatal_alert[4].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_val_4_qs) |
| ); |
| |
| // F[val_5]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_val_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.fatal_alert[5].de), |
| .d (hw2reg.fatal_alert[5].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_val_5_qs) |
| ); |
| |
| // F[val_6]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_val_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.fatal_alert[6].de), |
| .d (hw2reg.fatal_alert[6].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_val_6_qs) |
| ); |
| |
| // F[val_7]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_val_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.fatal_alert[7].de), |
| .d (hw2reg.fatal_alert[7].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_val_7_qs) |
| ); |
| |
| // F[val_8]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_val_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.fatal_alert[8].de), |
| .d (hw2reg.fatal_alert[8].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert[8].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_val_8_qs) |
| ); |
| |
| // F[val_9]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_val_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.fatal_alert[9].de), |
| .d (hw2reg.fatal_alert[9].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert[9].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_val_9_qs) |
| ); |
| |
| // F[val_10]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_val_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.fatal_alert[10].de), |
| .d (hw2reg.fatal_alert[10].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert[10].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_val_10_qs) |
| ); |
| |
| // F[val_11]: 11:11 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_fatal_alert_val_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.fatal_alert[11].de), |
| .d (hw2reg.fatal_alert[11].d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.fatal_alert[11].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (fatal_alert_val_11_qs) |
| ); |
| |
| |
| // R[status]: V(False) |
| // F[ast_init_done]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (1'h0) |
| ) u_status_ast_init_done ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.status.ast_init_done.de), |
| .d (hw2reg.status.ast_init_done.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (status_ast_init_done_qs) |
| ); |
| |
| // F[io_pok]: 2:1 |
| prim_subreg #( |
| .DW (2), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (2'h0) |
| ) u_status_io_pok ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.status.io_pok.de), |
| .d (hw2reg.status.io_pok.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (status_io_pok_qs) |
| ); |
| |
| |
| |
| logic [9:0] addr_hit; |
| always_comb begin |
| addr_hit = '0; |
| addr_hit[0] = (reg_addr == SENSOR_CTRL_INTR_STATE_OFFSET); |
| addr_hit[1] = (reg_addr == SENSOR_CTRL_INTR_ENABLE_OFFSET); |
| addr_hit[2] = (reg_addr == SENSOR_CTRL_INTR_TEST_OFFSET); |
| addr_hit[3] = (reg_addr == SENSOR_CTRL_ALERT_TEST_OFFSET); |
| addr_hit[4] = (reg_addr == SENSOR_CTRL_CFG_REGWEN_OFFSET); |
| addr_hit[5] = (reg_addr == SENSOR_CTRL_ALERT_TRIG_OFFSET); |
| addr_hit[6] = (reg_addr == SENSOR_CTRL_FATAL_ALERT_EN_OFFSET); |
| addr_hit[7] = (reg_addr == SENSOR_CTRL_RECOV_ALERT_OFFSET); |
| addr_hit[8] = (reg_addr == SENSOR_CTRL_FATAL_ALERT_OFFSET); |
| addr_hit[9] = (reg_addr == SENSOR_CTRL_STATUS_OFFSET); |
| end |
| |
| assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; |
| |
| // Check sub-word write is permitted |
| always_comb begin |
| wr_err = (reg_we & |
| ((addr_hit[0] & (|(SENSOR_CTRL_PERMIT[0] & ~reg_be))) | |
| (addr_hit[1] & (|(SENSOR_CTRL_PERMIT[1] & ~reg_be))) | |
| (addr_hit[2] & (|(SENSOR_CTRL_PERMIT[2] & ~reg_be))) | |
| (addr_hit[3] & (|(SENSOR_CTRL_PERMIT[3] & ~reg_be))) | |
| (addr_hit[4] & (|(SENSOR_CTRL_PERMIT[4] & ~reg_be))) | |
| (addr_hit[5] & (|(SENSOR_CTRL_PERMIT[5] & ~reg_be))) | |
| (addr_hit[6] & (|(SENSOR_CTRL_PERMIT[6] & ~reg_be))) | |
| (addr_hit[7] & (|(SENSOR_CTRL_PERMIT[7] & ~reg_be))) | |
| (addr_hit[8] & (|(SENSOR_CTRL_PERMIT[8] & ~reg_be))) | |
| (addr_hit[9] & (|(SENSOR_CTRL_PERMIT[9] & ~reg_be))))); |
| end |
| |
| // Generate write-enables |
| assign intr_state_we = addr_hit[0] & reg_we & !reg_error; |
| |
| assign intr_state_io_status_change_wd = reg_wdata[0]; |
| |
| assign intr_state_init_status_change_wd = reg_wdata[1]; |
| assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; |
| |
| assign intr_enable_io_status_change_wd = reg_wdata[0]; |
| |
| assign intr_enable_init_status_change_wd = reg_wdata[1]; |
| assign intr_test_we = addr_hit[2] & reg_we & !reg_error; |
| |
| assign intr_test_io_status_change_wd = reg_wdata[0]; |
| |
| assign intr_test_init_status_change_wd = reg_wdata[1]; |
| assign alert_test_we = addr_hit[3] & reg_we & !reg_error; |
| |
| assign alert_test_recov_alert_wd = reg_wdata[0]; |
| |
| assign alert_test_fatal_alert_wd = reg_wdata[1]; |
| assign cfg_regwen_we = addr_hit[4] & reg_we & !reg_error; |
| |
| assign cfg_regwen_wd = reg_wdata[0]; |
| assign alert_trig_we = addr_hit[5] & reg_we & !reg_error; |
| |
| assign alert_trig_val_0_wd = reg_wdata[0]; |
| |
| assign alert_trig_val_1_wd = reg_wdata[1]; |
| |
| assign alert_trig_val_2_wd = reg_wdata[2]; |
| |
| assign alert_trig_val_3_wd = reg_wdata[3]; |
| |
| assign alert_trig_val_4_wd = reg_wdata[4]; |
| |
| assign alert_trig_val_5_wd = reg_wdata[5]; |
| |
| assign alert_trig_val_6_wd = reg_wdata[6]; |
| |
| assign alert_trig_val_7_wd = reg_wdata[7]; |
| |
| assign alert_trig_val_8_wd = reg_wdata[8]; |
| |
| assign alert_trig_val_9_wd = reg_wdata[9]; |
| |
| assign alert_trig_val_10_wd = reg_wdata[10]; |
| assign fatal_alert_en_we = addr_hit[6] & reg_we & !reg_error; |
| |
| assign fatal_alert_en_val_0_wd = reg_wdata[0]; |
| |
| assign fatal_alert_en_val_1_wd = reg_wdata[1]; |
| |
| assign fatal_alert_en_val_2_wd = reg_wdata[2]; |
| |
| assign fatal_alert_en_val_3_wd = reg_wdata[3]; |
| |
| assign fatal_alert_en_val_4_wd = reg_wdata[4]; |
| |
| assign fatal_alert_en_val_5_wd = reg_wdata[5]; |
| |
| assign fatal_alert_en_val_6_wd = reg_wdata[6]; |
| |
| assign fatal_alert_en_val_7_wd = reg_wdata[7]; |
| |
| assign fatal_alert_en_val_8_wd = reg_wdata[8]; |
| |
| assign fatal_alert_en_val_9_wd = reg_wdata[9]; |
| |
| assign fatal_alert_en_val_10_wd = reg_wdata[10]; |
| assign recov_alert_we = addr_hit[7] & reg_we & !reg_error; |
| |
| assign recov_alert_val_0_wd = reg_wdata[0]; |
| |
| assign recov_alert_val_1_wd = reg_wdata[1]; |
| |
| assign recov_alert_val_2_wd = reg_wdata[2]; |
| |
| assign recov_alert_val_3_wd = reg_wdata[3]; |
| |
| assign recov_alert_val_4_wd = reg_wdata[4]; |
| |
| assign recov_alert_val_5_wd = reg_wdata[5]; |
| |
| assign recov_alert_val_6_wd = reg_wdata[6]; |
| |
| assign recov_alert_val_7_wd = reg_wdata[7]; |
| |
| assign recov_alert_val_8_wd = reg_wdata[8]; |
| |
| assign recov_alert_val_9_wd = reg_wdata[9]; |
| |
| assign recov_alert_val_10_wd = reg_wdata[10]; |
| |
| // Assign write-enables to checker logic vector. |
| always_comb begin |
| reg_we_check = '0; |
| reg_we_check[0] = intr_state_we; |
| reg_we_check[1] = intr_enable_we; |
| reg_we_check[2] = intr_test_we; |
| reg_we_check[3] = alert_test_we; |
| reg_we_check[4] = cfg_regwen_we; |
| reg_we_check[5] = alert_trig_we; |
| reg_we_check[6] = fatal_alert_en_gated_we; |
| reg_we_check[7] = recov_alert_we; |
| reg_we_check[8] = 1'b0; |
| reg_we_check[9] = 1'b0; |
| end |
| |
| // Read data return |
| always_comb begin |
| reg_rdata_next = '0; |
| unique case (1'b1) |
| addr_hit[0]: begin |
| reg_rdata_next[0] = intr_state_io_status_change_qs; |
| reg_rdata_next[1] = intr_state_init_status_change_qs; |
| end |
| |
| addr_hit[1]: begin |
| reg_rdata_next[0] = intr_enable_io_status_change_qs; |
| reg_rdata_next[1] = intr_enable_init_status_change_qs; |
| end |
| |
| addr_hit[2]: begin |
| reg_rdata_next[0] = '0; |
| reg_rdata_next[1] = '0; |
| end |
| |
| addr_hit[3]: begin |
| reg_rdata_next[0] = '0; |
| reg_rdata_next[1] = '0; |
| end |
| |
| addr_hit[4]: begin |
| reg_rdata_next[0] = cfg_regwen_qs; |
| end |
| |
| addr_hit[5]: begin |
| reg_rdata_next[0] = alert_trig_val_0_qs; |
| reg_rdata_next[1] = alert_trig_val_1_qs; |
| reg_rdata_next[2] = alert_trig_val_2_qs; |
| reg_rdata_next[3] = alert_trig_val_3_qs; |
| reg_rdata_next[4] = alert_trig_val_4_qs; |
| reg_rdata_next[5] = alert_trig_val_5_qs; |
| reg_rdata_next[6] = alert_trig_val_6_qs; |
| reg_rdata_next[7] = alert_trig_val_7_qs; |
| reg_rdata_next[8] = alert_trig_val_8_qs; |
| reg_rdata_next[9] = alert_trig_val_9_qs; |
| reg_rdata_next[10] = alert_trig_val_10_qs; |
| end |
| |
| addr_hit[6]: begin |
| reg_rdata_next[0] = fatal_alert_en_val_0_qs; |
| reg_rdata_next[1] = fatal_alert_en_val_1_qs; |
| reg_rdata_next[2] = fatal_alert_en_val_2_qs; |
| reg_rdata_next[3] = fatal_alert_en_val_3_qs; |
| reg_rdata_next[4] = fatal_alert_en_val_4_qs; |
| reg_rdata_next[5] = fatal_alert_en_val_5_qs; |
| reg_rdata_next[6] = fatal_alert_en_val_6_qs; |
| reg_rdata_next[7] = fatal_alert_en_val_7_qs; |
| reg_rdata_next[8] = fatal_alert_en_val_8_qs; |
| reg_rdata_next[9] = fatal_alert_en_val_9_qs; |
| reg_rdata_next[10] = fatal_alert_en_val_10_qs; |
| end |
| |
| addr_hit[7]: begin |
| reg_rdata_next[0] = recov_alert_val_0_qs; |
| reg_rdata_next[1] = recov_alert_val_1_qs; |
| reg_rdata_next[2] = recov_alert_val_2_qs; |
| reg_rdata_next[3] = recov_alert_val_3_qs; |
| reg_rdata_next[4] = recov_alert_val_4_qs; |
| reg_rdata_next[5] = recov_alert_val_5_qs; |
| reg_rdata_next[6] = recov_alert_val_6_qs; |
| reg_rdata_next[7] = recov_alert_val_7_qs; |
| reg_rdata_next[8] = recov_alert_val_8_qs; |
| reg_rdata_next[9] = recov_alert_val_9_qs; |
| reg_rdata_next[10] = recov_alert_val_10_qs; |
| end |
| |
| addr_hit[8]: begin |
| reg_rdata_next[0] = fatal_alert_val_0_qs; |
| reg_rdata_next[1] = fatal_alert_val_1_qs; |
| reg_rdata_next[2] = fatal_alert_val_2_qs; |
| reg_rdata_next[3] = fatal_alert_val_3_qs; |
| reg_rdata_next[4] = fatal_alert_val_4_qs; |
| reg_rdata_next[5] = fatal_alert_val_5_qs; |
| reg_rdata_next[6] = fatal_alert_val_6_qs; |
| reg_rdata_next[7] = fatal_alert_val_7_qs; |
| reg_rdata_next[8] = fatal_alert_val_8_qs; |
| reg_rdata_next[9] = fatal_alert_val_9_qs; |
| reg_rdata_next[10] = fatal_alert_val_10_qs; |
| reg_rdata_next[11] = fatal_alert_val_11_qs; |
| end |
| |
| addr_hit[9]: begin |
| reg_rdata_next[0] = status_ast_init_done_qs; |
| reg_rdata_next[2:1] = status_io_pok_qs; |
| end |
| |
| default: begin |
| reg_rdata_next = '1; |
| end |
| endcase |
| end |
| |
| // shadow busy |
| logic shadow_busy; |
| assign shadow_busy = 1'b0; |
| |
| // register busy |
| assign reg_busy = shadow_busy; |
| |
| // Unused signal tieoff |
| |
| // wdata / byte enable are not always fully used |
| // add a blanket unused statement to handle lint waivers |
| logic unused_wdata; |
| logic unused_be; |
| assign unused_wdata = ^reg_wdata; |
| assign unused_be = ^reg_be; |
| |
| // Assertions for Register Interface |
| `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) |
| `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) |
| |
| `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) |
| |
| `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) |
| |
| // this is formulated as an assumption such that the FPV testbenches do disprove this |
| // property by mistake |
| //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) |
| |
| endmodule |
