hw/ip/usbdev/dv/usbdev_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: usbdev

  // Top level dut name (sv module).
  dut: usbdev

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:usbdev_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/usbdev/data/usbdev_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/usbdev/data/usbdev.hjson"

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: ["usbdev_bind", "sec_cm_prim_onehot_check_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Default UVM test and seq class name.
  uvm_test: usbdev_base_test
  uvm_test_seq: usbdev_base_vseq

  // TODO: temporary fix for CSR tests - USB link reset interrupt is sticky - clearing it
  // has no effect. Update "csr_test_mode" to add +do_clear_all_interrupts=0 switch to
  // prevent the intr checks from being run.
  run_modes: [
    {
      name: csr_tests_mode
      run_opts: ["+do_clear_all_interrupts=0"]
    }
  ]

  // List of test specifications.
  tests: [
    {
      name: usbdev_smoke
      uvm_test_seq: usbdev_smoke_vseq
    }
  ]

  // List of regressions.
  regressions: [
    // {
    //   name: smoke
    //   tests: ["usbdev_smoke"]
    // }
  ]
}