hw/ip/spi_device/dv/spi_device_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: spi_device

  // Top level dut name (sv module).
  dut: spi_device

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:spi_device_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/spi_device/data/spi_device_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/spi_device/data/spi_device.hjson"

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/stress_all_test.hjson"
                // TODO, enable stress_all_with_rand_reset later
                // "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"
                ]

  // Add additional tops for simulation.
  sim_tops: ["spi_device_bind", "sec_cm_prim_onehot_check_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Default UVM test and seq class name.
  uvm_test: spi_device_base_test
  uvm_test_seq: spi_device_base_vseq

  // Add UART specific exclusion files.
  vcs_cov_excl_files: ["{proj_root}/hw/ip/spi_device/dv/cov/spi_device_cov_excl.el"]

  // List of test specifications.
  tests: [
    {
      name: spi_device_smoke
      uvm_test_seq: spi_device_smoke_vseq
    }

    {
      name: spi_device_txrx
      uvm_test_seq: spi_device_txrx_vseq
    }

    {
      name: spi_device_fifo_full
      uvm_test_seq: spi_device_fifo_full_vseq
    }

    {
      name: spi_device_fifo_underflow_overflow
      uvm_test_seq: spi_device_fifo_underflow_overflow_vseq
    }

    {
      name: spi_device_extreme_fifo_size
      uvm_test_seq: spi_device_extreme_fifo_size_vseq
      run_timeout_mins: 90
    }

    {
      name: spi_device_dummy_item_extra_dly
      uvm_test_seq: spi_device_dummy_item_extra_dly_vseq
    }

    {
      name: spi_device_intr
      uvm_test_seq: spi_device_intr_vseq
    }

    {
      name: spi_device_perf
      uvm_test_seq: spi_device_perf_vseq
    }

    {
      name: spi_device_csb_read
      uvm_test_seq: spi_device_csb_read_vseq
    }

    {
      name: spi_device_byte_transfer
      uvm_test_seq: spi_device_byte_transfer_vseq
    }

    {
      name: spi_device_rx_timeout
      uvm_test_seq: spi_device_rx_timeout_vseq
    }
    // This test reuses the same structure as tl_intg_err.
    {
      name: "spi_device_mem_parity"
      uvm_test_seq: "spi_device_mem_parity_vseq"
      run_opts: ["+en_scb=0", "+en_scb_tl_err_chk=0"]
      reseed: 20
    }

    {
      name: "spi_device_ram_cfg"
      uvm_test_seq: "spi_device_ram_cfg_vseq"
      reseed: 20
    }

    {
      name: spi_device_tpm_read_hw_reg
      uvm_test_seq: spi_device_tpm_read_hw_reg_vseq
    }

    {
      name: spi_device_tpm_all
      uvm_test_seq: spi_device_tpm_all_vseq
    }

    {
      name: spi_device_bit_transfer
      uvm_test_seq: spi_device_bit_transfer_vseq
    }

    {
      name: spi_device_tx_async_fifo_reset
      uvm_test_seq: spi_device_tx_async_fifo_reset_vseq
    }

    {
      name: spi_device_rx_async_fifo_reset
      uvm_test_seq: spi_device_rx_async_fifo_reset_vseq
    }

    {
      name: spi_device_abort
      uvm_test_seq: spi_device_abort_vseq
    }

    {
      name: spi_device_tpm_sts_read
      uvm_test_seq: spi_device_tpm_sts_read_vseq
    }

    {
      name: spi_device_tpm_rw
      uvm_test_seq: spi_device_tpm_rw_vseq
    }

    {
      name: spi_device_pass_cmd_filtering
      uvm_test_seq: spi_device_pass_cmd_filtering_vseq
    }

    {
      name: spi_device_pass_addr_payload_swap
      uvm_test_seq: spi_device_pass_addr_payload_swap_vseq
    }

    {
      name: spi_device_intercept
      uvm_test_seq: spi_device_intercept_vseq
    }

    {
      name: spi_device_mailbox
      uvm_test_seq: spi_device_mailbox_vseq
    }

    {
      name: spi_device_upload
      uvm_test_seq: spi_device_upload_vseq
    }

    {
      name: spi_device_cfg_cmd
      uvm_test_seq: spi_device_cfg_cmd_vseq
    }

    {
      name: spi_device_flash_mode
      uvm_test_seq: spi_device_flash_mode_vseq
    }

    {
      name: spi_device_read_buffer_direct
      uvm_test_seq: spi_device_read_buffer_direct_vseq
      // it's a direct test, and checking is done in seq
      run_opts: ["+en_scb=0"]
    }

    {
      name: spi_device_flash_all
      uvm_test_seq: spi_device_flash_all_vseq
    }

    {
      name: spi_device_flash_and_tpm
      uvm_test_seq: spi_device_flash_and_tpm_vseq
    }

    {
      name: spi_device_flash_and_tpm_min_idle
      uvm_test_seq: spi_device_flash_and_tpm_min_idle_vseq
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["spi_device_smoke"]
    }
  ]
}