blob: e37640fad5e2b48d485b969884634ac807ae20c4 [file] [log] [blame]
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//==================================================
// This file contains the Excluded objects
// Generated By User: root
// Format Version: 2
// Date: Mon Oct 10 17:24:43 2022
// ExclMode: default
//==================================================
CHECKSUM: "1723488990 3787458315"
INSTANCE: tb.dut.top_earlgrey.u_otbn
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.ram_cfg.cfg_en "logic ram_cfg_i.ram_cfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.rf_cfg.cfg "logic ram_cfg_i.rf_cfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.rf_cfg.cfg_en "logic ram_cfg_i.rf_cfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.ram_cfg.cfg "logic ram_cfg_i.ram_cfg.cfg[3:0]"
CHECKSUM: "2093258215 2721317761"
INSTANCE: tb.dut.u_ast
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle dpram_rmf_o.marg_b "logic dpram_rmf_o.marg_b[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle dpram_rmf_o.marg_en_a "logic dpram_rmf_o.marg_en_a"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle dpram_rmf_o.marg_en_b "logic dpram_rmf_o.marg_en_b"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle dpram_rml_o.marg_a "logic dpram_rml_o.marg_a[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle dpram_rml_o.marg_b "logic dpram_rml_o.marg_b[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle dpram_rml_o.marg_en_a "logic dpram_rml_o.marg_en_a"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle dpram_rml_o.marg_en_b "logic dpram_rml_o.marg_en_b"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle spram_rm_o.marg "logic spram_rm_o.marg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle spram_rm_o.marg_en "logic spram_rm_o.marg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle dpram_rmf_o.marg_a "logic dpram_rmf_o.marg_a[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle sprgf_rm_o.marg "logic sprgf_rm_o.marg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle sprom_rm_o.marg_en "logic sprom_rm_o.marg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle sprom_rm_o.marg "logic sprom_rm_o.marg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle sprgf_rm_o.marg_en "logic sprgf_rm_o.marg_en"
CHECKSUM: "1073499243 944375913"
INSTANCE: tb.dut.top_earlgrey.u_spi_device
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.a_ram_fcfg.cfg_en "logic ram_cfg_i.a_ram_fcfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.a_ram_lcfg.cfg "logic ram_cfg_i.a_ram_lcfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.a_ram_lcfg.cfg_en "logic ram_cfg_i.a_ram_lcfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.b_ram_fcfg.cfg "logic ram_cfg_i.b_ram_fcfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.b_ram_fcfg.cfg_en "logic ram_cfg_i.b_ram_fcfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.b_ram_lcfg.cfg "logic ram_cfg_i.b_ram_lcfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.b_ram_lcfg.cfg_en "logic ram_cfg_i.b_ram_lcfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.a_ram_fcfg.cfg "logic ram_cfg_i.a_ram_fcfg.cfg[3:0]"
CHECKSUM: "2901544182 2216765521"
INSTANCE: tb.dut.top_earlgrey.u_rv_core_ibex.u_core
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.ram_cfg.cfg_en "logic ram_cfg_i.ram_cfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.rf_cfg.cfg "logic ram_cfg_i.rf_cfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.rf_cfg.cfg_en "logic ram_cfg_i.rf_cfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.ram_cfg.cfg "logic ram_cfg_i.ram_cfg.cfg[3:0]"
CHECKSUM: "3284529020 1014860158"
INSTANCE: tb.dut.top_earlgrey
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_1p_cfg_i.ram_cfg.cfg_en "logic ram_1p_cfg_i.ram_cfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_1p_cfg_i.rf_cfg.cfg "logic ram_1p_cfg_i.rf_cfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_1p_cfg_i.rf_cfg.cfg_en "logic ram_1p_cfg_i.rf_cfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_2p_cfg_i.a_ram_fcfg.cfg "logic ram_2p_cfg_i.a_ram_fcfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_2p_cfg_i.a_ram_fcfg.cfg_en "logic ram_2p_cfg_i.a_ram_fcfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_2p_cfg_i.a_ram_lcfg.cfg "logic ram_2p_cfg_i.a_ram_lcfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_2p_cfg_i.a_ram_lcfg.cfg_en "logic ram_2p_cfg_i.a_ram_lcfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_2p_cfg_i.b_ram_fcfg.cfg "logic ram_2p_cfg_i.b_ram_fcfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_2p_cfg_i.b_ram_fcfg.cfg_en "logic ram_2p_cfg_i.b_ram_fcfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_2p_cfg_i.b_ram_lcfg.cfg "logic ram_2p_cfg_i.b_ram_lcfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_2p_cfg_i.b_ram_lcfg.cfg_en "logic ram_2p_cfg_i.b_ram_lcfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle rom_cfg_i.cfg "logic rom_cfg_i.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle rom_cfg_i.cfg_en "logic rom_cfg_i.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_1p_cfg_i.ram_cfg.cfg "logic ram_1p_cfg_i.ram_cfg.cfg[3:0]"
CHECKSUM: "2518565141 1739668335"
INSTANCE: tb.dut.top_earlgrey.u_sram_ctrl_ret_aon
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle cfg_i.ram_cfg.cfg_en "logic cfg_i.ram_cfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle cfg_i.rf_cfg.cfg "logic cfg_i.rf_cfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle cfg_i.rf_cfg.cfg_en "logic cfg_i.rf_cfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle cfg_i.ram_cfg.cfg "logic cfg_i.ram_cfg.cfg[3:0]"
CHECKSUM: "2518565141 1739668335"
INSTANCE: tb.dut.top_earlgrey.u_sram_ctrl_main
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle cfg_i.ram_cfg.cfg_en "logic cfg_i.ram_cfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle cfg_i.rf_cfg.cfg "logic cfg_i.rf_cfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle cfg_i.rf_cfg.cfg_en "logic cfg_i.rf_cfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle cfg_i.ram_cfg.cfg "logic cfg_i.ram_cfg.cfg[3:0]"
CHECKSUM: "2504344714 679381807"
INSTANCE: tb.dut.top_earlgrey.u_usbdev
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.a_ram_fcfg.cfg_en "logic ram_cfg_i.a_ram_fcfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.a_ram_lcfg.cfg "logic ram_cfg_i.a_ram_lcfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.a_ram_lcfg.cfg_en "logic ram_cfg_i.a_ram_lcfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.b_ram_fcfg.cfg "logic ram_cfg_i.b_ram_fcfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.b_ram_fcfg.cfg_en "logic ram_cfg_i.b_ram_fcfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.b_ram_lcfg.cfg "logic ram_cfg_i.b_ram_lcfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.b_ram_lcfg.cfg_en "logic ram_cfg_i.b_ram_lcfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.a_ram_fcfg.cfg "logic ram_cfg_i.a_ram_fcfg.cfg[3:0]"
CHECKSUM: "2984655879 4250263796"
INSTANCE: tb.dut.top_earlgrey.u_rv_core_ibex
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.ram_cfg.cfg_en "logic ram_cfg_i.ram_cfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.rf_cfg.cfg "logic ram_cfg_i.rf_cfg.cfg[3:0]"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.rf_cfg.cfg_en "logic ram_cfg_i.rf_cfg.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle ram_cfg_i.ram_cfg.cfg "logic ram_cfg_i.ram_cfg.cfg[3:0]"
CHECKSUM: "180068024 3922028773"
INSTANCE: tb.dut.top_earlgrey.u_rom_ctrl
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle rom_cfg_i.cfg_en "logic rom_cfg_i.cfg_en"
ANNOTATION: "[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv"
Toggle rom_cfg_i.cfg "logic rom_cfg_i.cfg[3:0]"