tree 17f8ba9a9e81f70b90b85cecb3871ad0b904f8f3
parent ce8e393d4b2d9b9e789f6e1333a9f3fd530bdba2
author Timothy Chen <timothytim@google.com> 1619054078 -0700
committer tjaychen <timothytim@google.com> 1619062419 -0700

[top] Fixes for optimized modules

- The pins used for creating ast clocks were sometimes being removed
  during synthesis optimization.  This caused a whole set of logic to
  not have a clock, even though the initial constraint definition was
  successful.

- Add buffers to anchor where the constraints would go and ensure logic is
  not removed.  Note this is only needed for open source synthesis since
  AST is not real

Signed-off-by: Timothy Chen <timothytim@google.com>