)]}'
{
  "commit": "29ad4e80338f45aa6158a8eb7e9277016819d69a",
  "tree": "08658720b3a46aab8f73357d860b388199a2c870",
  "parents": [
    "7900b549df3a408897ead54999206c56fcee8e18"
  ],
  "author": {
    "name": "Weicai Yang",
    "email": "weicai@google.com",
    "time": "Thu Mar 05 16:02:15 2020 -0800"
  },
  "committer": {
    "name": "weicaiyang",
    "email": "49293026+weicaiyang@users.noreply.github.com",
    "time": "Thu Mar 05 17:27:59 2020 -0800"
  },
  "message": "[spi_device/dv] Remove setting spi clk on in csr test\n\nreset value is added in design reg #1669, no need to set spi clock always\non to avoid reading unknown reg value\nSigned-off-by: Weicai Yang \u003cweicai@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "87733b9422328032a13b0312d76006c8d3a2f5bf",
      "old_mode": 33188,
      "old_path": "hw/ip/spi_device/dv/env/seq_lib/spi_device_common_vseq.sv",
      "new_id": "d90b7ccbbb2b04bfee3d07e2c908b5c768f3b871",
      "new_mode": 33188,
      "new_path": "hw/ip/spi_device/dv/env/seq_lib/spi_device_common_vseq.sv"
    },
    {
      "type": "modify",
      "old_id": "93821ef3e5453dd28fcc6b489f0583dd37225715",
      "old_mode": 33188,
      "old_path": "hw/top_earlgrey/dv/env/seq_lib/chip_common_vseq.sv",
      "new_id": "9e0fcbea0cfae6c2789aa6c7f4b62452cd0a6741",
      "new_mode": 33188,
      "new_path": "hw/top_earlgrey/dv/env/seq_lib/chip_common_vseq.sv"
    }
  ]
}