tree f24106e2d7ae68f17f247c52ac7c4d91337b9774
parent 1e4989944a3d9657aca16a5a968dc2b7f32d0be4
author Rupert Swarbrick <rswarbrick@lowrisc.org> 1610353533 +0000
committer Rupert Swarbrick <rswarbrick@gmail.com> 1610365419 +0000

[prim] Teach verilator to recognise a clock gate

This avoids an UNOPTFLAT warning, and should speed up simulation a
bit. Quoting from the Verilator manual:

> The clock_enable attribute will cause the clock gate to be ignored
> in the scheduling algorithm, sometimes required for correct clock
> behavior, and always improving performance. It's also a good idea to
> enable the IMPERFECTSCH warning, to ensure all clock enables are
> properly recognized.

Adding the IMPERFECTSCH warning throws up LOTS of cases, unrelated to
this patch, so I'm not convinced that's worth doing at the moment (it
probably shows there are some low-hanging simulation performance
improvements though).

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>