)]}'
{
  "commit": "24c0f12f1fa83376297e62146a272d0e73eca6f1",
  "tree": "fa750dcd924a8be285310ee2b8d7c2cc7176b599",
  "parents": [
    "7728634f7d88bd0b37dde9b1819490bd9764f010"
  ],
  "author": {
    "name": "Timothy Chen",
    "email": "timothytim@google.com",
    "time": "Fri Mar 04 10:45:24 2022 -0800"
  },
  "committer": {
    "name": "tjaychen",
    "email": "timothytim@google.com",
    "time": "Tue Mar 08 09:14:24 2022 -0800"
  },
  "message": "[pwrmgr] Alter behavior of ast clock enables\n\n- instead of changing the clock enable values only in specific states,\n  continuously evaluate the clock enable to ensure that a glitch cannot\n  permanently disable a clock.\n\n- this is done by outputting an \"active\" signal from the appropriate sparse\n  state. Using this signal, the logic then decides whether to evaluate\n  the clock enable on every cycle.  So if the clock enable were glitched \"off\",\n  it would be restored on the next cycle before the clock enable is re-evaluated\n  to be \"on\".  To completely disable a clock when not intended, the state itself\n  must be altered, and that should be significantly more difficult due to the\n  state being sparsely encoded.\n\n- This addresses an issue similar to #11156\n\nSigned-off-by: Timothy Chen \u003ctimothytim@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "682f96784cd4814a3e0f64c807de757694f70502",
      "old_mode": 33188,
      "old_path": "hw/ip/pwrmgr/rtl/pwrmgr_slow_fsm.sv",
      "new_id": "4ebda385f9d4719d52d03dc81b233d9ef47e5271",
      "new_mode": 33188,
      "new_path": "hw/ip/pwrmgr/rtl/pwrmgr_slow_fsm.sv"
    }
  ]
}