)]}'
{
  "commit": "21a20e241808df7074edc8aca4ccf6969ee5c6f2",
  "tree": "9bad98a2555040307623af5c04deaf349b67bf4d",
  "parents": [
    "ef65cb35521783cc2a8e291cf24d0a7369cd39e6"
  ],
  "author": {
    "name": "Weicai Yang",
    "email": "weicai@google.com",
    "time": "Mon Jun 08 18:02:50 2020 -0700"
  },
  "committer": {
    "name": "weicaiyang",
    "email": "49293026+weicaiyang@users.noreply.github.com",
    "time": "Wed Jun 10 18:48:46 2020 -0700"
  },
  "message": "[dv/uart] Fix a corner case\n\nDuring last bit of uart transfer, shouldn\u0027t read rdata to avoid\nunaccurary prediction. Here is the change\n\nOriginal:\n`wait_when_in_ignored_period; read N bytes`\nChange to:\n`repeat (N) {wait_when_in_ignored_period; read one byte}`\n\nSigned-off-by: Weicai Yang \u003cweicai@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0e5506042b92691b13fad68dc3b55a23c2c69a80",
      "old_mode": 33188,
      "old_path": "hw/ip/uart/dv/env/seq_lib/uart_base_vseq.sv",
      "new_id": "69f498fd43a2fbe3524a772972f50552664d578a",
      "new_mode": 33188,
      "new_path": "hw/ip/uart/dv/env/seq_lib/uart_base_vseq.sv"
    },
    {
      "type": "modify",
      "old_id": "7189a384b9888b837f5e61d70d43c0dbce7f6748",
      "old_mode": 33188,
      "old_path": "hw/ip/uart/dv/env/seq_lib/uart_tx_rx_vseq.sv",
      "new_id": "fbdb8c0bb58bef0409e5a9945440aee9bd14d25b",
      "new_mode": 33188,
      "new_path": "hw/ip/uart/dv/env/seq_lib/uart_tx_rx_vseq.sv"
    }
  ]
}