| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| |
| // UVM Registers auto-generated by `reggen` containing data structure |
| // Later, hand-edited to remove TL specific assumptions and made to work with JTAG interface. |
| // |
| // The following hand-edits were made: |
| // 1. Change individually_accessible attribute of all fields to 0, in the configure method. |
| // 2. Remove all backdoor paths. |
| // 3. Change the address offset of all registers added to the default_map from byte address to raw |
| // address with word size 32-bits. |
| // 4. Change default_map configuration to disable the byte_addressing attribute. |
| // 5. Removal of package wrapping. |
| |
| // Forward declare all register/memory/block classes |
| typedef class jtag_dmi_reg_abstractdata; |
| typedef class jtag_dmi_reg_dmcontrol; |
| typedef class jtag_dmi_reg_dmstatus; |
| typedef class jtag_dmi_reg_hartinfo; |
| typedef class jtag_dmi_reg_haltsum1; |
| typedef class jtag_dmi_reg_abstractcs; |
| typedef class jtag_dmi_reg_command; |
| typedef class jtag_dmi_reg_abstractauto; |
| typedef class jtag_dmi_reg_progbuf; |
| typedef class jtag_dmi_reg_haltsum2; |
| typedef class jtag_dmi_reg_haltsum3; |
| typedef class jtag_dmi_reg_sbcs; |
| typedef class jtag_dmi_reg_sbaddress0; |
| typedef class jtag_dmi_reg_sbaddress1; |
| typedef class jtag_dmi_reg_sbaddress2; |
| typedef class jtag_dmi_reg_sbaddress3; |
| typedef class jtag_dmi_reg_sbdata0; |
| typedef class jtag_dmi_reg_sbdata1; |
| typedef class jtag_dmi_reg_sbdata2; |
| typedef class jtag_dmi_reg_sbdata3; |
| typedef class jtag_dmi_reg_haltsum0; |
| typedef class jtag_dmi_reg_block; |
| |
| class jtag_dmi_reg_abstractdata extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field abstractdata; |
| |
| `uvm_object_utils(jtag_dmi_reg_abstractdata) |
| |
| function new(string name = "jtag_dmi_reg_abstractdata", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| abstractdata = (dv_base_reg_field:: |
| type_id::create("abstractdata_0")); |
| abstractdata.configure( |
| .parent(this), |
| .size(32), |
| .lsb_pos(0), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| abstractdata.set_original_access("RW"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_abstractdata |
| |
| class jtag_dmi_reg_dmcontrol extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field dmactive; |
| rand dv_base_reg_field ndmreset; |
| rand dv_base_reg_field clrresethaltreq; |
| rand dv_base_reg_field setresethaltreq; |
| rand dv_base_reg_field hartselhi; |
| rand dv_base_reg_field hartsello; |
| rand dv_base_reg_field hasel; |
| rand dv_base_reg_field ackhavereset; |
| rand dv_base_reg_field hartreset; |
| rand dv_base_reg_field resumereq; |
| rand dv_base_reg_field haltreq; |
| |
| `uvm_object_utils(jtag_dmi_reg_dmcontrol) |
| |
| function new(string name = "jtag_dmi_reg_dmcontrol", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| dmactive = (dv_base_reg_field:: |
| type_id::create("dmactive")); |
| dmactive.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(0), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| dmactive.set_original_access("RW"); |
| |
| ndmreset = (dv_base_reg_field:: |
| type_id::create("ndmreset")); |
| ndmreset.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(1), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| ndmreset.set_original_access("RW"); |
| |
| clrresethaltreq = (dv_base_reg_field:: |
| type_id::create("clrresethaltreq")); |
| clrresethaltreq.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(2), |
| .access("W1C"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| clrresethaltreq.set_original_access("W1C"); |
| |
| setresethaltreq = (dv_base_reg_field:: |
| type_id::create("setresethaltreq")); |
| setresethaltreq.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(3), |
| .access("W1C"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| setresethaltreq.set_original_access("W1C"); |
| |
| hartselhi = (dv_base_reg_field:: |
| type_id::create("hartselhi")); |
| hartselhi.configure( |
| .parent(this), |
| .size(10), |
| .lsb_pos(6), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| hartselhi.set_original_access("RW"); |
| |
| hartsello = (dv_base_reg_field:: |
| type_id::create("hartsello")); |
| hartsello.configure( |
| .parent(this), |
| .size(10), |
| .lsb_pos(16), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| hartsello.set_original_access("RW"); |
| |
| hasel = (dv_base_reg_field:: |
| type_id::create("hasel")); |
| hasel.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(26), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| hasel.set_original_access("RW"); |
| |
| ackhavereset = (dv_base_reg_field:: |
| type_id::create("ackhavereset")); |
| ackhavereset.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(28), |
| .access("W1C"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| ackhavereset.set_original_access("W1C"); |
| |
| hartreset = (dv_base_reg_field:: |
| type_id::create("hartreset")); |
| hartreset.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(29), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| hartreset.set_original_access("RW"); |
| |
| resumereq = (dv_base_reg_field:: |
| type_id::create("resumereq")); |
| resumereq.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(30), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| resumereq.set_original_access("RW"); |
| |
| haltreq = (dv_base_reg_field:: |
| type_id::create("haltreq")); |
| haltreq.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(31), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| haltreq.set_original_access("RW"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_dmcontrol |
| |
| class jtag_dmi_reg_dmstatus extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field version; |
| rand dv_base_reg_field confstrptrvalid; |
| rand dv_base_reg_field hasresethaltreq; |
| rand dv_base_reg_field authbusy; |
| rand dv_base_reg_field authenticated; |
| rand dv_base_reg_field anyhalted; |
| rand dv_base_reg_field allhalted; |
| rand dv_base_reg_field anyrunning; |
| rand dv_base_reg_field allrunning; |
| rand dv_base_reg_field anyunavail; |
| rand dv_base_reg_field allunavail; |
| rand dv_base_reg_field anynonexistent; |
| rand dv_base_reg_field allnonexistent; |
| rand dv_base_reg_field anyresumeack; |
| rand dv_base_reg_field allresumeack; |
| rand dv_base_reg_field anyhavereset; |
| rand dv_base_reg_field allhavereset; |
| rand dv_base_reg_field impebreak; |
| |
| `uvm_object_utils(jtag_dmi_reg_dmstatus) |
| |
| function new(string name = "jtag_dmi_reg_dmstatus", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| version = (dv_base_reg_field:: |
| type_id::create("version")); |
| version.configure( |
| .parent(this), |
| .size(4), |
| .lsb_pos(0), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h2), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| version.set_original_access("RO"); |
| |
| confstrptrvalid = (dv_base_reg_field:: |
| type_id::create("confstrptrvalid")); |
| confstrptrvalid.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(4), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| confstrptrvalid.set_original_access("RO"); |
| |
| hasresethaltreq = (dv_base_reg_field:: |
| type_id::create("hasresethaltreq")); |
| hasresethaltreq.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(5), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| hasresethaltreq.set_original_access("RO"); |
| |
| authbusy = (dv_base_reg_field:: |
| type_id::create("authbusy")); |
| authbusy.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(6), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| authbusy.set_original_access("RO"); |
| |
| authenticated = (dv_base_reg_field:: |
| type_id::create("authenticated")); |
| authenticated.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(7), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| authenticated.set_original_access("RO"); |
| |
| anyhalted = (dv_base_reg_field:: |
| type_id::create("anyhalted")); |
| anyhalted.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(8), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| anyhalted.set_original_access("RO"); |
| |
| allhalted = (dv_base_reg_field:: |
| type_id::create("allhalted")); |
| allhalted.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(9), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| allhalted.set_original_access("RO"); |
| |
| anyrunning = (dv_base_reg_field:: |
| type_id::create("anyrunning")); |
| anyrunning.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(10), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| anyrunning.set_original_access("RO"); |
| |
| allrunning = (dv_base_reg_field:: |
| type_id::create("allrunning")); |
| allrunning.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(11), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| allrunning.set_original_access("RO"); |
| |
| anyunavail = (dv_base_reg_field:: |
| type_id::create("anyunavail")); |
| anyunavail.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(12), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| anyunavail.set_original_access("RO"); |
| |
| allunavail = (dv_base_reg_field:: |
| type_id::create("allunavail")); |
| allunavail.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(13), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| allunavail.set_original_access("RO"); |
| |
| anynonexistent = (dv_base_reg_field:: |
| type_id::create("anynonexistent")); |
| anynonexistent.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(14), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| anynonexistent.set_original_access("RO"); |
| |
| allnonexistent = (dv_base_reg_field:: |
| type_id::create("allnonexistent")); |
| allnonexistent.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(15), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| allnonexistent.set_original_access("RO"); |
| |
| anyresumeack = (dv_base_reg_field:: |
| type_id::create("anyresumeack")); |
| anyresumeack.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(16), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| anyresumeack.set_original_access("RO"); |
| |
| allresumeack = (dv_base_reg_field:: |
| type_id::create("allresumeack")); |
| allresumeack.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(17), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| allresumeack.set_original_access("RO"); |
| |
| anyhavereset = (dv_base_reg_field:: |
| type_id::create("anyhavereset")); |
| anyhavereset.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(18), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h1), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| anyhavereset.set_original_access("RO"); |
| |
| allhavereset = (dv_base_reg_field:: |
| type_id::create("allhavereset")); |
| allhavereset.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(19), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h1), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| allhavereset.set_original_access("RO"); |
| |
| impebreak = (dv_base_reg_field:: |
| type_id::create("impebreak")); |
| impebreak.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(22), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| impebreak.set_original_access("RO"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_dmstatus |
| |
| class jtag_dmi_reg_hartinfo extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field dataaddr; |
| rand dv_base_reg_field datasize; |
| rand dv_base_reg_field dataaccess; |
| rand dv_base_reg_field nscratch; |
| |
| `uvm_object_utils(jtag_dmi_reg_hartinfo) |
| |
| function new(string name = "jtag_dmi_reg_hartinfo", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| dataaddr = (dv_base_reg_field:: |
| type_id::create("dataaddr")); |
| dataaddr.configure( |
| .parent(this), |
| .size(12), |
| .lsb_pos(0), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| dataaddr.set_original_access("RO"); |
| |
| datasize = (dv_base_reg_field:: |
| type_id::create("datasize")); |
| datasize.configure( |
| .parent(this), |
| .size(4), |
| .lsb_pos(12), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| datasize.set_original_access("RO"); |
| |
| dataaccess = (dv_base_reg_field:: |
| type_id::create("dataaccess")); |
| dataaccess.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(16), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| dataaccess.set_original_access("RO"); |
| |
| nscratch = (dv_base_reg_field:: |
| type_id::create("nscratch")); |
| nscratch.configure( |
| .parent(this), |
| .size(4), |
| .lsb_pos(20), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| nscratch.set_original_access("RO"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_hartinfo |
| |
| class jtag_dmi_reg_haltsum1 extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field haltsum1; |
| |
| `uvm_object_utils(jtag_dmi_reg_haltsum1) |
| |
| function new(string name = "jtag_dmi_reg_haltsum1", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| haltsum1 = (dv_base_reg_field:: |
| type_id::create("haltsum1")); |
| haltsum1.configure( |
| .parent(this), |
| .size(32), |
| .lsb_pos(0), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| haltsum1.set_original_access("RO"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_haltsum1 |
| |
| class jtag_dmi_reg_abstractcs extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field datacount; |
| rand dv_base_reg_field cmderr; |
| rand dv_base_reg_field busy; |
| rand dv_base_reg_field progbufsize; |
| |
| `uvm_object_utils(jtag_dmi_reg_abstractcs) |
| |
| function new(string name = "jtag_dmi_reg_abstractcs", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| datacount = (dv_base_reg_field:: |
| type_id::create("datacount")); |
| datacount.configure( |
| .parent(this), |
| .size(4), |
| .lsb_pos(0), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| datacount.set_original_access("RO"); |
| |
| cmderr = (dv_base_reg_field:: |
| type_id::create("cmderr")); |
| cmderr.configure( |
| .parent(this), |
| .size(3), |
| .lsb_pos(8), |
| .access("W1C"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| cmderr.set_original_access("W1C"); |
| |
| busy = (dv_base_reg_field:: |
| type_id::create("busy")); |
| busy.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(12), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| busy.set_original_access("RO"); |
| |
| progbufsize = (dv_base_reg_field:: |
| type_id::create("progbufsize")); |
| progbufsize.configure( |
| .parent(this), |
| .size(5), |
| .lsb_pos(24), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| progbufsize.set_original_access("RO"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_abstractcs |
| |
| class jtag_dmi_reg_command extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field control; |
| rand dv_base_reg_field cmdtype; |
| |
| `uvm_object_utils(jtag_dmi_reg_command) |
| |
| function new(string name = "jtag_dmi_reg_command", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| control = (dv_base_reg_field:: |
| type_id::create("control")); |
| control.configure( |
| .parent(this), |
| .size(24), |
| .lsb_pos(0), |
| .access("WO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| control.set_original_access("WO"); |
| |
| cmdtype = (dv_base_reg_field:: |
| type_id::create("cmdtype")); |
| cmdtype.configure( |
| .parent(this), |
| .size(8), |
| .lsb_pos(24), |
| .access("WO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| cmdtype.set_original_access("WO"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_command |
| |
| class jtag_dmi_reg_abstractauto extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field autoexecdata; |
| rand dv_base_reg_field autoexecprogbuf; |
| |
| `uvm_object_utils(jtag_dmi_reg_abstractauto) |
| |
| function new(string name = "jtag_dmi_reg_abstractauto", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| autoexecdata = (dv_base_reg_field:: |
| type_id::create("autoexecdata")); |
| autoexecdata.configure( |
| .parent(this), |
| .size(12), |
| .lsb_pos(0), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| autoexecdata.set_original_access("RW"); |
| |
| autoexecprogbuf = (dv_base_reg_field:: |
| type_id::create("autoexecprogbuf")); |
| autoexecprogbuf.configure( |
| .parent(this), |
| .size(16), |
| .lsb_pos(16), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| autoexecprogbuf.set_original_access("RW"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_abstractauto |
| |
| class jtag_dmi_reg_progbuf extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field data; |
| |
| `uvm_object_utils(jtag_dmi_reg_progbuf) |
| |
| function new(string name = "jtag_dmi_reg_progbuf", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| data = (dv_base_reg_field:: |
| type_id::create("data_0")); |
| data.configure( |
| .parent(this), |
| .size(32), |
| .lsb_pos(0), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| data.set_original_access("RW"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_progbuf |
| |
| class jtag_dmi_reg_haltsum2 extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field haltsum2; |
| |
| `uvm_object_utils(jtag_dmi_reg_haltsum2) |
| |
| function new(string name = "jtag_dmi_reg_haltsum2", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| haltsum2 = (dv_base_reg_field:: |
| type_id::create("haltsum2")); |
| haltsum2.configure( |
| .parent(this), |
| .size(32), |
| .lsb_pos(0), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| haltsum2.set_original_access("RO"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_haltsum2 |
| |
| class jtag_dmi_reg_haltsum3 extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field haltsum3; |
| |
| `uvm_object_utils(jtag_dmi_reg_haltsum3) |
| |
| function new(string name = "jtag_dmi_reg_haltsum3", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| haltsum3 = (dv_base_reg_field:: |
| type_id::create("haltsum3")); |
| haltsum3.configure( |
| .parent(this), |
| .size(32), |
| .lsb_pos(0), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| haltsum3.set_original_access("RO"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_haltsum3 |
| |
| class jtag_dmi_reg_field_sbcs_sberror extends dv_base_reg_field; |
| `uvm_object_utils(jtag_dmi_reg_field_sbcs_sberror) |
| |
| function new(string name = "jtag_dmi_reg_field_sbcs_sberror"); |
| super.new(name); |
| endfunction: new |
| |
| // Field is cleared when written to 1 exactly. |
| virtual function uvm_reg_data_t XpredictX(uvm_reg_data_t cur_val, |
| uvm_reg_data_t wr_val, |
| uvm_reg_map map); |
| if (get_access(map) == "W1C" && wr_val == 1) return 0; |
| else return super.XpredictX(cur_val, wr_val, map); |
| endfunction |
| |
| endclass |
| |
| class jtag_dmi_reg_sbcs extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field sbaccess8; |
| rand dv_base_reg_field sbaccess16; |
| rand dv_base_reg_field sbaccess32; |
| rand dv_base_reg_field sbaccess64; |
| rand dv_base_reg_field sbaccess128; |
| rand dv_base_reg_field sbasize; |
| rand jtag_dmi_reg_field_sbcs_sberror sberror; |
| rand dv_base_reg_field sbreadondata; |
| rand dv_base_reg_field sbautoincrement; |
| rand dv_base_reg_field sbaccess; |
| rand dv_base_reg_field sbreadonaddr; |
| rand dv_base_reg_field sbbusy; |
| rand dv_base_reg_field sbbusyerror; |
| rand dv_base_reg_field zero0; |
| rand dv_base_reg_field sbversion; |
| |
| `uvm_object_utils(jtag_dmi_reg_sbcs) |
| |
| function new(string name = "jtag_dmi_reg_sbcs", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| sbaccess8 = (dv_base_reg_field:: |
| type_id::create("sbaccess8")); |
| sbaccess8.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(0), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| sbaccess8.set_original_access("RO"); |
| |
| sbaccess16 = (dv_base_reg_field:: |
| type_id::create("sbaccess16")); |
| sbaccess16.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(1), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| sbaccess16.set_original_access("RO"); |
| |
| sbaccess32 = (dv_base_reg_field:: |
| type_id::create("sbaccess32")); |
| sbaccess32.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(2), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| sbaccess32.set_original_access("RO"); |
| |
| sbaccess64 = (dv_base_reg_field:: |
| type_id::create("sbaccess64")); |
| sbaccess64.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(3), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| sbaccess64.set_original_access("RO"); |
| |
| sbaccess128 = (dv_base_reg_field:: |
| type_id::create("sbaccess128")); |
| sbaccess128.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(4), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| sbaccess128.set_original_access("RO"); |
| |
| sbasize = (dv_base_reg_field:: |
| type_id::create("sbasize")); |
| sbasize.configure( |
| .parent(this), |
| .size(7), |
| .lsb_pos(5), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| sbasize.set_original_access("RO"); |
| |
| sberror = (jtag_dmi_reg_field_sbcs_sberror:: |
| type_id::create("sberror")); |
| sberror.configure( |
| .parent(this), |
| .size(3), |
| .lsb_pos(12), |
| .access("W1C"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| sberror.set_original_access("W1C"); |
| |
| sbreadondata = (dv_base_reg_field:: |
| type_id::create("sbreadondata")); |
| sbreadondata.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(15), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| sbreadondata.set_original_access("RW"); |
| |
| sbautoincrement = (dv_base_reg_field:: |
| type_id::create("sbautoincrement")); |
| sbautoincrement.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(16), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| sbautoincrement.set_original_access("RW"); |
| |
| sbaccess = (dv_base_reg_field:: |
| type_id::create("sbaccess")); |
| sbaccess.configure( |
| .parent(this), |
| .size(3), |
| .lsb_pos(17), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h2), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| sbaccess.set_original_access("RW"); |
| |
| sbreadonaddr = (dv_base_reg_field:: |
| type_id::create("sbreadonaddr")); |
| sbreadonaddr.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(20), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| sbreadonaddr.set_original_access("RW"); |
| |
| sbbusy = (dv_base_reg_field:: |
| type_id::create("sbbusy")); |
| sbbusy.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(21), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| sbbusy.set_original_access("RO"); |
| |
| sbbusyerror = (dv_base_reg_field:: |
| type_id::create("sbbusyerror")); |
| sbbusyerror.configure( |
| .parent(this), |
| .size(1), |
| .lsb_pos(22), |
| .access("W1C"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| sbbusyerror.set_original_access("W1C"); |
| |
| zero0 = (dv_base_reg_field:: |
| type_id::create("zero0")); |
| zero0.configure( |
| .parent(this), |
| .size(6), |
| .lsb_pos(23), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| zero0.set_original_access("RW"); |
| |
| sbversion = (dv_base_reg_field:: |
| type_id::create("sbversion")); |
| sbversion.configure( |
| .parent(this), |
| .size(3), |
| .lsb_pos(29), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h1), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| sbversion.set_original_access("RO"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_sbcs |
| |
| class jtag_dmi_reg_sbaddress0 extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field address; |
| |
| `uvm_object_utils(jtag_dmi_reg_sbaddress0) |
| |
| function new(string name = "jtag_dmi_reg_sbaddress0", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| address = (dv_base_reg_field:: |
| type_id::create("address")); |
| address.configure( |
| .parent(this), |
| .size(32), |
| .lsb_pos(0), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| address.set_original_access("RW"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_sbaddress0 |
| |
| class jtag_dmi_reg_sbaddress1 extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field address; |
| |
| `uvm_object_utils(jtag_dmi_reg_sbaddress1) |
| |
| function new(string name = "jtag_dmi_reg_sbaddress1", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| address = (dv_base_reg_field:: |
| type_id::create("address")); |
| address.configure( |
| .parent(this), |
| .size(32), |
| .lsb_pos(0), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| address.set_original_access("RW"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_sbaddress1 |
| |
| class jtag_dmi_reg_sbaddress2 extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field address; |
| |
| `uvm_object_utils(jtag_dmi_reg_sbaddress2) |
| |
| function new(string name = "jtag_dmi_reg_sbaddress2", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| address = (dv_base_reg_field:: |
| type_id::create("address")); |
| address.configure( |
| .parent(this), |
| .size(32), |
| .lsb_pos(0), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| address.set_original_access("RW"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_sbaddress2 |
| |
| class jtag_dmi_reg_sbaddress3 extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field address; |
| |
| `uvm_object_utils(jtag_dmi_reg_sbaddress3) |
| |
| function new(string name = "jtag_dmi_reg_sbaddress3", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| address = (dv_base_reg_field:: |
| type_id::create("address")); |
| address.configure( |
| .parent(this), |
| .size(32), |
| .lsb_pos(0), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| address.set_original_access("RW"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_sbaddress3 |
| |
| class jtag_dmi_reg_sbdata0 extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field data; |
| |
| `uvm_object_utils(jtag_dmi_reg_sbdata0) |
| |
| function new(string name = "jtag_dmi_reg_sbdata0", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| data = (dv_base_reg_field:: |
| type_id::create("data")); |
| data.configure( |
| .parent(this), |
| .size(32), |
| .lsb_pos(0), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| data.set_original_access("RW"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_sbdata0 |
| |
| class jtag_dmi_reg_sbdata1 extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field data; |
| |
| `uvm_object_utils(jtag_dmi_reg_sbdata1) |
| |
| function new(string name = "jtag_dmi_reg_sbdata1", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| data = (dv_base_reg_field:: |
| type_id::create("data")); |
| data.configure( |
| .parent(this), |
| .size(32), |
| .lsb_pos(0), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| data.set_original_access("RW"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_sbdata1 |
| |
| class jtag_dmi_reg_sbdata2 extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field data; |
| |
| `uvm_object_utils(jtag_dmi_reg_sbdata2) |
| |
| function new(string name = "jtag_dmi_reg_sbdata2", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| data = (dv_base_reg_field:: |
| type_id::create("data")); |
| data.configure( |
| .parent(this), |
| .size(32), |
| .lsb_pos(0), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| data.set_original_access("RW"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_sbdata2 |
| |
| class jtag_dmi_reg_sbdata3 extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field data; |
| |
| `uvm_object_utils(jtag_dmi_reg_sbdata3) |
| |
| function new(string name = "jtag_dmi_reg_sbdata3", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| data = (dv_base_reg_field:: |
| type_id::create("data")); |
| data.configure( |
| .parent(this), |
| .size(32), |
| .lsb_pos(0), |
| .access("RW"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| data.set_original_access("RW"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_sbdata3 |
| |
| class jtag_dmi_reg_haltsum0 extends dv_base_reg; |
| // fields |
| rand dv_base_reg_field haltsum0; |
| |
| `uvm_object_utils(jtag_dmi_reg_haltsum0) |
| |
| function new(string name = "jtag_dmi_reg_haltsum0", |
| int unsigned n_bits = 32, |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, n_bits, has_coverage); |
| endfunction : new |
| |
| virtual function void build(csr_excl_item csr_excl = null); |
| // create fields |
| haltsum0 = (dv_base_reg_field:: |
| type_id::create("haltsum0")); |
| haltsum0.configure( |
| .parent(this), |
| .size(32), |
| .lsb_pos(0), |
| .access("RO"), |
| .volatile(0), |
| .reset(32'h0), |
| .has_reset(1), |
| .is_rand(1), |
| .individually_accessible(0)); |
| |
| haltsum0.set_original_access("RO"); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_haltsum0 |
| |
| class jtag_dmi_reg_block extends dv_base_reg_block; |
| // registers |
| rand jtag_dmi_reg_abstractdata abstractdata[12]; |
| rand jtag_dmi_reg_dmcontrol dmcontrol; |
| rand jtag_dmi_reg_dmstatus dmstatus; |
| rand jtag_dmi_reg_hartinfo hartinfo; |
| rand jtag_dmi_reg_haltsum1 haltsum1; |
| rand jtag_dmi_reg_abstractcs abstractcs; |
| rand jtag_dmi_reg_command command; |
| rand jtag_dmi_reg_abstractauto abstractauto; |
| rand jtag_dmi_reg_progbuf progbuf[16]; |
| rand jtag_dmi_reg_haltsum2 haltsum2; |
| rand jtag_dmi_reg_haltsum3 haltsum3; |
| rand jtag_dmi_reg_sbcs sbcs; |
| rand jtag_dmi_reg_sbaddress0 sbaddress0; |
| rand jtag_dmi_reg_sbaddress1 sbaddress1; |
| rand jtag_dmi_reg_sbaddress2 sbaddress2; |
| rand jtag_dmi_reg_sbaddress3 sbaddress3; |
| rand jtag_dmi_reg_sbdata0 sbdata0; |
| rand jtag_dmi_reg_sbdata1 sbdata1; |
| rand jtag_dmi_reg_sbdata2 sbdata2; |
| rand jtag_dmi_reg_sbdata3 sbdata3; |
| rand jtag_dmi_reg_haltsum0 haltsum0; |
| |
| `uvm_object_utils(jtag_dmi_reg_block) |
| |
| function new(string name = "jtag_dmi_reg_block", |
| int has_coverage = UVM_NO_COVERAGE); |
| super.new(name, has_coverage); |
| endfunction : new |
| |
| virtual function void build(uvm_reg_addr_t base_addr, |
| csr_excl_item csr_excl = null); |
| // create default map |
| this.default_map = create_map(.name("default_map"), |
| .base_addr(base_addr), |
| .n_bytes(4), |
| .endian(UVM_LITTLE_ENDIAN), |
| .byte_addressing(0)); |
| if (csr_excl == null) begin |
| csr_excl = csr_excl_item::type_id::create("csr_excl"); |
| this.csr_excl = csr_excl; |
| end |
| // create registers |
| abstractdata[0] = (jtag_dmi_reg_abstractdata:: |
| type_id::create("abstractdata_0")); |
| abstractdata[0].configure(.blk_parent(this)); |
| abstractdata[0].build(csr_excl); |
| default_map.add_reg(.rg(abstractdata[0]), |
| .offset(32'h4)); |
| |
| abstractdata[1] = (jtag_dmi_reg_abstractdata:: |
| type_id::create("abstractdata_1")); |
| abstractdata[1].configure(.blk_parent(this)); |
| abstractdata[1].build(csr_excl); |
| default_map.add_reg(.rg(abstractdata[1]), |
| .offset(32'h5)); |
| |
| abstractdata[2] = (jtag_dmi_reg_abstractdata:: |
| type_id::create("abstractdata_2")); |
| abstractdata[2].configure(.blk_parent(this)); |
| abstractdata[2].build(csr_excl); |
| default_map.add_reg(.rg(abstractdata[2]), |
| .offset(32'h6)); |
| |
| abstractdata[3] = (jtag_dmi_reg_abstractdata:: |
| type_id::create("abstractdata_3")); |
| abstractdata[3].configure(.blk_parent(this)); |
| abstractdata[3].build(csr_excl); |
| default_map.add_reg(.rg(abstractdata[3]), |
| .offset(32'h7)); |
| |
| abstractdata[4] = (jtag_dmi_reg_abstractdata:: |
| type_id::create("abstractdata_4")); |
| abstractdata[4].configure(.blk_parent(this)); |
| abstractdata[4].build(csr_excl); |
| default_map.add_reg(.rg(abstractdata[4]), |
| .offset(32'h8)); |
| |
| abstractdata[5] = (jtag_dmi_reg_abstractdata:: |
| type_id::create("abstractdata_5")); |
| abstractdata[5].configure(.blk_parent(this)); |
| abstractdata[5].build(csr_excl); |
| default_map.add_reg(.rg(abstractdata[5]), |
| .offset(32'h9)); |
| |
| abstractdata[6] = (jtag_dmi_reg_abstractdata:: |
| type_id::create("abstractdata_6")); |
| abstractdata[6].configure(.blk_parent(this)); |
| abstractdata[6].build(csr_excl); |
| default_map.add_reg(.rg(abstractdata[6]), |
| .offset(32'ha)); |
| |
| abstractdata[7] = (jtag_dmi_reg_abstractdata:: |
| type_id::create("abstractdata_7")); |
| abstractdata[7].configure(.blk_parent(this)); |
| abstractdata[7].build(csr_excl); |
| default_map.add_reg(.rg(abstractdata[7]), |
| .offset(32'hb)); |
| |
| abstractdata[8] = (jtag_dmi_reg_abstractdata:: |
| type_id::create("abstractdata_8")); |
| abstractdata[8].configure(.blk_parent(this)); |
| abstractdata[8].build(csr_excl); |
| default_map.add_reg(.rg(abstractdata[8]), |
| .offset(32'hc)); |
| |
| abstractdata[9] = (jtag_dmi_reg_abstractdata:: |
| type_id::create("abstractdata_9")); |
| abstractdata[9].configure(.blk_parent(this)); |
| abstractdata[9].build(csr_excl); |
| default_map.add_reg(.rg(abstractdata[9]), |
| .offset(32'hd)); |
| |
| abstractdata[10] = (jtag_dmi_reg_abstractdata:: |
| type_id::create("abstractdata_10")); |
| abstractdata[10].configure(.blk_parent(this)); |
| abstractdata[10].build(csr_excl); |
| default_map.add_reg(.rg(abstractdata[10]), |
| .offset(32'he)); |
| |
| abstractdata[11] = (jtag_dmi_reg_abstractdata:: |
| type_id::create("abstractdata_11")); |
| abstractdata[11].configure(.blk_parent(this)); |
| abstractdata[11].build(csr_excl); |
| default_map.add_reg(.rg(abstractdata[11]), |
| .offset(32'hf)); |
| |
| dmcontrol = (jtag_dmi_reg_dmcontrol:: |
| type_id::create("dmcontrol")); |
| dmcontrol.configure(.blk_parent(this)); |
| dmcontrol.build(csr_excl); |
| default_map.add_reg(.rg(dmcontrol), |
| .offset(32'h10)); |
| |
| dmstatus = (jtag_dmi_reg_dmstatus:: |
| type_id::create("dmstatus")); |
| dmstatus.configure(.blk_parent(this)); |
| dmstatus.build(csr_excl); |
| default_map.add_reg(.rg(dmstatus), |
| .offset(32'h11)); |
| |
| hartinfo = (jtag_dmi_reg_hartinfo:: |
| type_id::create("hartinfo")); |
| hartinfo.configure(.blk_parent(this)); |
| hartinfo.build(csr_excl); |
| default_map.add_reg(.rg(hartinfo), |
| .offset(32'h12)); |
| |
| haltsum1 = (jtag_dmi_reg_haltsum1:: |
| type_id::create("haltsum1")); |
| haltsum1.configure(.blk_parent(this)); |
| haltsum1.build(csr_excl); |
| default_map.add_reg(.rg(haltsum1), |
| .offset(32'h13)); |
| |
| abstractcs = (jtag_dmi_reg_abstractcs:: |
| type_id::create("abstractcs")); |
| abstractcs.configure(.blk_parent(this)); |
| abstractcs.build(csr_excl); |
| default_map.add_reg(.rg(abstractcs), |
| .offset(32'h16)); |
| |
| command = (jtag_dmi_reg_command:: |
| type_id::create("command")); |
| command.configure(.blk_parent(this)); |
| command.build(csr_excl); |
| default_map.add_reg(.rg(command), |
| .offset(32'h17)); |
| |
| abstractauto = (jtag_dmi_reg_abstractauto:: |
| type_id::create("abstractauto")); |
| abstractauto.configure(.blk_parent(this)); |
| abstractauto.build(csr_excl); |
| default_map.add_reg(.rg(abstractauto), |
| .offset(32'h18)); |
| |
| progbuf[0] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_0")); |
| progbuf[0].configure(.blk_parent(this)); |
| progbuf[0].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[0]), |
| .offset(32'h20)); |
| |
| progbuf[1] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_1")); |
| progbuf[1].configure(.blk_parent(this)); |
| progbuf[1].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[1]), |
| .offset(32'h21)); |
| |
| progbuf[2] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_2")); |
| progbuf[2].configure(.blk_parent(this)); |
| progbuf[2].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[2]), |
| .offset(32'h22)); |
| |
| progbuf[3] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_3")); |
| progbuf[3].configure(.blk_parent(this)); |
| progbuf[3].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[3]), |
| .offset(32'h23)); |
| |
| progbuf[4] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_4")); |
| progbuf[4].configure(.blk_parent(this)); |
| progbuf[4].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[4]), |
| .offset(32'h24)); |
| |
| progbuf[5] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_5")); |
| progbuf[5].configure(.blk_parent(this)); |
| progbuf[5].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[5]), |
| .offset(32'h25)); |
| |
| progbuf[6] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_6")); |
| progbuf[6].configure(.blk_parent(this)); |
| progbuf[6].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[6]), |
| .offset(32'h26)); |
| |
| progbuf[7] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_7")); |
| progbuf[7].configure(.blk_parent(this)); |
| progbuf[7].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[7]), |
| .offset(32'h27)); |
| |
| progbuf[8] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_8")); |
| progbuf[8].configure(.blk_parent(this)); |
| progbuf[8].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[8]), |
| .offset(32'h28)); |
| |
| progbuf[9] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_9")); |
| progbuf[9].configure(.blk_parent(this)); |
| progbuf[9].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[9]), |
| .offset(32'h29)); |
| |
| progbuf[10] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_10")); |
| progbuf[10].configure(.blk_parent(this)); |
| progbuf[10].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[10]), |
| .offset(32'h2a)); |
| |
| progbuf[11] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_11")); |
| progbuf[11].configure(.blk_parent(this)); |
| progbuf[11].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[11]), |
| .offset(32'h2b)); |
| |
| progbuf[12] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_12")); |
| progbuf[12].configure(.blk_parent(this)); |
| progbuf[12].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[12]), |
| .offset(32'h2c)); |
| |
| progbuf[13] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_13")); |
| progbuf[13].configure(.blk_parent(this)); |
| progbuf[13].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[13]), |
| .offset(32'h2d)); |
| |
| progbuf[14] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_14")); |
| progbuf[14].configure(.blk_parent(this)); |
| progbuf[14].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[14]), |
| .offset(32'h2e)); |
| |
| progbuf[15] = (jtag_dmi_reg_progbuf:: |
| type_id::create("progbuf_15")); |
| progbuf[15].configure(.blk_parent(this)); |
| progbuf[15].build(csr_excl); |
| default_map.add_reg(.rg(progbuf[15]), |
| .offset(32'h2f)); |
| |
| haltsum2 = (jtag_dmi_reg_haltsum2:: |
| type_id::create("haltsum2")); |
| haltsum2.configure(.blk_parent(this)); |
| haltsum2.build(csr_excl); |
| default_map.add_reg(.rg(haltsum2), |
| .offset(32'h34)); |
| |
| haltsum3 = (jtag_dmi_reg_haltsum3:: |
| type_id::create("haltsum3")); |
| haltsum3.configure(.blk_parent(this)); |
| haltsum3.build(csr_excl); |
| default_map.add_reg(.rg(haltsum3), |
| .offset(32'h35)); |
| |
| sbcs = (jtag_dmi_reg_sbcs:: |
| type_id::create("sbcs")); |
| sbcs.configure(.blk_parent(this)); |
| sbcs.build(csr_excl); |
| default_map.add_reg(.rg(sbcs), |
| .offset(32'h38)); |
| |
| sbaddress0 = (jtag_dmi_reg_sbaddress0:: |
| type_id::create("sbaddress0")); |
| sbaddress0.configure(.blk_parent(this)); |
| sbaddress0.build(csr_excl); |
| default_map.add_reg(.rg(sbaddress0), |
| .offset(32'h39)); |
| |
| sbaddress1 = (jtag_dmi_reg_sbaddress1:: |
| type_id::create("sbaddress1")); |
| sbaddress1.configure(.blk_parent(this)); |
| sbaddress1.build(csr_excl); |
| default_map.add_reg(.rg(sbaddress1), |
| .offset(32'h3a)); |
| |
| sbaddress2 = (jtag_dmi_reg_sbaddress2:: |
| type_id::create("sbaddress2")); |
| sbaddress2.configure(.blk_parent(this)); |
| sbaddress2.build(csr_excl); |
| default_map.add_reg(.rg(sbaddress2), |
| .offset(32'h3b)); |
| |
| sbaddress3 = (jtag_dmi_reg_sbaddress3:: |
| type_id::create("sbaddress3")); |
| sbaddress3.configure(.blk_parent(this)); |
| sbaddress3.build(csr_excl); |
| default_map.add_reg(.rg(sbaddress3), |
| .offset(32'h37)); |
| |
| sbdata0 = (jtag_dmi_reg_sbdata0:: |
| type_id::create("sbdata0")); |
| sbdata0.configure(.blk_parent(this)); |
| sbdata0.build(csr_excl); |
| default_map.add_reg(.rg(sbdata0), |
| .offset(32'h3c)); |
| |
| sbdata1 = (jtag_dmi_reg_sbdata1:: |
| type_id::create("sbdata1")); |
| sbdata1.configure(.blk_parent(this)); |
| sbdata1.build(csr_excl); |
| default_map.add_reg(.rg(sbdata1), |
| .offset(32'h3d)); |
| |
| sbdata2 = (jtag_dmi_reg_sbdata2:: |
| type_id::create("sbdata2")); |
| sbdata2.configure(.blk_parent(this)); |
| sbdata2.build(csr_excl); |
| default_map.add_reg(.rg(sbdata2), |
| .offset(32'h3e)); |
| |
| sbdata3 = (jtag_dmi_reg_sbdata3:: |
| type_id::create("sbdata3")); |
| sbdata3.configure(.blk_parent(this)); |
| sbdata3.build(csr_excl); |
| default_map.add_reg(.rg(sbdata3), |
| .offset(32'h3f)); |
| |
| haltsum0 = (jtag_dmi_reg_haltsum0:: |
| type_id::create("haltsum0")); |
| haltsum0.configure(.blk_parent(this)); |
| haltsum0.build(csr_excl); |
| default_map.add_reg(.rg(haltsum0), |
| .offset(32'h40)); |
| |
| endfunction : build |
| endclass : jtag_dmi_reg_block |
