diff --git a/sw/device/silicon_creator/rom/data/rom_testplan.hjson b/sw/device/silicon_creator/rom/data/rom_testplan.hjson
index 6a9d226..2235d82 100644
--- a/sw/device/silicon_creator/rom/data/rom_testplan.hjson
+++ b/sw/device/silicon_creator/rom/data/rom_testplan.hjson
@@ -405,15 +405,12 @@
             `OWNER_SW_CFG_ROM_BOOTSTRAP_EN` OTP item must be `kHardenedBoolTrue` (`0x739`).
 
             - Apply bootstrap pin strapping and reset the chip.
-            - Send `erase`.
-            - Write `0x4552544f` (ASCII "OTRE") at byte offset `0x334`.
+            - Send `CHIP_ERASE` (`0xc7`).
+            - Write `0x4552544f_00000000` (ASCII "\0\0\0\0OTRE") at byte offset `0x80330`.
+              - Note: Writes must start at a flash-word-aligned address and we must write to the second slot since ROM returns the last error.
             - Release pins and reset.
-            - Verify that the chip outputs the expected `BFV`: `024d410d`
-              (`kErrorManifestBadCodeRegion`) over UART.
+            - Verify that the chip outputs the expected `BFV`: `0242500d` over UART (`kErrorBootPolicyBadLength`).
               - ROM will continously reset the chip and output the same `BFV` and `LCV`.
-
-            Note: For additional coverage we can also add another test point that uses a test
-            program on flash that verifies that the rest of the flash is empty after bootstrap.
             '''
       tags: ["rom", "verilator", "dv", "fpga", "silicon"]
       stage: V2
diff --git a/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs b/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs
index 10b7eaa..7d39eb1 100644
--- a/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs
+++ b/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs
@@ -463,6 +463,33 @@
     Ok(())
 }
 
+fn test_bootstrap_phase2_page_program(opts: &Opts, transport: &TransportWrapper) -> Result<()> {
+    let _bs = BootstrapTest::start(transport, opts.init.bootstrap.options.reset_delay)?;
+    let spi = transport.spi("0")?;
+    let uart = transport.uart("0")?;
+    SpiFlash::from_spi(&*spi)?
+        // Send CHIP_ERASE to transition to phase 2.
+        .chip_erase(&*spi)?
+        // Write "OTRE" to the identifier field of the manifest in the second slot.
+        .program(&*spi, 0x80330, &0x4552544f_00000000u64.to_le_bytes())?;
+
+    let mut console = UartConsole {
+        timeout: Some(Duration::new(1, 0)),
+        // `kErrorBootPolicyBadLength` (0242500d) is defined in `error.h`.
+        exit_success: Some(Regex::new("BFV:0242500d\r\n")?),
+        ..Default::default()
+    };
+    // Remove strapping so that chip fails to boot instead of going into bootstrap.
+    transport.remove_pin_strapping("ROM_BOOTSTRAP")?;
+    transport.reset_target(opts.init.bootstrap.options.reset_delay, true)?;
+    let result = console.interact(&*uart, None, Some(&mut std::io::stdout()))?;
+    if result != ExitStatus::ExitSuccess {
+        bail!("FAIL: {:?}", result);
+    }
+
+    Ok(())
+}
+
 fn main() -> Result<()> {
     let opts = Opts::from_args();
     opts.init.init_logging();
@@ -488,6 +515,7 @@
     }
     execute_test!(test_bootstrap_phase1_read, &opts, &transport);
     execute_test!(test_bootstrap_phase2_reset, &opts, &transport);
+    execute_test!(test_bootstrap_phase2_page_program, &opts, &transport);
 
     Ok(())
 }