tree f7985daac7ef25527de7480477fc2bc66685cf7d
parent a39557eb0b8f1bc90461b4bc90f7a22b49a410ec
author Michael Schaffner <msf@opentitan.org> 1584037430 -0700
committer Michael Schaffner <msf@google.com> 1584592382 -0700

[syn] This adds a simple testsynthesis flow for DC

This adds a similar makefile based test synthesis flow for DC  analogous
to the AscentLint flow. It allows to run a simple wire-load-model-based
synthesis of individual IPs or the top-level.

Two example targets are provided within this PR, and they can be called
by stepping into `hw/syn` and running:
```
make ip-aes_syn
make systems-top_earlgrey_syn
```
Area, timing, power and link reports will be written to
`hw/syn/reports` once synthesis has completed.

Note that this is only a starting point and will soon be extended.

Also, this requires a technology setup scripts and the corresponding
technology wrapper primitives to be present under `hw/foundry/syn/dc`
and `hw/foundry/ip/prim_<tech id>/`

The integration into the dvsim dashboard (analogous to AscentLint) is in
the making and will follow in a subsequent PR (together with more
documentation).

Signed-off-by: Michael Schaffner <msf@opentitan.org>