)]}'
{
  "commit": "17df5a2fcf2825e3bdd8a89cfd5dbea0dd39cd63",
  "tree": "f7985daac7ef25527de7480477fc2bc66685cf7d",
  "parents": [
    "a39557eb0b8f1bc90461b4bc90f7a22b49a410ec"
  ],
  "author": {
    "name": "Michael Schaffner",
    "email": "msf@opentitan.org",
    "time": "Thu Mar 12 11:23:50 2020 -0700"
  },
  "committer": {
    "name": "Michael Schaffner",
    "email": "msf@google.com",
    "time": "Wed Mar 18 21:33:02 2020 -0700"
  },
  "message": "[syn] This adds a simple testsynthesis flow for DC\n\nThis adds a similar makefile based test synthesis flow for DC  analogous\nto the AscentLint flow. It allows to run a simple wire-load-model-based\nsynthesis of individual IPs or the top-level.\n\nTwo example targets are provided within this PR, and they can be called\nby stepping into `hw/syn` and running:\n```\nmake ip-aes_syn\nmake systems-top_earlgrey_syn\n```\nArea, timing, power and link reports will be written to\n`hw/syn/reports` once synthesis has completed.\n\nNote that this is only a starting point and will soon be extended.\n\nAlso, this requires a technology setup scripts and the corresponding\ntechnology wrapper primitives to be present under `hw/foundry/syn/dc`\nand `hw/foundry/ip/prim_\u003ctech id\u003e/`\n\nThe integration into the dvsim dashboard (analogous to AscentLint) is in\nthe making and will follow in a subsequent PR (together with more\ndocumentation).\n\nSigned-off-by: Michael Schaffner \u003cmsf@opentitan.org\u003e\n",
  "tree_diff": [
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