diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 3960515..5a889ea 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -6890,1092 +6890,6 @@
       ]
     }
   ]
-  interrupt_module:
-  [
-    uart0
-    uart1
-    uart2
-    uart3
-    gpio
-    spi_device
-    i2c0
-    i2c1
-    i2c2
-    pattgen
-    flash_ctrl
-    hmac
-    alert_handler
-    usbdev
-    pwrmgr_aon
-    otbn
-    keymgr
-    kmac
-    otp_ctrl
-    csrng
-    edn0
-    edn1
-    aon_timer_aon
-    entropy_src
-  ]
-  interrupt:
-  [
-    {
-      name: uart0_tx_watermark
-      width: 1
-      type: interrupt
-      module_name: uart0
-    }
-    {
-      name: uart0_rx_watermark
-      width: 1
-      type: interrupt
-      module_name: uart0
-    }
-    {
-      name: uart0_tx_empty
-      width: 1
-      type: interrupt
-      module_name: uart0
-    }
-    {
-      name: uart0_rx_overflow
-      width: 1
-      type: interrupt
-      module_name: uart0
-    }
-    {
-      name: uart0_rx_frame_err
-      width: 1
-      type: interrupt
-      module_name: uart0
-    }
-    {
-      name: uart0_rx_break_err
-      width: 1
-      type: interrupt
-      module_name: uart0
-    }
-    {
-      name: uart0_rx_timeout
-      width: 1
-      type: interrupt
-      module_name: uart0
-    }
-    {
-      name: uart0_rx_parity_err
-      width: 1
-      type: interrupt
-      module_name: uart0
-    }
-    {
-      name: uart1_tx_watermark
-      width: 1
-      type: interrupt
-      module_name: uart1
-    }
-    {
-      name: uart1_rx_watermark
-      width: 1
-      type: interrupt
-      module_name: uart1
-    }
-    {
-      name: uart1_tx_empty
-      width: 1
-      type: interrupt
-      module_name: uart1
-    }
-    {
-      name: uart1_rx_overflow
-      width: 1
-      type: interrupt
-      module_name: uart1
-    }
-    {
-      name: uart1_rx_frame_err
-      width: 1
-      type: interrupt
-      module_name: uart1
-    }
-    {
-      name: uart1_rx_break_err
-      width: 1
-      type: interrupt
-      module_name: uart1
-    }
-    {
-      name: uart1_rx_timeout
-      width: 1
-      type: interrupt
-      module_name: uart1
-    }
-    {
-      name: uart1_rx_parity_err
-      width: 1
-      type: interrupt
-      module_name: uart1
-    }
-    {
-      name: uart2_tx_watermark
-      width: 1
-      type: interrupt
-      module_name: uart2
-    }
-    {
-      name: uart2_rx_watermark
-      width: 1
-      type: interrupt
-      module_name: uart2
-    }
-    {
-      name: uart2_tx_empty
-      width: 1
-      type: interrupt
-      module_name: uart2
-    }
-    {
-      name: uart2_rx_overflow
-      width: 1
-      type: interrupt
-      module_name: uart2
-    }
-    {
-      name: uart2_rx_frame_err
-      width: 1
-      type: interrupt
-      module_name: uart2
-    }
-    {
-      name: uart2_rx_break_err
-      width: 1
-      type: interrupt
-      module_name: uart2
-    }
-    {
-      name: uart2_rx_timeout
-      width: 1
-      type: interrupt
-      module_name: uart2
-    }
-    {
-      name: uart2_rx_parity_err
-      width: 1
-      type: interrupt
-      module_name: uart2
-    }
-    {
-      name: uart3_tx_watermark
-      width: 1
-      type: interrupt
-      module_name: uart3
-    }
-    {
-      name: uart3_rx_watermark
-      width: 1
-      type: interrupt
-      module_name: uart3
-    }
-    {
-      name: uart3_tx_empty
-      width: 1
-      type: interrupt
-      module_name: uart3
-    }
-    {
-      name: uart3_rx_overflow
-      width: 1
-      type: interrupt
-      module_name: uart3
-    }
-    {
-      name: uart3_rx_frame_err
-      width: 1
-      type: interrupt
-      module_name: uart3
-    }
-    {
-      name: uart3_rx_break_err
-      width: 1
-      type: interrupt
-      module_name: uart3
-    }
-    {
-      name: uart3_rx_timeout
-      width: 1
-      type: interrupt
-      module_name: uart3
-    }
-    {
-      name: uart3_rx_parity_err
-      width: 1
-      type: interrupt
-      module_name: uart3
-    }
-    {
-      name: gpio_gpio
-      width: 32
-      type: interrupt
-      module_name: gpio
-    }
-    {
-      name: spi_device_rxf
-      width: 1
-      type: interrupt
-      module_name: spi_device
-    }
-    {
-      name: spi_device_rxlvl
-      width: 1
-      type: interrupt
-      module_name: spi_device
-    }
-    {
-      name: spi_device_txlvl
-      width: 1
-      type: interrupt
-      module_name: spi_device
-    }
-    {
-      name: spi_device_rxerr
-      width: 1
-      type: interrupt
-      module_name: spi_device
-    }
-    {
-      name: spi_device_rxoverflow
-      width: 1
-      type: interrupt
-      module_name: spi_device
-    }
-    {
-      name: spi_device_txunderflow
-      width: 1
-      type: interrupt
-      module_name: spi_device
-    }
-    {
-      name: i2c0_fmt_watermark
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c0_rx_watermark
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c0_fmt_overflow
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c0_rx_overflow
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c0_nak
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c0_scl_interference
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c0_sda_interference
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c0_stretch_timeout
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c0_sda_unstable
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c0_trans_complete
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c0_tx_empty
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c0_tx_nonempty
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c0_tx_overflow
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c0_acq_overflow
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c0_ack_stop
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c0_host_timeout
-      width: 1
-      type: interrupt
-      module_name: i2c0
-    }
-    {
-      name: i2c1_fmt_watermark
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c1_rx_watermark
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c1_fmt_overflow
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c1_rx_overflow
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c1_nak
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c1_scl_interference
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c1_sda_interference
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c1_stretch_timeout
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c1_sda_unstable
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c1_trans_complete
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c1_tx_empty
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c1_tx_nonempty
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c1_tx_overflow
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c1_acq_overflow
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c1_ack_stop
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c1_host_timeout
-      width: 1
-      type: interrupt
-      module_name: i2c1
-    }
-    {
-      name: i2c2_fmt_watermark
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: i2c2_rx_watermark
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: i2c2_fmt_overflow
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: i2c2_rx_overflow
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: i2c2_nak
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: i2c2_scl_interference
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: i2c2_sda_interference
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: i2c2_stretch_timeout
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: i2c2_sda_unstable
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: i2c2_trans_complete
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: i2c2_tx_empty
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: i2c2_tx_nonempty
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: i2c2_tx_overflow
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: i2c2_acq_overflow
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: i2c2_ack_stop
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: i2c2_host_timeout
-      width: 1
-      type: interrupt
-      module_name: i2c2
-    }
-    {
-      name: pattgen_done_ch0
-      width: 1
-      type: interrupt
-      module_name: pattgen
-    }
-    {
-      name: pattgen_done_ch1
-      width: 1
-      type: interrupt
-      module_name: pattgen
-    }
-    {
-      name: flash_ctrl_prog_empty
-      width: 1
-      type: interrupt
-      module_name: flash_ctrl
-    }
-    {
-      name: flash_ctrl_prog_lvl
-      width: 1
-      type: interrupt
-      module_name: flash_ctrl
-    }
-    {
-      name: flash_ctrl_rd_full
-      width: 1
-      type: interrupt
-      module_name: flash_ctrl
-    }
-    {
-      name: flash_ctrl_rd_lvl
-      width: 1
-      type: interrupt
-      module_name: flash_ctrl
-    }
-    {
-      name: flash_ctrl_op_done
-      width: 1
-      type: interrupt
-      module_name: flash_ctrl
-    }
-    {
-      name: hmac_hmac_done
-      width: 1
-      type: interrupt
-      module_name: hmac
-    }
-    {
-      name: hmac_fifo_empty
-      width: 1
-      type: interrupt
-      module_name: hmac
-    }
-    {
-      name: hmac_hmac_err
-      width: 1
-      type: interrupt
-      module_name: hmac
-    }
-    {
-      name: alert_handler_classa
-      width: 1
-      type: interrupt
-      module_name: alert_handler
-    }
-    {
-      name: alert_handler_classb
-      width: 1
-      type: interrupt
-      module_name: alert_handler
-    }
-    {
-      name: alert_handler_classc
-      width: 1
-      type: interrupt
-      module_name: alert_handler
-    }
-    {
-      name: alert_handler_classd
-      width: 1
-      type: interrupt
-      module_name: alert_handler
-    }
-    {
-      name: usbdev_pkt_received
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_pkt_sent
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_disconnected
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_host_lost
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_link_reset
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_link_suspend
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_link_resume
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_av_empty
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_rx_full
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_av_overflow
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_link_in_err
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_rx_crc_err
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_rx_pid_err
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_rx_bitstuff_err
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_frame
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_connected
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: usbdev_link_out_err
-      width: 1
-      type: interrupt
-      module_name: usbdev
-    }
-    {
-      name: pwrmgr_aon_wakeup
-      width: 1
-      type: interrupt
-      module_name: pwrmgr_aon
-    }
-    {
-      name: otbn_done
-      width: 1
-      type: interrupt
-      module_name: otbn
-    }
-    {
-      name: keymgr_op_done
-      width: 1
-      type: interrupt
-      module_name: keymgr
-    }
-    {
-      name: kmac_kmac_done
-      width: 1
-      type: interrupt
-      module_name: kmac
-    }
-    {
-      name: kmac_fifo_empty
-      width: 1
-      type: interrupt
-      module_name: kmac
-    }
-    {
-      name: kmac_kmac_err
-      width: 1
-      type: interrupt
-      module_name: kmac
-    }
-    {
-      name: otp_ctrl_otp_operation_done
-      width: 1
-      type: interrupt
-      module_name: otp_ctrl
-    }
-    {
-      name: otp_ctrl_otp_error
-      width: 1
-      type: interrupt
-      module_name: otp_ctrl
-    }
-    {
-      name: csrng_cs_cmd_req_done
-      width: 1
-      type: interrupt
-      module_name: csrng
-    }
-    {
-      name: csrng_cs_entropy_req
-      width: 1
-      type: interrupt
-      module_name: csrng
-    }
-    {
-      name: csrng_cs_hw_inst_exc
-      width: 1
-      type: interrupt
-      module_name: csrng
-    }
-    {
-      name: csrng_cs_fatal_err
-      width: 1
-      type: interrupt
-      module_name: csrng
-    }
-    {
-      name: edn0_edn_cmd_req_done
-      width: 1
-      type: interrupt
-      module_name: edn0
-    }
-    {
-      name: edn0_edn_fatal_err
-      width: 1
-      type: interrupt
-      module_name: edn0
-    }
-    {
-      name: edn1_edn_cmd_req_done
-      width: 1
-      type: interrupt
-      module_name: edn1
-    }
-    {
-      name: edn1_edn_fatal_err
-      width: 1
-      type: interrupt
-      module_name: edn1
-    }
-    {
-      name: aon_timer_aon_wkup_timer_expired
-      width: 1
-      type: interrupt
-      module_name: aon_timer_aon
-    }
-    {
-      name: aon_timer_aon_wdog_timer_bark
-      width: 1
-      type: interrupt
-      module_name: aon_timer_aon
-    }
-    {
-      name: entropy_src_es_entropy_valid
-      width: 1
-      type: interrupt
-      module_name: entropy_src
-    }
-    {
-      name: entropy_src_es_health_test_failed
-      width: 1
-      type: interrupt
-      module_name: entropy_src
-    }
-    {
-      name: entropy_src_es_fatal_err
-      width: 1
-      type: interrupt
-      module_name: entropy_src
-    }
-  ]
-  alert_module:
-  [
-    aes
-    otbn
-    sensor_ctrl_aon
-    keymgr
-    otp_ctrl
-    lc_ctrl
-    entropy_src
-    csrng
-    edn0
-    edn1
-    sram_ctrl_main
-    sram_ctrl_ret_aon
-    flash_ctrl
-  ]
-  alert:
-  [
-    {
-      name: aes_recov_ctrl_update_err
-      width: 1
-      type: alert
-      async: "1"
-      module_name: aes
-    }
-    {
-      name: aes_fatal_fault
-      width: 1
-      type: alert
-      async: "1"
-      module_name: aes
-    }
-    {
-      name: otbn_fatal
-      width: 1
-      type: alert
-      async: "1"
-      module_name: otbn
-    }
-    {
-      name: otbn_recov
-      width: 1
-      type: alert
-      async: "1"
-      module_name: otbn
-    }
-    {
-      name: sensor_ctrl_aon_recov_as
-      width: 1
-      type: alert
-      async: "0"
-      module_name: sensor_ctrl_aon
-    }
-    {
-      name: sensor_ctrl_aon_recov_cg
-      width: 1
-      type: alert
-      async: "0"
-      module_name: sensor_ctrl_aon
-    }
-    {
-      name: sensor_ctrl_aon_recov_gd
-      width: 1
-      type: alert
-      async: "0"
-      module_name: sensor_ctrl_aon
-    }
-    {
-      name: sensor_ctrl_aon_recov_ts_hi
-      width: 1
-      type: alert
-      async: "0"
-      module_name: sensor_ctrl_aon
-    }
-    {
-      name: sensor_ctrl_aon_recov_ts_lo
-      width: 1
-      type: alert
-      async: "0"
-      module_name: sensor_ctrl_aon
-    }
-    {
-      name: sensor_ctrl_aon_recov_ls
-      width: 1
-      type: alert
-      async: "0"
-      module_name: sensor_ctrl_aon
-    }
-    {
-      name: sensor_ctrl_aon_recov_ot
-      width: 1
-      type: alert
-      async: "0"
-      module_name: sensor_ctrl_aon
-    }
-    {
-      name: keymgr_fatal_fault_err
-      width: 1
-      type: alert
-      async: "1"
-      module_name: keymgr
-    }
-    {
-      name: keymgr_recov_operation_err
-      width: 1
-      type: alert
-      async: "1"
-      module_name: keymgr
-    }
-    {
-      name: otp_ctrl_fatal_macro_error
-      width: 1
-      type: alert
-      async: "0"
-      module_name: otp_ctrl
-    }
-    {
-      name: otp_ctrl_fatal_check_error
-      width: 1
-      type: alert
-      async: "0"
-      module_name: otp_ctrl
-    }
-    {
-      name: lc_ctrl_fatal_prog_error
-      width: 1
-      type: alert
-      async: "0"
-      module_name: lc_ctrl
-    }
-    {
-      name: lc_ctrl_fatal_state_error
-      width: 1
-      type: alert
-      async: "0"
-      module_name: lc_ctrl
-    }
-    {
-      name: entropy_src_recov_alert
-      width: 1
-      type: alert
-      async: "1"
-      module_name: entropy_src
-    }
-    {
-      name: entropy_src_fatal_alert
-      width: 1
-      type: alert
-      async: "1"
-      module_name: entropy_src
-    }
-    {
-      name: csrng_fatal_alert
-      width: 1
-      type: alert
-      async: "1"
-      module_name: csrng
-    }
-    {
-      name: edn0_fatal_alert
-      width: 1
-      type: alert
-      async: "1"
-      module_name: edn0
-    }
-    {
-      name: edn1_fatal_alert
-      width: 1
-      type: alert
-      async: "1"
-      module_name: edn1
-    }
-    {
-      name: sram_ctrl_main_fatal_intg_error
-      width: 1
-      type: alert
-      async: "1"
-      module_name: sram_ctrl_main
-    }
-    {
-      name: sram_ctrl_main_fatal_parity_error
-      width: 1
-      type: alert
-      async: "1"
-      module_name: sram_ctrl_main
-    }
-    {
-      name: sram_ctrl_ret_aon_fatal_intg_error
-      width: 1
-      type: alert
-      async: "0"
-      module_name: sram_ctrl_ret_aon
-    }
-    {
-      name: sram_ctrl_ret_aon_fatal_parity_error
-      width: 1
-      type: alert
-      async: "0"
-      module_name: sram_ctrl_ret_aon
-    }
-    {
-      name: flash_ctrl_recov_err
-      width: 1
-      type: alert
-      async: "1"
-      module_name: flash_ctrl
-    }
-    {
-      name: flash_ctrl_recov_mp_err
-      width: 1
-      type: alert
-      async: "1"
-      module_name: flash_ctrl
-    }
-    {
-      name: flash_ctrl_recov_ecc_err
-      width: 1
-      type: alert
-      async: "1"
-      module_name: flash_ctrl
-    }
-  ]
   pinmux:
   {
     num_mio: 44
@@ -8546,6 +7460,1125 @@
       module: aon_timer_aon
     }
   ]
+  interrupt_module:
+  [
+    uart0
+    uart1
+    uart2
+    uart3
+    gpio
+    spi_device
+    spi_host0
+    spi_host1
+    i2c0
+    i2c1
+    i2c2
+    pattgen
+    rv_timer
+    usbdev
+    otp_ctrl
+    alert_handler
+    pwrmgr_aon
+    aon_timer_aon
+    flash_ctrl
+    hmac
+    kmac
+    keymgr
+    csrng
+    entropy_src
+    edn0
+    edn1
+    otbn
+  ]
+  interrupt:
+  [
+    {
+      name: uart0_tx_watermark
+      width: 1
+      type: interrupt
+      module_name: uart0
+    }
+    {
+      name: uart0_rx_watermark
+      width: 1
+      type: interrupt
+      module_name: uart0
+    }
+    {
+      name: uart0_tx_empty
+      width: 1
+      type: interrupt
+      module_name: uart0
+    }
+    {
+      name: uart0_rx_overflow
+      width: 1
+      type: interrupt
+      module_name: uart0
+    }
+    {
+      name: uart0_rx_frame_err
+      width: 1
+      type: interrupt
+      module_name: uart0
+    }
+    {
+      name: uart0_rx_break_err
+      width: 1
+      type: interrupt
+      module_name: uart0
+    }
+    {
+      name: uart0_rx_timeout
+      width: 1
+      type: interrupt
+      module_name: uart0
+    }
+    {
+      name: uart0_rx_parity_err
+      width: 1
+      type: interrupt
+      module_name: uart0
+    }
+    {
+      name: uart1_tx_watermark
+      width: 1
+      type: interrupt
+      module_name: uart1
+    }
+    {
+      name: uart1_rx_watermark
+      width: 1
+      type: interrupt
+      module_name: uart1
+    }
+    {
+      name: uart1_tx_empty
+      width: 1
+      type: interrupt
+      module_name: uart1
+    }
+    {
+      name: uart1_rx_overflow
+      width: 1
+      type: interrupt
+      module_name: uart1
+    }
+    {
+      name: uart1_rx_frame_err
+      width: 1
+      type: interrupt
+      module_name: uart1
+    }
+    {
+      name: uart1_rx_break_err
+      width: 1
+      type: interrupt
+      module_name: uart1
+    }
+    {
+      name: uart1_rx_timeout
+      width: 1
+      type: interrupt
+      module_name: uart1
+    }
+    {
+      name: uart1_rx_parity_err
+      width: 1
+      type: interrupt
+      module_name: uart1
+    }
+    {
+      name: uart2_tx_watermark
+      width: 1
+      type: interrupt
+      module_name: uart2
+    }
+    {
+      name: uart2_rx_watermark
+      width: 1
+      type: interrupt
+      module_name: uart2
+    }
+    {
+      name: uart2_tx_empty
+      width: 1
+      type: interrupt
+      module_name: uart2
+    }
+    {
+      name: uart2_rx_overflow
+      width: 1
+      type: interrupt
+      module_name: uart2
+    }
+    {
+      name: uart2_rx_frame_err
+      width: 1
+      type: interrupt
+      module_name: uart2
+    }
+    {
+      name: uart2_rx_break_err
+      width: 1
+      type: interrupt
+      module_name: uart2
+    }
+    {
+      name: uart2_rx_timeout
+      width: 1
+      type: interrupt
+      module_name: uart2
+    }
+    {
+      name: uart2_rx_parity_err
+      width: 1
+      type: interrupt
+      module_name: uart2
+    }
+    {
+      name: uart3_tx_watermark
+      width: 1
+      type: interrupt
+      module_name: uart3
+    }
+    {
+      name: uart3_rx_watermark
+      width: 1
+      type: interrupt
+      module_name: uart3
+    }
+    {
+      name: uart3_tx_empty
+      width: 1
+      type: interrupt
+      module_name: uart3
+    }
+    {
+      name: uart3_rx_overflow
+      width: 1
+      type: interrupt
+      module_name: uart3
+    }
+    {
+      name: uart3_rx_frame_err
+      width: 1
+      type: interrupt
+      module_name: uart3
+    }
+    {
+      name: uart3_rx_break_err
+      width: 1
+      type: interrupt
+      module_name: uart3
+    }
+    {
+      name: uart3_rx_timeout
+      width: 1
+      type: interrupt
+      module_name: uart3
+    }
+    {
+      name: uart3_rx_parity_err
+      width: 1
+      type: interrupt
+      module_name: uart3
+    }
+    {
+      name: gpio_gpio
+      width: 32
+      type: interrupt
+      module_name: gpio
+    }
+    {
+      name: spi_device_rxf
+      width: 1
+      type: interrupt
+      module_name: spi_device
+    }
+    {
+      name: spi_device_rxlvl
+      width: 1
+      type: interrupt
+      module_name: spi_device
+    }
+    {
+      name: spi_device_txlvl
+      width: 1
+      type: interrupt
+      module_name: spi_device
+    }
+    {
+      name: spi_device_rxerr
+      width: 1
+      type: interrupt
+      module_name: spi_device
+    }
+    {
+      name: spi_device_rxoverflow
+      width: 1
+      type: interrupt
+      module_name: spi_device
+    }
+    {
+      name: spi_device_txunderflow
+      width: 1
+      type: interrupt
+      module_name: spi_device
+    }
+    {
+      name: spi_host0_error
+      width: 1
+      type: interrupt
+      module_name: spi_host0
+    }
+    {
+      name: spi_host0_spi_event
+      width: 1
+      type: interrupt
+      module_name: spi_host0
+    }
+    {
+      name: spi_host1_error
+      width: 1
+      type: interrupt
+      module_name: spi_host1
+    }
+    {
+      name: spi_host1_spi_event
+      width: 1
+      type: interrupt
+      module_name: spi_host1
+    }
+    {
+      name: i2c0_fmt_watermark
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c0_rx_watermark
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c0_fmt_overflow
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c0_rx_overflow
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c0_nak
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c0_scl_interference
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c0_sda_interference
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c0_stretch_timeout
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c0_sda_unstable
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c0_trans_complete
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c0_tx_empty
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c0_tx_nonempty
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c0_tx_overflow
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c0_acq_overflow
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c0_ack_stop
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c0_host_timeout
+      width: 1
+      type: interrupt
+      module_name: i2c0
+    }
+    {
+      name: i2c1_fmt_watermark
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c1_rx_watermark
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c1_fmt_overflow
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c1_rx_overflow
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c1_nak
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c1_scl_interference
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c1_sda_interference
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c1_stretch_timeout
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c1_sda_unstable
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c1_trans_complete
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c1_tx_empty
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c1_tx_nonempty
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c1_tx_overflow
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c1_acq_overflow
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c1_ack_stop
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c1_host_timeout
+      width: 1
+      type: interrupt
+      module_name: i2c1
+    }
+    {
+      name: i2c2_fmt_watermark
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: i2c2_rx_watermark
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: i2c2_fmt_overflow
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: i2c2_rx_overflow
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: i2c2_nak
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: i2c2_scl_interference
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: i2c2_sda_interference
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: i2c2_stretch_timeout
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: i2c2_sda_unstable
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: i2c2_trans_complete
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: i2c2_tx_empty
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: i2c2_tx_nonempty
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: i2c2_tx_overflow
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: i2c2_acq_overflow
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: i2c2_ack_stop
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: i2c2_host_timeout
+      width: 1
+      type: interrupt
+      module_name: i2c2
+    }
+    {
+      name: pattgen_done_ch0
+      width: 1
+      type: interrupt
+      module_name: pattgen
+    }
+    {
+      name: pattgen_done_ch1
+      width: 1
+      type: interrupt
+      module_name: pattgen
+    }
+    {
+      name: rv_timer_timer_expired_0_0
+      width: 1
+      type: interrupt
+      module_name: rv_timer
+    }
+    {
+      name: usbdev_pkt_received
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_pkt_sent
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_disconnected
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_host_lost
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_link_reset
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_link_suspend
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_link_resume
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_av_empty
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_rx_full
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_av_overflow
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_link_in_err
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_rx_crc_err
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_rx_pid_err
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_rx_bitstuff_err
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_frame
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_connected
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: usbdev_link_out_err
+      width: 1
+      type: interrupt
+      module_name: usbdev
+    }
+    {
+      name: otp_ctrl_otp_operation_done
+      width: 1
+      type: interrupt
+      module_name: otp_ctrl
+    }
+    {
+      name: otp_ctrl_otp_error
+      width: 1
+      type: interrupt
+      module_name: otp_ctrl
+    }
+    {
+      name: alert_handler_classa
+      width: 1
+      type: interrupt
+      module_name: alert_handler
+    }
+    {
+      name: alert_handler_classb
+      width: 1
+      type: interrupt
+      module_name: alert_handler
+    }
+    {
+      name: alert_handler_classc
+      width: 1
+      type: interrupt
+      module_name: alert_handler
+    }
+    {
+      name: alert_handler_classd
+      width: 1
+      type: interrupt
+      module_name: alert_handler
+    }
+    {
+      name: pwrmgr_aon_wakeup
+      width: 1
+      type: interrupt
+      module_name: pwrmgr_aon
+    }
+    {
+      name: aon_timer_aon_wkup_timer_expired
+      width: 1
+      type: interrupt
+      module_name: aon_timer_aon
+    }
+    {
+      name: aon_timer_aon_wdog_timer_bark
+      width: 1
+      type: interrupt
+      module_name: aon_timer_aon
+    }
+    {
+      name: flash_ctrl_prog_empty
+      width: 1
+      type: interrupt
+      module_name: flash_ctrl
+    }
+    {
+      name: flash_ctrl_prog_lvl
+      width: 1
+      type: interrupt
+      module_name: flash_ctrl
+    }
+    {
+      name: flash_ctrl_rd_full
+      width: 1
+      type: interrupt
+      module_name: flash_ctrl
+    }
+    {
+      name: flash_ctrl_rd_lvl
+      width: 1
+      type: interrupt
+      module_name: flash_ctrl
+    }
+    {
+      name: flash_ctrl_op_done
+      width: 1
+      type: interrupt
+      module_name: flash_ctrl
+    }
+    {
+      name: hmac_hmac_done
+      width: 1
+      type: interrupt
+      module_name: hmac
+    }
+    {
+      name: hmac_fifo_empty
+      width: 1
+      type: interrupt
+      module_name: hmac
+    }
+    {
+      name: hmac_hmac_err
+      width: 1
+      type: interrupt
+      module_name: hmac
+    }
+    {
+      name: kmac_kmac_done
+      width: 1
+      type: interrupt
+      module_name: kmac
+    }
+    {
+      name: kmac_fifo_empty
+      width: 1
+      type: interrupt
+      module_name: kmac
+    }
+    {
+      name: kmac_kmac_err
+      width: 1
+      type: interrupt
+      module_name: kmac
+    }
+    {
+      name: keymgr_op_done
+      width: 1
+      type: interrupt
+      module_name: keymgr
+    }
+    {
+      name: csrng_cs_cmd_req_done
+      width: 1
+      type: interrupt
+      module_name: csrng
+    }
+    {
+      name: csrng_cs_entropy_req
+      width: 1
+      type: interrupt
+      module_name: csrng
+    }
+    {
+      name: csrng_cs_hw_inst_exc
+      width: 1
+      type: interrupt
+      module_name: csrng
+    }
+    {
+      name: csrng_cs_fatal_err
+      width: 1
+      type: interrupt
+      module_name: csrng
+    }
+    {
+      name: entropy_src_es_entropy_valid
+      width: 1
+      type: interrupt
+      module_name: entropy_src
+    }
+    {
+      name: entropy_src_es_health_test_failed
+      width: 1
+      type: interrupt
+      module_name: entropy_src
+    }
+    {
+      name: entropy_src_es_fatal_err
+      width: 1
+      type: interrupt
+      module_name: entropy_src
+    }
+    {
+      name: edn0_edn_cmd_req_done
+      width: 1
+      type: interrupt
+      module_name: edn0
+    }
+    {
+      name: edn0_edn_fatal_err
+      width: 1
+      type: interrupt
+      module_name: edn0
+    }
+    {
+      name: edn1_edn_cmd_req_done
+      width: 1
+      type: interrupt
+      module_name: edn1
+    }
+    {
+      name: edn1_edn_fatal_err
+      width: 1
+      type: interrupt
+      module_name: edn1
+    }
+    {
+      name: otbn_done
+      width: 1
+      type: interrupt
+      module_name: otbn
+    }
+  ]
+  alert_module:
+  [
+    otp_ctrl
+    lc_ctrl
+    sensor_ctrl_aon
+    sram_ctrl_ret_aon
+    flash_ctrl
+    aes
+    keymgr
+    csrng
+    entropy_src
+    edn0
+    edn1
+    sram_ctrl_main
+    otbn
+  ]
+  alert:
+  [
+    {
+      name: otp_ctrl_fatal_macro_error
+      width: 1
+      type: alert
+      async: "0"
+      module_name: otp_ctrl
+    }
+    {
+      name: otp_ctrl_fatal_check_error
+      width: 1
+      type: alert
+      async: "0"
+      module_name: otp_ctrl
+    }
+    {
+      name: lc_ctrl_fatal_prog_error
+      width: 1
+      type: alert
+      async: "0"
+      module_name: lc_ctrl
+    }
+    {
+      name: lc_ctrl_fatal_state_error
+      width: 1
+      type: alert
+      async: "0"
+      module_name: lc_ctrl
+    }
+    {
+      name: sensor_ctrl_aon_recov_as
+      width: 1
+      type: alert
+      async: "0"
+      module_name: sensor_ctrl_aon
+    }
+    {
+      name: sensor_ctrl_aon_recov_cg
+      width: 1
+      type: alert
+      async: "0"
+      module_name: sensor_ctrl_aon
+    }
+    {
+      name: sensor_ctrl_aon_recov_gd
+      width: 1
+      type: alert
+      async: "0"
+      module_name: sensor_ctrl_aon
+    }
+    {
+      name: sensor_ctrl_aon_recov_ts_hi
+      width: 1
+      type: alert
+      async: "0"
+      module_name: sensor_ctrl_aon
+    }
+    {
+      name: sensor_ctrl_aon_recov_ts_lo
+      width: 1
+      type: alert
+      async: "0"
+      module_name: sensor_ctrl_aon
+    }
+    {
+      name: sensor_ctrl_aon_recov_ls
+      width: 1
+      type: alert
+      async: "0"
+      module_name: sensor_ctrl_aon
+    }
+    {
+      name: sensor_ctrl_aon_recov_ot
+      width: 1
+      type: alert
+      async: "0"
+      module_name: sensor_ctrl_aon
+    }
+    {
+      name: sram_ctrl_ret_aon_fatal_intg_error
+      width: 1
+      type: alert
+      async: "0"
+      module_name: sram_ctrl_ret_aon
+    }
+    {
+      name: sram_ctrl_ret_aon_fatal_parity_error
+      width: 1
+      type: alert
+      async: "0"
+      module_name: sram_ctrl_ret_aon
+    }
+    {
+      name: flash_ctrl_recov_err
+      width: 1
+      type: alert
+      async: "1"
+      module_name: flash_ctrl
+    }
+    {
+      name: flash_ctrl_recov_mp_err
+      width: 1
+      type: alert
+      async: "1"
+      module_name: flash_ctrl
+    }
+    {
+      name: flash_ctrl_recov_ecc_err
+      width: 1
+      type: alert
+      async: "1"
+      module_name: flash_ctrl
+    }
+    {
+      name: aes_recov_ctrl_update_err
+      width: 1
+      type: alert
+      async: "1"
+      module_name: aes
+    }
+    {
+      name: aes_fatal_fault
+      width: 1
+      type: alert
+      async: "1"
+      module_name: aes
+    }
+    {
+      name: keymgr_fatal_fault_err
+      width: 1
+      type: alert
+      async: "1"
+      module_name: keymgr
+    }
+    {
+      name: keymgr_recov_operation_err
+      width: 1
+      type: alert
+      async: "1"
+      module_name: keymgr
+    }
+    {
+      name: csrng_fatal_alert
+      width: 1
+      type: alert
+      async: "1"
+      module_name: csrng
+    }
+    {
+      name: entropy_src_recov_alert
+      width: 1
+      type: alert
+      async: "1"
+      module_name: entropy_src
+    }
+    {
+      name: entropy_src_fatal_alert
+      width: 1
+      type: alert
+      async: "1"
+      module_name: entropy_src
+    }
+    {
+      name: edn0_fatal_alert
+      width: 1
+      type: alert
+      async: "1"
+      module_name: edn0
+    }
+    {
+      name: edn1_fatal_alert
+      width: 1
+      type: alert
+      async: "1"
+      module_name: edn1
+    }
+    {
+      name: sram_ctrl_main_fatal_intg_error
+      width: 1
+      type: alert
+      async: "1"
+      module_name: sram_ctrl_main
+    }
+    {
+      name: sram_ctrl_main_fatal_parity_error
+      width: 1
+      type: alert
+      async: "1"
+      module_name: sram_ctrl_main
+    }
+    {
+      name: otbn_fatal
+      width: 1
+      type: alert
+      async: "1"
+      module_name: otbn
+    }
+    {
+      name: otbn_recov
+      width: 1
+      type: alert
+      async: "1"
+      module_name: otbn
+    }
+  ]
   exported_rsts:
   {
     ast:
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 8d04ace..318da36 100755
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -914,34 +914,11 @@
   ],
 
   // ===== INTERRUPT CTRL =====================================================
-  // `rv_plic`  will be instantiate (need to be defined in `module` field
-  // If interrupt is not defined, it uses the order from the module list
-  // and include every modules.
-  // first item goes to LSB of the interrupt source
-  interrupt_module: ["uart0", "uart1", "uart2", "uart3",
-                     "gpio", "spi_device", "i2c0", "i2c1", "i2c2", "pattgen",
-                     "flash_ctrl", "hmac", "alert_handler", "usbdev", "pwrmgr_aon",
-                     "otbn", "keymgr", "kmac", "otp_ctrl", "csrng", "edn0", "edn1",
-                     "aon_timer_aon", "entropy_src"]
-
   // RV_PLIC has two searching algorithm internally to pick the most highest priority interrupt
   // source. "sequential" is smaller but slower, "matrix" is larger but faster.
   // Choose depends on the criteria. Currently it is set to "matrix" to meet FPGA timing @ 50MHz
 
-  // generated:
-  interrupt: [
-  ]
-
   // ===== ALERT HANDLER ======================================================
-  // list all modules that expose alerts
-  // first item goes to LSB of the alert source
-  alert_module: [ "aes", "otbn", "sensor_ctrl_aon", "keymgr", "otp_ctrl", "lc_ctrl",
-                  "entropy_src","csrng", "edn0", "edn1",
-                  "sram_ctrl_main", "sram_ctrl_ret_aon", "flash_ctrl"]
-
-  // generated list of alerts:
-  alert: [
-  ]
 
   // TODO: need to overhaul this datastructure.
   pinmux: {
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
index 3ac7dd2..930538a 100644
--- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -4,10 +4,10 @@
 //
 // tb__alert_handler_connect.sv is auto-generated by `topgen.py` tool
 
-assign alert_if[0].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
-assign alert_if[1].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
-assign alert_if[2].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
-assign alert_if[3].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
+assign alert_if[0].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0];
+assign alert_if[1].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1];
+assign alert_if[2].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0];
+assign alert_if[3].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
 assign alert_if[4].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0];
 assign alert_if[5].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1];
 assign alert_if[6].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[2];
@@ -15,21 +15,21 @@
 assign alert_if[8].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[4];
 assign alert_if[9].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[5];
 assign alert_if[10].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[6];
-assign alert_if[11].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
-assign alert_if[12].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
-assign alert_if[13].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0];
-assign alert_if[14].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1];
-assign alert_if[15].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0];
-assign alert_if[16].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
-assign alert_if[17].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
-assign alert_if[18].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
-assign alert_if[19].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
-assign alert_if[20].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
-assign alert_if[21].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
-assign alert_if[22].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
-assign alert_if[23].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1];
-assign alert_if[24].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
-assign alert_if[25].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1];
-assign alert_if[26].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
-assign alert_if[27].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
-assign alert_if[28].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
+assign alert_if[11].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
+assign alert_if[12].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1];
+assign alert_if[13].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
+assign alert_if[14].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
+assign alert_if[15].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
+assign alert_if[16].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
+assign alert_if[17].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
+assign alert_if[18].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
+assign alert_if[19].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
+assign alert_if[20].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
+assign alert_if[21].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
+assign alert_if[22].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
+assign alert_if[23].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
+assign alert_if[24].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
+assign alert_if[25].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
+assign alert_if[26].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1];
+assign alert_if[27].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
+assign alert_if[28].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
index da53ed4..a99f290 100644
--- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
@@ -5,10 +5,10 @@
 // Generated by topgen.py
 
 parameter string LIST_OF_ALERTS[] = {
-  "aes_recov_ctrl_update_err",
-  "aes_fatal_fault",
-  "otbn_fatal",
-  "otbn_recov",
+  "otp_ctrl_fatal_macro_error",
+  "otp_ctrl_fatal_check_error",
+  "lc_ctrl_fatal_prog_error",
+  "lc_ctrl_fatal_state_error",
   "sensor_ctrl_aon_recov_as",
   "sensor_ctrl_aon_recov_cg",
   "sensor_ctrl_aon_recov_gd",
@@ -16,24 +16,24 @@
   "sensor_ctrl_aon_recov_ts_lo",
   "sensor_ctrl_aon_recov_ls",
   "sensor_ctrl_aon_recov_ot",
-  "keymgr_fatal_fault_err",
-  "keymgr_recov_operation_err",
-  "otp_ctrl_fatal_macro_error",
-  "otp_ctrl_fatal_check_error",
-  "lc_ctrl_fatal_prog_error",
-  "lc_ctrl_fatal_state_error",
-  "entropy_src_recov_alert",
-  "entropy_src_fatal_alert",
-  "csrng_fatal_alert",
-  "edn0_fatal_alert",
-  "edn1_fatal_alert",
-  "sram_ctrl_main_fatal_intg_error",
-  "sram_ctrl_main_fatal_parity_error",
   "sram_ctrl_ret_aon_fatal_intg_error",
   "sram_ctrl_ret_aon_fatal_parity_error",
   "flash_ctrl_recov_err",
   "flash_ctrl_recov_mp_err",
-  "flash_ctrl_recov_ecc_err"
+  "flash_ctrl_recov_ecc_err",
+  "aes_recov_ctrl_update_err",
+  "aes_fatal_fault",
+  "keymgr_fatal_fault_err",
+  "keymgr_recov_operation_err",
+  "csrng_fatal_alert",
+  "entropy_src_recov_alert",
+  "entropy_src_fatal_alert",
+  "edn0_fatal_alert",
+  "edn1_fatal_alert",
+  "sram_ctrl_main_fatal_intg_error",
+  "sram_ctrl_main_fatal_parity_error",
+  "otbn_fatal",
+  "otbn_recov"
 };
 
 parameter uint NUM_ALERTS = 29;
diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
index 4b44781..fe1c08c 100644
--- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
+++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
@@ -64,7 +64,7 @@
     { name: "AsyncOn",
       desc: "Number of peripheral outputs",
       type: "logic [NAlerts-1:0]",
-      default: "29'b11100111111100001100000001111",
+      default: "29'b11111111111111110000000000000",
       local: "true"
     },
     { name: "N_CLASSES",
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
index df3fff3..f544a9b 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
@@ -10,7 +10,7 @@
   parameter int NAlerts = 29;
   parameter int EscCntDw = 32;
   parameter int AccuCntDw = 16;
-  parameter logic [NAlerts-1:0] AsyncOn = 29'b11100111111100001100000001111;
+  parameter logic [NAlerts-1:0] AsyncOn = 29'b11111111111111110000000000000;
   parameter int N_CLASSES = 4;
   parameter int N_ESC_SEV = 4;
   parameter int N_PHASES = 4;
diff --git a/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson b/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
index 966e0d7..257cef0 100644
--- a/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
+++ b/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
@@ -25,7 +25,7 @@
     { name: "NumSrc",
       desc: "Number of interrupt sources",
       type: "int",
-      default: "171",
+      default: "176",
       local: "true"
     },
     { name: "NumTarget",
@@ -1437,6 +1437,46 @@
         { bits: "1:0" }
       ],
     }
+    { name: "PRIO171",
+      desc: "Interrupt Source 171 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+    { name: "PRIO172",
+      desc: "Interrupt Source 172 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+    { name: "PRIO173",
+      desc: "Interrupt Source 173 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+    { name: "PRIO174",
+      desc: "Interrupt Source 174 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
+    { name: "PRIO175",
+      desc: "Interrupt Source 175 Priority",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "1:0" }
+      ],
+    }
     { skipto: "768" }
     { multireg: {
         name: "IE0",
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
index 0d15c40..ff64702 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
@@ -265,11 +265,16 @@
   assign prio[168] = reg2hw.prio168.q;
   assign prio[169] = reg2hw.prio169.q;
   assign prio[170] = reg2hw.prio170.q;
+  assign prio[171] = reg2hw.prio171.q;
+  assign prio[172] = reg2hw.prio172.q;
+  assign prio[173] = reg2hw.prio173.q;
+  assign prio[174] = reg2hw.prio174.q;
+  assign prio[175] = reg2hw.prio175.q;
 
   //////////////////////
   // Interrupt Enable //
   //////////////////////
-  for (genvar s = 0; s < 171; s++) begin : gen_ie0
+  for (genvar s = 0; s < 176; s++) begin : gen_ie0
     assign ie[0][s] = reg2hw.ie0[s].q;
   end
 
@@ -295,7 +300,7 @@
   ////////
   // IP //
   ////////
-  for (genvar s = 0; s < 171; s++) begin : gen_ip
+  for (genvar s = 0; s < 176; s++) begin : gen_ip
     assign hw2reg.ip[s].de = 1'b1; // Always write
     assign hw2reg.ip[s].d  = ip[s];
   end
@@ -303,7 +308,7 @@
   ///////////////////////////////////
   // Detection:: 0: Level, 1: Edge //
   ///////////////////////////////////
-  for (genvar s = 0; s < 171; s++) begin : gen_le
+  for (genvar s = 0; s < 176; s++) begin : gen_le
     assign le[s] = reg2hw.le[s].q;
   end
 
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
index 326dd87..2bedb35 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
@@ -7,7 +7,7 @@
 package rv_plic_reg_pkg;
 
   // Param list
-  parameter int NumSrc = 171;
+  parameter int NumSrc = 176;
   parameter int NumTarget = 1;
   parameter int PrioWidth = 2;
 
@@ -706,6 +706,26 @@
   } rv_plic_reg2hw_prio170_reg_t;
 
   typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio171_reg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio172_reg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio173_reg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio174_reg_t;
+
+  typedef struct packed {
+    logic [1:0]  q;
+  } rv_plic_reg2hw_prio175_reg_t;
+
+  typedef struct packed {
     logic        q;
   } rv_plic_reg2hw_ie0_mreg_t;
 
@@ -738,179 +758,184 @@
   // Register to internal design logic //
   ///////////////////////////////////////
   typedef struct packed {
-    rv_plic_reg2hw_le_mreg_t [170:0] le; // [696:526]
-    rv_plic_reg2hw_prio0_reg_t prio0; // [525:524]
-    rv_plic_reg2hw_prio1_reg_t prio1; // [523:522]
-    rv_plic_reg2hw_prio2_reg_t prio2; // [521:520]
-    rv_plic_reg2hw_prio3_reg_t prio3; // [519:518]
-    rv_plic_reg2hw_prio4_reg_t prio4; // [517:516]
-    rv_plic_reg2hw_prio5_reg_t prio5; // [515:514]
-    rv_plic_reg2hw_prio6_reg_t prio6; // [513:512]
-    rv_plic_reg2hw_prio7_reg_t prio7; // [511:510]
-    rv_plic_reg2hw_prio8_reg_t prio8; // [509:508]
-    rv_plic_reg2hw_prio9_reg_t prio9; // [507:506]
-    rv_plic_reg2hw_prio10_reg_t prio10; // [505:504]
-    rv_plic_reg2hw_prio11_reg_t prio11; // [503:502]
-    rv_plic_reg2hw_prio12_reg_t prio12; // [501:500]
-    rv_plic_reg2hw_prio13_reg_t prio13; // [499:498]
-    rv_plic_reg2hw_prio14_reg_t prio14; // [497:496]
-    rv_plic_reg2hw_prio15_reg_t prio15; // [495:494]
-    rv_plic_reg2hw_prio16_reg_t prio16; // [493:492]
-    rv_plic_reg2hw_prio17_reg_t prio17; // [491:490]
-    rv_plic_reg2hw_prio18_reg_t prio18; // [489:488]
-    rv_plic_reg2hw_prio19_reg_t prio19; // [487:486]
-    rv_plic_reg2hw_prio20_reg_t prio20; // [485:484]
-    rv_plic_reg2hw_prio21_reg_t prio21; // [483:482]
-    rv_plic_reg2hw_prio22_reg_t prio22; // [481:480]
-    rv_plic_reg2hw_prio23_reg_t prio23; // [479:478]
-    rv_plic_reg2hw_prio24_reg_t prio24; // [477:476]
-    rv_plic_reg2hw_prio25_reg_t prio25; // [475:474]
-    rv_plic_reg2hw_prio26_reg_t prio26; // [473:472]
-    rv_plic_reg2hw_prio27_reg_t prio27; // [471:470]
-    rv_plic_reg2hw_prio28_reg_t prio28; // [469:468]
-    rv_plic_reg2hw_prio29_reg_t prio29; // [467:466]
-    rv_plic_reg2hw_prio30_reg_t prio30; // [465:464]
-    rv_plic_reg2hw_prio31_reg_t prio31; // [463:462]
-    rv_plic_reg2hw_prio32_reg_t prio32; // [461:460]
-    rv_plic_reg2hw_prio33_reg_t prio33; // [459:458]
-    rv_plic_reg2hw_prio34_reg_t prio34; // [457:456]
-    rv_plic_reg2hw_prio35_reg_t prio35; // [455:454]
-    rv_plic_reg2hw_prio36_reg_t prio36; // [453:452]
-    rv_plic_reg2hw_prio37_reg_t prio37; // [451:450]
-    rv_plic_reg2hw_prio38_reg_t prio38; // [449:448]
-    rv_plic_reg2hw_prio39_reg_t prio39; // [447:446]
-    rv_plic_reg2hw_prio40_reg_t prio40; // [445:444]
-    rv_plic_reg2hw_prio41_reg_t prio41; // [443:442]
-    rv_plic_reg2hw_prio42_reg_t prio42; // [441:440]
-    rv_plic_reg2hw_prio43_reg_t prio43; // [439:438]
-    rv_plic_reg2hw_prio44_reg_t prio44; // [437:436]
-    rv_plic_reg2hw_prio45_reg_t prio45; // [435:434]
-    rv_plic_reg2hw_prio46_reg_t prio46; // [433:432]
-    rv_plic_reg2hw_prio47_reg_t prio47; // [431:430]
-    rv_plic_reg2hw_prio48_reg_t prio48; // [429:428]
-    rv_plic_reg2hw_prio49_reg_t prio49; // [427:426]
-    rv_plic_reg2hw_prio50_reg_t prio50; // [425:424]
-    rv_plic_reg2hw_prio51_reg_t prio51; // [423:422]
-    rv_plic_reg2hw_prio52_reg_t prio52; // [421:420]
-    rv_plic_reg2hw_prio53_reg_t prio53; // [419:418]
-    rv_plic_reg2hw_prio54_reg_t prio54; // [417:416]
-    rv_plic_reg2hw_prio55_reg_t prio55; // [415:414]
-    rv_plic_reg2hw_prio56_reg_t prio56; // [413:412]
-    rv_plic_reg2hw_prio57_reg_t prio57; // [411:410]
-    rv_plic_reg2hw_prio58_reg_t prio58; // [409:408]
-    rv_plic_reg2hw_prio59_reg_t prio59; // [407:406]
-    rv_plic_reg2hw_prio60_reg_t prio60; // [405:404]
-    rv_plic_reg2hw_prio61_reg_t prio61; // [403:402]
-    rv_plic_reg2hw_prio62_reg_t prio62; // [401:400]
-    rv_plic_reg2hw_prio63_reg_t prio63; // [399:398]
-    rv_plic_reg2hw_prio64_reg_t prio64; // [397:396]
-    rv_plic_reg2hw_prio65_reg_t prio65; // [395:394]
-    rv_plic_reg2hw_prio66_reg_t prio66; // [393:392]
-    rv_plic_reg2hw_prio67_reg_t prio67; // [391:390]
-    rv_plic_reg2hw_prio68_reg_t prio68; // [389:388]
-    rv_plic_reg2hw_prio69_reg_t prio69; // [387:386]
-    rv_plic_reg2hw_prio70_reg_t prio70; // [385:384]
-    rv_plic_reg2hw_prio71_reg_t prio71; // [383:382]
-    rv_plic_reg2hw_prio72_reg_t prio72; // [381:380]
-    rv_plic_reg2hw_prio73_reg_t prio73; // [379:378]
-    rv_plic_reg2hw_prio74_reg_t prio74; // [377:376]
-    rv_plic_reg2hw_prio75_reg_t prio75; // [375:374]
-    rv_plic_reg2hw_prio76_reg_t prio76; // [373:372]
-    rv_plic_reg2hw_prio77_reg_t prio77; // [371:370]
-    rv_plic_reg2hw_prio78_reg_t prio78; // [369:368]
-    rv_plic_reg2hw_prio79_reg_t prio79; // [367:366]
-    rv_plic_reg2hw_prio80_reg_t prio80; // [365:364]
-    rv_plic_reg2hw_prio81_reg_t prio81; // [363:362]
-    rv_plic_reg2hw_prio82_reg_t prio82; // [361:360]
-    rv_plic_reg2hw_prio83_reg_t prio83; // [359:358]
-    rv_plic_reg2hw_prio84_reg_t prio84; // [357:356]
-    rv_plic_reg2hw_prio85_reg_t prio85; // [355:354]
-    rv_plic_reg2hw_prio86_reg_t prio86; // [353:352]
-    rv_plic_reg2hw_prio87_reg_t prio87; // [351:350]
-    rv_plic_reg2hw_prio88_reg_t prio88; // [349:348]
-    rv_plic_reg2hw_prio89_reg_t prio89; // [347:346]
-    rv_plic_reg2hw_prio90_reg_t prio90; // [345:344]
-    rv_plic_reg2hw_prio91_reg_t prio91; // [343:342]
-    rv_plic_reg2hw_prio92_reg_t prio92; // [341:340]
-    rv_plic_reg2hw_prio93_reg_t prio93; // [339:338]
-    rv_plic_reg2hw_prio94_reg_t prio94; // [337:336]
-    rv_plic_reg2hw_prio95_reg_t prio95; // [335:334]
-    rv_plic_reg2hw_prio96_reg_t prio96; // [333:332]
-    rv_plic_reg2hw_prio97_reg_t prio97; // [331:330]
-    rv_plic_reg2hw_prio98_reg_t prio98; // [329:328]
-    rv_plic_reg2hw_prio99_reg_t prio99; // [327:326]
-    rv_plic_reg2hw_prio100_reg_t prio100; // [325:324]
-    rv_plic_reg2hw_prio101_reg_t prio101; // [323:322]
-    rv_plic_reg2hw_prio102_reg_t prio102; // [321:320]
-    rv_plic_reg2hw_prio103_reg_t prio103; // [319:318]
-    rv_plic_reg2hw_prio104_reg_t prio104; // [317:316]
-    rv_plic_reg2hw_prio105_reg_t prio105; // [315:314]
-    rv_plic_reg2hw_prio106_reg_t prio106; // [313:312]
-    rv_plic_reg2hw_prio107_reg_t prio107; // [311:310]
-    rv_plic_reg2hw_prio108_reg_t prio108; // [309:308]
-    rv_plic_reg2hw_prio109_reg_t prio109; // [307:306]
-    rv_plic_reg2hw_prio110_reg_t prio110; // [305:304]
-    rv_plic_reg2hw_prio111_reg_t prio111; // [303:302]
-    rv_plic_reg2hw_prio112_reg_t prio112; // [301:300]
-    rv_plic_reg2hw_prio113_reg_t prio113; // [299:298]
-    rv_plic_reg2hw_prio114_reg_t prio114; // [297:296]
-    rv_plic_reg2hw_prio115_reg_t prio115; // [295:294]
-    rv_plic_reg2hw_prio116_reg_t prio116; // [293:292]
-    rv_plic_reg2hw_prio117_reg_t prio117; // [291:290]
-    rv_plic_reg2hw_prio118_reg_t prio118; // [289:288]
-    rv_plic_reg2hw_prio119_reg_t prio119; // [287:286]
-    rv_plic_reg2hw_prio120_reg_t prio120; // [285:284]
-    rv_plic_reg2hw_prio121_reg_t prio121; // [283:282]
-    rv_plic_reg2hw_prio122_reg_t prio122; // [281:280]
-    rv_plic_reg2hw_prio123_reg_t prio123; // [279:278]
-    rv_plic_reg2hw_prio124_reg_t prio124; // [277:276]
-    rv_plic_reg2hw_prio125_reg_t prio125; // [275:274]
-    rv_plic_reg2hw_prio126_reg_t prio126; // [273:272]
-    rv_plic_reg2hw_prio127_reg_t prio127; // [271:270]
-    rv_plic_reg2hw_prio128_reg_t prio128; // [269:268]
-    rv_plic_reg2hw_prio129_reg_t prio129; // [267:266]
-    rv_plic_reg2hw_prio130_reg_t prio130; // [265:264]
-    rv_plic_reg2hw_prio131_reg_t prio131; // [263:262]
-    rv_plic_reg2hw_prio132_reg_t prio132; // [261:260]
-    rv_plic_reg2hw_prio133_reg_t prio133; // [259:258]
-    rv_plic_reg2hw_prio134_reg_t prio134; // [257:256]
-    rv_plic_reg2hw_prio135_reg_t prio135; // [255:254]
-    rv_plic_reg2hw_prio136_reg_t prio136; // [253:252]
-    rv_plic_reg2hw_prio137_reg_t prio137; // [251:250]
-    rv_plic_reg2hw_prio138_reg_t prio138; // [249:248]
-    rv_plic_reg2hw_prio139_reg_t prio139; // [247:246]
-    rv_plic_reg2hw_prio140_reg_t prio140; // [245:244]
-    rv_plic_reg2hw_prio141_reg_t prio141; // [243:242]
-    rv_plic_reg2hw_prio142_reg_t prio142; // [241:240]
-    rv_plic_reg2hw_prio143_reg_t prio143; // [239:238]
-    rv_plic_reg2hw_prio144_reg_t prio144; // [237:236]
-    rv_plic_reg2hw_prio145_reg_t prio145; // [235:234]
-    rv_plic_reg2hw_prio146_reg_t prio146; // [233:232]
-    rv_plic_reg2hw_prio147_reg_t prio147; // [231:230]
-    rv_plic_reg2hw_prio148_reg_t prio148; // [229:228]
-    rv_plic_reg2hw_prio149_reg_t prio149; // [227:226]
-    rv_plic_reg2hw_prio150_reg_t prio150; // [225:224]
-    rv_plic_reg2hw_prio151_reg_t prio151; // [223:222]
-    rv_plic_reg2hw_prio152_reg_t prio152; // [221:220]
-    rv_plic_reg2hw_prio153_reg_t prio153; // [219:218]
-    rv_plic_reg2hw_prio154_reg_t prio154; // [217:216]
-    rv_plic_reg2hw_prio155_reg_t prio155; // [215:214]
-    rv_plic_reg2hw_prio156_reg_t prio156; // [213:212]
-    rv_plic_reg2hw_prio157_reg_t prio157; // [211:210]
-    rv_plic_reg2hw_prio158_reg_t prio158; // [209:208]
-    rv_plic_reg2hw_prio159_reg_t prio159; // [207:206]
-    rv_plic_reg2hw_prio160_reg_t prio160; // [205:204]
-    rv_plic_reg2hw_prio161_reg_t prio161; // [203:202]
-    rv_plic_reg2hw_prio162_reg_t prio162; // [201:200]
-    rv_plic_reg2hw_prio163_reg_t prio163; // [199:198]
-    rv_plic_reg2hw_prio164_reg_t prio164; // [197:196]
-    rv_plic_reg2hw_prio165_reg_t prio165; // [195:194]
-    rv_plic_reg2hw_prio166_reg_t prio166; // [193:192]
-    rv_plic_reg2hw_prio167_reg_t prio167; // [191:190]
-    rv_plic_reg2hw_prio168_reg_t prio168; // [189:188]
-    rv_plic_reg2hw_prio169_reg_t prio169; // [187:186]
-    rv_plic_reg2hw_prio170_reg_t prio170; // [185:184]
-    rv_plic_reg2hw_ie0_mreg_t [170:0] ie0; // [183:13]
+    rv_plic_reg2hw_le_mreg_t [175:0] le; // [716:541]
+    rv_plic_reg2hw_prio0_reg_t prio0; // [540:539]
+    rv_plic_reg2hw_prio1_reg_t prio1; // [538:537]
+    rv_plic_reg2hw_prio2_reg_t prio2; // [536:535]
+    rv_plic_reg2hw_prio3_reg_t prio3; // [534:533]
+    rv_plic_reg2hw_prio4_reg_t prio4; // [532:531]
+    rv_plic_reg2hw_prio5_reg_t prio5; // [530:529]
+    rv_plic_reg2hw_prio6_reg_t prio6; // [528:527]
+    rv_plic_reg2hw_prio7_reg_t prio7; // [526:525]
+    rv_plic_reg2hw_prio8_reg_t prio8; // [524:523]
+    rv_plic_reg2hw_prio9_reg_t prio9; // [522:521]
+    rv_plic_reg2hw_prio10_reg_t prio10; // [520:519]
+    rv_plic_reg2hw_prio11_reg_t prio11; // [518:517]
+    rv_plic_reg2hw_prio12_reg_t prio12; // [516:515]
+    rv_plic_reg2hw_prio13_reg_t prio13; // [514:513]
+    rv_plic_reg2hw_prio14_reg_t prio14; // [512:511]
+    rv_plic_reg2hw_prio15_reg_t prio15; // [510:509]
+    rv_plic_reg2hw_prio16_reg_t prio16; // [508:507]
+    rv_plic_reg2hw_prio17_reg_t prio17; // [506:505]
+    rv_plic_reg2hw_prio18_reg_t prio18; // [504:503]
+    rv_plic_reg2hw_prio19_reg_t prio19; // [502:501]
+    rv_plic_reg2hw_prio20_reg_t prio20; // [500:499]
+    rv_plic_reg2hw_prio21_reg_t prio21; // [498:497]
+    rv_plic_reg2hw_prio22_reg_t prio22; // [496:495]
+    rv_plic_reg2hw_prio23_reg_t prio23; // [494:493]
+    rv_plic_reg2hw_prio24_reg_t prio24; // [492:491]
+    rv_plic_reg2hw_prio25_reg_t prio25; // [490:489]
+    rv_plic_reg2hw_prio26_reg_t prio26; // [488:487]
+    rv_plic_reg2hw_prio27_reg_t prio27; // [486:485]
+    rv_plic_reg2hw_prio28_reg_t prio28; // [484:483]
+    rv_plic_reg2hw_prio29_reg_t prio29; // [482:481]
+    rv_plic_reg2hw_prio30_reg_t prio30; // [480:479]
+    rv_plic_reg2hw_prio31_reg_t prio31; // [478:477]
+    rv_plic_reg2hw_prio32_reg_t prio32; // [476:475]
+    rv_plic_reg2hw_prio33_reg_t prio33; // [474:473]
+    rv_plic_reg2hw_prio34_reg_t prio34; // [472:471]
+    rv_plic_reg2hw_prio35_reg_t prio35; // [470:469]
+    rv_plic_reg2hw_prio36_reg_t prio36; // [468:467]
+    rv_plic_reg2hw_prio37_reg_t prio37; // [466:465]
+    rv_plic_reg2hw_prio38_reg_t prio38; // [464:463]
+    rv_plic_reg2hw_prio39_reg_t prio39; // [462:461]
+    rv_plic_reg2hw_prio40_reg_t prio40; // [460:459]
+    rv_plic_reg2hw_prio41_reg_t prio41; // [458:457]
+    rv_plic_reg2hw_prio42_reg_t prio42; // [456:455]
+    rv_plic_reg2hw_prio43_reg_t prio43; // [454:453]
+    rv_plic_reg2hw_prio44_reg_t prio44; // [452:451]
+    rv_plic_reg2hw_prio45_reg_t prio45; // [450:449]
+    rv_plic_reg2hw_prio46_reg_t prio46; // [448:447]
+    rv_plic_reg2hw_prio47_reg_t prio47; // [446:445]
+    rv_plic_reg2hw_prio48_reg_t prio48; // [444:443]
+    rv_plic_reg2hw_prio49_reg_t prio49; // [442:441]
+    rv_plic_reg2hw_prio50_reg_t prio50; // [440:439]
+    rv_plic_reg2hw_prio51_reg_t prio51; // [438:437]
+    rv_plic_reg2hw_prio52_reg_t prio52; // [436:435]
+    rv_plic_reg2hw_prio53_reg_t prio53; // [434:433]
+    rv_plic_reg2hw_prio54_reg_t prio54; // [432:431]
+    rv_plic_reg2hw_prio55_reg_t prio55; // [430:429]
+    rv_plic_reg2hw_prio56_reg_t prio56; // [428:427]
+    rv_plic_reg2hw_prio57_reg_t prio57; // [426:425]
+    rv_plic_reg2hw_prio58_reg_t prio58; // [424:423]
+    rv_plic_reg2hw_prio59_reg_t prio59; // [422:421]
+    rv_plic_reg2hw_prio60_reg_t prio60; // [420:419]
+    rv_plic_reg2hw_prio61_reg_t prio61; // [418:417]
+    rv_plic_reg2hw_prio62_reg_t prio62; // [416:415]
+    rv_plic_reg2hw_prio63_reg_t prio63; // [414:413]
+    rv_plic_reg2hw_prio64_reg_t prio64; // [412:411]
+    rv_plic_reg2hw_prio65_reg_t prio65; // [410:409]
+    rv_plic_reg2hw_prio66_reg_t prio66; // [408:407]
+    rv_plic_reg2hw_prio67_reg_t prio67; // [406:405]
+    rv_plic_reg2hw_prio68_reg_t prio68; // [404:403]
+    rv_plic_reg2hw_prio69_reg_t prio69; // [402:401]
+    rv_plic_reg2hw_prio70_reg_t prio70; // [400:399]
+    rv_plic_reg2hw_prio71_reg_t prio71; // [398:397]
+    rv_plic_reg2hw_prio72_reg_t prio72; // [396:395]
+    rv_plic_reg2hw_prio73_reg_t prio73; // [394:393]
+    rv_plic_reg2hw_prio74_reg_t prio74; // [392:391]
+    rv_plic_reg2hw_prio75_reg_t prio75; // [390:389]
+    rv_plic_reg2hw_prio76_reg_t prio76; // [388:387]
+    rv_plic_reg2hw_prio77_reg_t prio77; // [386:385]
+    rv_plic_reg2hw_prio78_reg_t prio78; // [384:383]
+    rv_plic_reg2hw_prio79_reg_t prio79; // [382:381]
+    rv_plic_reg2hw_prio80_reg_t prio80; // [380:379]
+    rv_plic_reg2hw_prio81_reg_t prio81; // [378:377]
+    rv_plic_reg2hw_prio82_reg_t prio82; // [376:375]
+    rv_plic_reg2hw_prio83_reg_t prio83; // [374:373]
+    rv_plic_reg2hw_prio84_reg_t prio84; // [372:371]
+    rv_plic_reg2hw_prio85_reg_t prio85; // [370:369]
+    rv_plic_reg2hw_prio86_reg_t prio86; // [368:367]
+    rv_plic_reg2hw_prio87_reg_t prio87; // [366:365]
+    rv_plic_reg2hw_prio88_reg_t prio88; // [364:363]
+    rv_plic_reg2hw_prio89_reg_t prio89; // [362:361]
+    rv_plic_reg2hw_prio90_reg_t prio90; // [360:359]
+    rv_plic_reg2hw_prio91_reg_t prio91; // [358:357]
+    rv_plic_reg2hw_prio92_reg_t prio92; // [356:355]
+    rv_plic_reg2hw_prio93_reg_t prio93; // [354:353]
+    rv_plic_reg2hw_prio94_reg_t prio94; // [352:351]
+    rv_plic_reg2hw_prio95_reg_t prio95; // [350:349]
+    rv_plic_reg2hw_prio96_reg_t prio96; // [348:347]
+    rv_plic_reg2hw_prio97_reg_t prio97; // [346:345]
+    rv_plic_reg2hw_prio98_reg_t prio98; // [344:343]
+    rv_plic_reg2hw_prio99_reg_t prio99; // [342:341]
+    rv_plic_reg2hw_prio100_reg_t prio100; // [340:339]
+    rv_plic_reg2hw_prio101_reg_t prio101; // [338:337]
+    rv_plic_reg2hw_prio102_reg_t prio102; // [336:335]
+    rv_plic_reg2hw_prio103_reg_t prio103; // [334:333]
+    rv_plic_reg2hw_prio104_reg_t prio104; // [332:331]
+    rv_plic_reg2hw_prio105_reg_t prio105; // [330:329]
+    rv_plic_reg2hw_prio106_reg_t prio106; // [328:327]
+    rv_plic_reg2hw_prio107_reg_t prio107; // [326:325]
+    rv_plic_reg2hw_prio108_reg_t prio108; // [324:323]
+    rv_plic_reg2hw_prio109_reg_t prio109; // [322:321]
+    rv_plic_reg2hw_prio110_reg_t prio110; // [320:319]
+    rv_plic_reg2hw_prio111_reg_t prio111; // [318:317]
+    rv_plic_reg2hw_prio112_reg_t prio112; // [316:315]
+    rv_plic_reg2hw_prio113_reg_t prio113; // [314:313]
+    rv_plic_reg2hw_prio114_reg_t prio114; // [312:311]
+    rv_plic_reg2hw_prio115_reg_t prio115; // [310:309]
+    rv_plic_reg2hw_prio116_reg_t prio116; // [308:307]
+    rv_plic_reg2hw_prio117_reg_t prio117; // [306:305]
+    rv_plic_reg2hw_prio118_reg_t prio118; // [304:303]
+    rv_plic_reg2hw_prio119_reg_t prio119; // [302:301]
+    rv_plic_reg2hw_prio120_reg_t prio120; // [300:299]
+    rv_plic_reg2hw_prio121_reg_t prio121; // [298:297]
+    rv_plic_reg2hw_prio122_reg_t prio122; // [296:295]
+    rv_plic_reg2hw_prio123_reg_t prio123; // [294:293]
+    rv_plic_reg2hw_prio124_reg_t prio124; // [292:291]
+    rv_plic_reg2hw_prio125_reg_t prio125; // [290:289]
+    rv_plic_reg2hw_prio126_reg_t prio126; // [288:287]
+    rv_plic_reg2hw_prio127_reg_t prio127; // [286:285]
+    rv_plic_reg2hw_prio128_reg_t prio128; // [284:283]
+    rv_plic_reg2hw_prio129_reg_t prio129; // [282:281]
+    rv_plic_reg2hw_prio130_reg_t prio130; // [280:279]
+    rv_plic_reg2hw_prio131_reg_t prio131; // [278:277]
+    rv_plic_reg2hw_prio132_reg_t prio132; // [276:275]
+    rv_plic_reg2hw_prio133_reg_t prio133; // [274:273]
+    rv_plic_reg2hw_prio134_reg_t prio134; // [272:271]
+    rv_plic_reg2hw_prio135_reg_t prio135; // [270:269]
+    rv_plic_reg2hw_prio136_reg_t prio136; // [268:267]
+    rv_plic_reg2hw_prio137_reg_t prio137; // [266:265]
+    rv_plic_reg2hw_prio138_reg_t prio138; // [264:263]
+    rv_plic_reg2hw_prio139_reg_t prio139; // [262:261]
+    rv_plic_reg2hw_prio140_reg_t prio140; // [260:259]
+    rv_plic_reg2hw_prio141_reg_t prio141; // [258:257]
+    rv_plic_reg2hw_prio142_reg_t prio142; // [256:255]
+    rv_plic_reg2hw_prio143_reg_t prio143; // [254:253]
+    rv_plic_reg2hw_prio144_reg_t prio144; // [252:251]
+    rv_plic_reg2hw_prio145_reg_t prio145; // [250:249]
+    rv_plic_reg2hw_prio146_reg_t prio146; // [248:247]
+    rv_plic_reg2hw_prio147_reg_t prio147; // [246:245]
+    rv_plic_reg2hw_prio148_reg_t prio148; // [244:243]
+    rv_plic_reg2hw_prio149_reg_t prio149; // [242:241]
+    rv_plic_reg2hw_prio150_reg_t prio150; // [240:239]
+    rv_plic_reg2hw_prio151_reg_t prio151; // [238:237]
+    rv_plic_reg2hw_prio152_reg_t prio152; // [236:235]
+    rv_plic_reg2hw_prio153_reg_t prio153; // [234:233]
+    rv_plic_reg2hw_prio154_reg_t prio154; // [232:231]
+    rv_plic_reg2hw_prio155_reg_t prio155; // [230:229]
+    rv_plic_reg2hw_prio156_reg_t prio156; // [228:227]
+    rv_plic_reg2hw_prio157_reg_t prio157; // [226:225]
+    rv_plic_reg2hw_prio158_reg_t prio158; // [224:223]
+    rv_plic_reg2hw_prio159_reg_t prio159; // [222:221]
+    rv_plic_reg2hw_prio160_reg_t prio160; // [220:219]
+    rv_plic_reg2hw_prio161_reg_t prio161; // [218:217]
+    rv_plic_reg2hw_prio162_reg_t prio162; // [216:215]
+    rv_plic_reg2hw_prio163_reg_t prio163; // [214:213]
+    rv_plic_reg2hw_prio164_reg_t prio164; // [212:211]
+    rv_plic_reg2hw_prio165_reg_t prio165; // [210:209]
+    rv_plic_reg2hw_prio166_reg_t prio166; // [208:207]
+    rv_plic_reg2hw_prio167_reg_t prio167; // [206:205]
+    rv_plic_reg2hw_prio168_reg_t prio168; // [204:203]
+    rv_plic_reg2hw_prio169_reg_t prio169; // [202:201]
+    rv_plic_reg2hw_prio170_reg_t prio170; // [200:199]
+    rv_plic_reg2hw_prio171_reg_t prio171; // [198:197]
+    rv_plic_reg2hw_prio172_reg_t prio172; // [196:195]
+    rv_plic_reg2hw_prio173_reg_t prio173; // [194:193]
+    rv_plic_reg2hw_prio174_reg_t prio174; // [192:191]
+    rv_plic_reg2hw_prio175_reg_t prio175; // [190:189]
+    rv_plic_reg2hw_ie0_mreg_t [175:0] ie0; // [188:13]
     rv_plic_reg2hw_threshold0_reg_t threshold0; // [12:11]
     rv_plic_reg2hw_cc0_reg_t cc0; // [10:1]
     rv_plic_reg2hw_msip0_reg_t msip0; // [0:0]
@@ -920,7 +945,7 @@
   // Internal design logic to register //
   ///////////////////////////////////////
   typedef struct packed {
-    rv_plic_hw2reg_ip_mreg_t [170:0] ip; // [349:8]
+    rv_plic_hw2reg_ip_mreg_t [175:0] ip; // [359:8]
     rv_plic_hw2reg_cc0_reg_t cc0; // [7:0]
   } rv_plic_hw2reg_t;
 
@@ -1108,6 +1133,11 @@
   parameter logic [BlockAw-1:0] RV_PLIC_PRIO168_OFFSET = 10'h 2d0;
   parameter logic [BlockAw-1:0] RV_PLIC_PRIO169_OFFSET = 10'h 2d4;
   parameter logic [BlockAw-1:0] RV_PLIC_PRIO170_OFFSET = 10'h 2d8;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO171_OFFSET = 10'h 2dc;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO172_OFFSET = 10'h 2e0;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO173_OFFSET = 10'h 2e4;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO174_OFFSET = 10'h 2e8;
+  parameter logic [BlockAw-1:0] RV_PLIC_PRIO175_OFFSET = 10'h 2ec;
   parameter logic [BlockAw-1:0] RV_PLIC_IE0_0_OFFSET = 10'h 300;
   parameter logic [BlockAw-1:0] RV_PLIC_IE0_1_OFFSET = 10'h 304;
   parameter logic [BlockAw-1:0] RV_PLIC_IE0_2_OFFSET = 10'h 308;
@@ -1306,6 +1336,11 @@
     RV_PLIC_PRIO168,
     RV_PLIC_PRIO169,
     RV_PLIC_PRIO170,
+    RV_PLIC_PRIO171,
+    RV_PLIC_PRIO172,
+    RV_PLIC_PRIO173,
+    RV_PLIC_PRIO174,
+    RV_PLIC_PRIO175,
     RV_PLIC_IE0_0,
     RV_PLIC_IE0_1,
     RV_PLIC_IE0_2,
@@ -1318,7 +1353,7 @@
   } rv_plic_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] RV_PLIC_PERMIT [192] = '{
+  parameter logic [3:0] RV_PLIC_PERMIT [197] = '{
     4'b 1111, // index[  0] RV_PLIC_IP_0
     4'b 1111, // index[  1] RV_PLIC_IP_1
     4'b 1111, // index[  2] RV_PLIC_IP_2
@@ -1502,15 +1537,20 @@
     4'b 0001, // index[180] RV_PLIC_PRIO168
     4'b 0001, // index[181] RV_PLIC_PRIO169
     4'b 0001, // index[182] RV_PLIC_PRIO170
-    4'b 1111, // index[183] RV_PLIC_IE0_0
-    4'b 1111, // index[184] RV_PLIC_IE0_1
-    4'b 1111, // index[185] RV_PLIC_IE0_2
-    4'b 1111, // index[186] RV_PLIC_IE0_3
-    4'b 1111, // index[187] RV_PLIC_IE0_4
-    4'b 0011, // index[188] RV_PLIC_IE0_5
-    4'b 0001, // index[189] RV_PLIC_THRESHOLD0
-    4'b 0001, // index[190] RV_PLIC_CC0
-    4'b 0001  // index[191] RV_PLIC_MSIP0
+    4'b 0001, // index[183] RV_PLIC_PRIO171
+    4'b 0001, // index[184] RV_PLIC_PRIO172
+    4'b 0001, // index[185] RV_PLIC_PRIO173
+    4'b 0001, // index[186] RV_PLIC_PRIO174
+    4'b 0001, // index[187] RV_PLIC_PRIO175
+    4'b 1111, // index[188] RV_PLIC_IE0_0
+    4'b 1111, // index[189] RV_PLIC_IE0_1
+    4'b 1111, // index[190] RV_PLIC_IE0_2
+    4'b 1111, // index[191] RV_PLIC_IE0_3
+    4'b 1111, // index[192] RV_PLIC_IE0_4
+    4'b 0011, // index[193] RV_PLIC_IE0_5
+    4'b 0001, // index[194] RV_PLIC_THRESHOLD0
+    4'b 0001, // index[195] RV_PLIC_CC0
+    4'b 0001  // index[196] RV_PLIC_MSIP0
   };
 endpackage
 
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
index 5e3438f..942ba26 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
@@ -272,6 +272,11 @@
   logic ip_5_p_168_qs;
   logic ip_5_p_169_qs;
   logic ip_5_p_170_qs;
+  logic ip_5_p_171_qs;
+  logic ip_5_p_172_qs;
+  logic ip_5_p_173_qs;
+  logic ip_5_p_174_qs;
+  logic ip_5_p_175_qs;
   logic le_0_le_0_qs;
   logic le_0_le_0_wd;
   logic le_0_le_0_we;
@@ -785,6 +790,21 @@
   logic le_5_le_170_qs;
   logic le_5_le_170_wd;
   logic le_5_le_170_we;
+  logic le_5_le_171_qs;
+  logic le_5_le_171_wd;
+  logic le_5_le_171_we;
+  logic le_5_le_172_qs;
+  logic le_5_le_172_wd;
+  logic le_5_le_172_we;
+  logic le_5_le_173_qs;
+  logic le_5_le_173_wd;
+  logic le_5_le_173_we;
+  logic le_5_le_174_qs;
+  logic le_5_le_174_wd;
+  logic le_5_le_174_we;
+  logic le_5_le_175_qs;
+  logic le_5_le_175_wd;
+  logic le_5_le_175_we;
   logic [1:0] prio0_qs;
   logic [1:0] prio0_wd;
   logic prio0_we;
@@ -1298,6 +1318,21 @@
   logic [1:0] prio170_qs;
   logic [1:0] prio170_wd;
   logic prio170_we;
+  logic [1:0] prio171_qs;
+  logic [1:0] prio171_wd;
+  logic prio171_we;
+  logic [1:0] prio172_qs;
+  logic [1:0] prio172_wd;
+  logic prio172_we;
+  logic [1:0] prio173_qs;
+  logic [1:0] prio173_wd;
+  logic prio173_we;
+  logic [1:0] prio174_qs;
+  logic [1:0] prio174_wd;
+  logic prio174_we;
+  logic [1:0] prio175_qs;
+  logic [1:0] prio175_wd;
+  logic prio175_we;
   logic ie0_0_e_0_qs;
   logic ie0_0_e_0_wd;
   logic ie0_0_e_0_we;
@@ -1811,6 +1846,21 @@
   logic ie0_5_e_170_qs;
   logic ie0_5_e_170_wd;
   logic ie0_5_e_170_we;
+  logic ie0_5_e_171_qs;
+  logic ie0_5_e_171_wd;
+  logic ie0_5_e_171_we;
+  logic ie0_5_e_172_qs;
+  logic ie0_5_e_172_wd;
+  logic ie0_5_e_172_we;
+  logic ie0_5_e_173_qs;
+  logic ie0_5_e_173_wd;
+  logic ie0_5_e_173_we;
+  logic ie0_5_e_174_qs;
+  logic ie0_5_e_174_wd;
+  logic ie0_5_e_174_we;
+  logic ie0_5_e_175_qs;
+  logic ie0_5_e_175_wd;
+  logic ie0_5_e_175_we;
   logic [1:0] threshold0_qs;
   logic [1:0] threshold0_wd;
   logic threshold0_we;
@@ -6117,6 +6167,131 @@
   );
 
 
+  // F[p_171]: 11:11
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip_5_p_171 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[171].de),
+    .d      (hw2reg.ip[171].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip_5_p_171_qs)
+  );
+
+
+  // F[p_172]: 12:12
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip_5_p_172 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[172].de),
+    .d      (hw2reg.ip[172].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip_5_p_172_qs)
+  );
+
+
+  // F[p_173]: 13:13
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip_5_p_173 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[173].de),
+    .d      (hw2reg.ip[173].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip_5_p_173_qs)
+  );
+
+
+  // F[p_174]: 14:14
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip_5_p_174 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[174].de),
+    .d      (hw2reg.ip[174].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip_5_p_174_qs)
+  );
+
+
+  // F[p_175]: 15:15
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RO"),
+    .RESVAL  (1'h0)
+  ) u_ip_5_p_175 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    .we     (1'b0),
+    .wd     ('0  ),
+
+    // from internal hardware
+    .de     (hw2reg.ip[175].de),
+    .d      (hw2reg.ip[175].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (ip_5_p_175_qs)
+  );
+
+
 
 
   // Subregister 0 of Multireg le
@@ -10583,6 +10758,136 @@
   );
 
 
+  // F[le_171]: 11:11
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le_5_le_171 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le_5_le_171_we),
+    .wd     (le_5_le_171_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[171].q ),
+
+    // to register interface (read)
+    .qs     (le_5_le_171_qs)
+  );
+
+
+  // F[le_172]: 12:12
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le_5_le_172 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le_5_le_172_we),
+    .wd     (le_5_le_172_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[172].q ),
+
+    // to register interface (read)
+    .qs     (le_5_le_172_qs)
+  );
+
+
+  // F[le_173]: 13:13
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le_5_le_173 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le_5_le_173_we),
+    .wd     (le_5_le_173_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[173].q ),
+
+    // to register interface (read)
+    .qs     (le_5_le_173_qs)
+  );
+
+
+  // F[le_174]: 14:14
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le_5_le_174 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le_5_le_174_we),
+    .wd     (le_5_le_174_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[174].q ),
+
+    // to register interface (read)
+    .qs     (le_5_le_174_qs)
+  );
+
+
+  // F[le_175]: 15:15
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_le_5_le_175 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (le_5_le_175_we),
+    .wd     (le_5_le_175_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.le[175].q ),
+
+    // to register interface (read)
+    .qs     (le_5_le_175_qs)
+  );
+
+
 
   // R[prio0]: V(False)
 
@@ -15201,6 +15506,141 @@
   );
 
 
+  // R[prio171]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio171 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio171_we),
+    .wd     (prio171_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio171.q ),
+
+    // to register interface (read)
+    .qs     (prio171_qs)
+  );
+
+
+  // R[prio172]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio172 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio172_we),
+    .wd     (prio172_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio172.q ),
+
+    // to register interface (read)
+    .qs     (prio172_qs)
+  );
+
+
+  // R[prio173]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio173 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio173_we),
+    .wd     (prio173_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio173.q ),
+
+    // to register interface (read)
+    .qs     (prio173_qs)
+  );
+
+
+  // R[prio174]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio174 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio174_we),
+    .wd     (prio174_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio174.q ),
+
+    // to register interface (read)
+    .qs     (prio174_qs)
+  );
+
+
+  // R[prio175]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_prio175 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (prio175_we),
+    .wd     (prio175_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.prio175.q ),
+
+    // to register interface (read)
+    .qs     (prio175_qs)
+  );
+
+
 
   // Subregister 0 of Multireg ie0
   // R[ie0_0]: V(False)
@@ -19666,6 +20106,136 @@
   );
 
 
+  // F[e_171]: 11:11
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie0_5_e_171 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie0_5_e_171_we),
+    .wd     (ie0_5_e_171_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[171].q ),
+
+    // to register interface (read)
+    .qs     (ie0_5_e_171_qs)
+  );
+
+
+  // F[e_172]: 12:12
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie0_5_e_172 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie0_5_e_172_we),
+    .wd     (ie0_5_e_172_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[172].q ),
+
+    // to register interface (read)
+    .qs     (ie0_5_e_172_qs)
+  );
+
+
+  // F[e_173]: 13:13
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie0_5_e_173 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie0_5_e_173_we),
+    .wd     (ie0_5_e_173_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[173].q ),
+
+    // to register interface (read)
+    .qs     (ie0_5_e_173_qs)
+  );
+
+
+  // F[e_174]: 14:14
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie0_5_e_174 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie0_5_e_174_we),
+    .wd     (ie0_5_e_174_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[174].q ),
+
+    // to register interface (read)
+    .qs     (ie0_5_e_174_qs)
+  );
+
+
+  // F[e_175]: 15:15
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_ie0_5_e_175 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (ie0_5_e_175_we),
+    .wd     (ie0_5_e_175_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.ie0[175].q ),
+
+    // to register interface (read)
+    .qs     (ie0_5_e_175_qs)
+  );
+
+
 
   // R[threshold0]: V(False)
 
@@ -19739,7 +20309,7 @@
 
 
 
-  logic [191:0] addr_hit;
+  logic [196:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[  0] = (reg_addr == RV_PLIC_IP_0_OFFSET);
@@ -19925,15 +20495,20 @@
     addr_hit[180] = (reg_addr == RV_PLIC_PRIO168_OFFSET);
     addr_hit[181] = (reg_addr == RV_PLIC_PRIO169_OFFSET);
     addr_hit[182] = (reg_addr == RV_PLIC_PRIO170_OFFSET);
-    addr_hit[183] = (reg_addr == RV_PLIC_IE0_0_OFFSET);
-    addr_hit[184] = (reg_addr == RV_PLIC_IE0_1_OFFSET);
-    addr_hit[185] = (reg_addr == RV_PLIC_IE0_2_OFFSET);
-    addr_hit[186] = (reg_addr == RV_PLIC_IE0_3_OFFSET);
-    addr_hit[187] = (reg_addr == RV_PLIC_IE0_4_OFFSET);
-    addr_hit[188] = (reg_addr == RV_PLIC_IE0_5_OFFSET);
-    addr_hit[189] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
-    addr_hit[190] = (reg_addr == RV_PLIC_CC0_OFFSET);
-    addr_hit[191] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
+    addr_hit[183] = (reg_addr == RV_PLIC_PRIO171_OFFSET);
+    addr_hit[184] = (reg_addr == RV_PLIC_PRIO172_OFFSET);
+    addr_hit[185] = (reg_addr == RV_PLIC_PRIO173_OFFSET);
+    addr_hit[186] = (reg_addr == RV_PLIC_PRIO174_OFFSET);
+    addr_hit[187] = (reg_addr == RV_PLIC_PRIO175_OFFSET);
+    addr_hit[188] = (reg_addr == RV_PLIC_IE0_0_OFFSET);
+    addr_hit[189] = (reg_addr == RV_PLIC_IE0_1_OFFSET);
+    addr_hit[190] = (reg_addr == RV_PLIC_IE0_2_OFFSET);
+    addr_hit[191] = (reg_addr == RV_PLIC_IE0_3_OFFSET);
+    addr_hit[192] = (reg_addr == RV_PLIC_IE0_4_OFFSET);
+    addr_hit[193] = (reg_addr == RV_PLIC_IE0_5_OFFSET);
+    addr_hit[194] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
+    addr_hit[195] = (reg_addr == RV_PLIC_CC0_OFFSET);
+    addr_hit[196] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -20133,6 +20708,11 @@
     if (addr_hit[189] && reg_we && (RV_PLIC_PERMIT[189] != (RV_PLIC_PERMIT[189] & reg_be))) wr_err = 1'b1 ;
     if (addr_hit[190] && reg_we && (RV_PLIC_PERMIT[190] != (RV_PLIC_PERMIT[190] & reg_be))) wr_err = 1'b1 ;
     if (addr_hit[191] && reg_we && (RV_PLIC_PERMIT[191] != (RV_PLIC_PERMIT[191] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[192] && reg_we && (RV_PLIC_PERMIT[192] != (RV_PLIC_PERMIT[192] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[193] && reg_we && (RV_PLIC_PERMIT[193] != (RV_PLIC_PERMIT[193] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[194] && reg_we && (RV_PLIC_PERMIT[194] != (RV_PLIC_PERMIT[194] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[195] && reg_we && (RV_PLIC_PERMIT[195] != (RV_PLIC_PERMIT[195] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[196] && reg_we && (RV_PLIC_PERMIT[196] != (RV_PLIC_PERMIT[196] & reg_be))) wr_err = 1'b1 ;
   end
 
 
@@ -20306,6 +20886,11 @@
 
 
 
+
+
+
+
+
   assign le_0_le_0_we = addr_hit[6] & reg_we & !reg_error;
   assign le_0_le_0_wd = reg_wdata[0];
 
@@ -20819,6 +21404,21 @@
   assign le_5_le_170_we = addr_hit[11] & reg_we & !reg_error;
   assign le_5_le_170_wd = reg_wdata[10];
 
+  assign le_5_le_171_we = addr_hit[11] & reg_we & !reg_error;
+  assign le_5_le_171_wd = reg_wdata[11];
+
+  assign le_5_le_172_we = addr_hit[11] & reg_we & !reg_error;
+  assign le_5_le_172_wd = reg_wdata[12];
+
+  assign le_5_le_173_we = addr_hit[11] & reg_we & !reg_error;
+  assign le_5_le_173_wd = reg_wdata[13];
+
+  assign le_5_le_174_we = addr_hit[11] & reg_we & !reg_error;
+  assign le_5_le_174_wd = reg_wdata[14];
+
+  assign le_5_le_175_we = addr_hit[11] & reg_we & !reg_error;
+  assign le_5_le_175_wd = reg_wdata[15];
+
   assign prio0_we = addr_hit[12] & reg_we & !reg_error;
   assign prio0_wd = reg_wdata[1:0];
 
@@ -21332,527 +21932,557 @@
   assign prio170_we = addr_hit[182] & reg_we & !reg_error;
   assign prio170_wd = reg_wdata[1:0];
 
-  assign ie0_0_e_0_we = addr_hit[183] & reg_we & !reg_error;
+  assign prio171_we = addr_hit[183] & reg_we & !reg_error;
+  assign prio171_wd = reg_wdata[1:0];
+
+  assign prio172_we = addr_hit[184] & reg_we & !reg_error;
+  assign prio172_wd = reg_wdata[1:0];
+
+  assign prio173_we = addr_hit[185] & reg_we & !reg_error;
+  assign prio173_wd = reg_wdata[1:0];
+
+  assign prio174_we = addr_hit[186] & reg_we & !reg_error;
+  assign prio174_wd = reg_wdata[1:0];
+
+  assign prio175_we = addr_hit[187] & reg_we & !reg_error;
+  assign prio175_wd = reg_wdata[1:0];
+
+  assign ie0_0_e_0_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_0_wd = reg_wdata[0];
 
-  assign ie0_0_e_1_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_1_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_1_wd = reg_wdata[1];
 
-  assign ie0_0_e_2_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_2_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_2_wd = reg_wdata[2];
 
-  assign ie0_0_e_3_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_3_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_3_wd = reg_wdata[3];
 
-  assign ie0_0_e_4_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_4_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_4_wd = reg_wdata[4];
 
-  assign ie0_0_e_5_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_5_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_5_wd = reg_wdata[5];
 
-  assign ie0_0_e_6_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_6_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_6_wd = reg_wdata[6];
 
-  assign ie0_0_e_7_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_7_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_7_wd = reg_wdata[7];
 
-  assign ie0_0_e_8_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_8_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_8_wd = reg_wdata[8];
 
-  assign ie0_0_e_9_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_9_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_9_wd = reg_wdata[9];
 
-  assign ie0_0_e_10_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_10_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_10_wd = reg_wdata[10];
 
-  assign ie0_0_e_11_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_11_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_11_wd = reg_wdata[11];
 
-  assign ie0_0_e_12_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_12_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_12_wd = reg_wdata[12];
 
-  assign ie0_0_e_13_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_13_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_13_wd = reg_wdata[13];
 
-  assign ie0_0_e_14_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_14_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_14_wd = reg_wdata[14];
 
-  assign ie0_0_e_15_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_15_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_15_wd = reg_wdata[15];
 
-  assign ie0_0_e_16_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_16_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_16_wd = reg_wdata[16];
 
-  assign ie0_0_e_17_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_17_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_17_wd = reg_wdata[17];
 
-  assign ie0_0_e_18_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_18_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_18_wd = reg_wdata[18];
 
-  assign ie0_0_e_19_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_19_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_19_wd = reg_wdata[19];
 
-  assign ie0_0_e_20_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_20_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_20_wd = reg_wdata[20];
 
-  assign ie0_0_e_21_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_21_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_21_wd = reg_wdata[21];
 
-  assign ie0_0_e_22_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_22_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_22_wd = reg_wdata[22];
 
-  assign ie0_0_e_23_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_23_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_23_wd = reg_wdata[23];
 
-  assign ie0_0_e_24_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_24_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_24_wd = reg_wdata[24];
 
-  assign ie0_0_e_25_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_25_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_25_wd = reg_wdata[25];
 
-  assign ie0_0_e_26_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_26_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_26_wd = reg_wdata[26];
 
-  assign ie0_0_e_27_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_27_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_27_wd = reg_wdata[27];
 
-  assign ie0_0_e_28_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_28_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_28_wd = reg_wdata[28];
 
-  assign ie0_0_e_29_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_29_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_29_wd = reg_wdata[29];
 
-  assign ie0_0_e_30_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_30_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_30_wd = reg_wdata[30];
 
-  assign ie0_0_e_31_we = addr_hit[183] & reg_we & !reg_error;
+  assign ie0_0_e_31_we = addr_hit[188] & reg_we & !reg_error;
   assign ie0_0_e_31_wd = reg_wdata[31];
 
-  assign ie0_1_e_32_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_32_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_32_wd = reg_wdata[0];
 
-  assign ie0_1_e_33_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_33_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_33_wd = reg_wdata[1];
 
-  assign ie0_1_e_34_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_34_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_34_wd = reg_wdata[2];
 
-  assign ie0_1_e_35_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_35_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_35_wd = reg_wdata[3];
 
-  assign ie0_1_e_36_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_36_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_36_wd = reg_wdata[4];
 
-  assign ie0_1_e_37_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_37_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_37_wd = reg_wdata[5];
 
-  assign ie0_1_e_38_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_38_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_38_wd = reg_wdata[6];
 
-  assign ie0_1_e_39_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_39_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_39_wd = reg_wdata[7];
 
-  assign ie0_1_e_40_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_40_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_40_wd = reg_wdata[8];
 
-  assign ie0_1_e_41_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_41_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_41_wd = reg_wdata[9];
 
-  assign ie0_1_e_42_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_42_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_42_wd = reg_wdata[10];
 
-  assign ie0_1_e_43_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_43_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_43_wd = reg_wdata[11];
 
-  assign ie0_1_e_44_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_44_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_44_wd = reg_wdata[12];
 
-  assign ie0_1_e_45_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_45_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_45_wd = reg_wdata[13];
 
-  assign ie0_1_e_46_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_46_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_46_wd = reg_wdata[14];
 
-  assign ie0_1_e_47_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_47_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_47_wd = reg_wdata[15];
 
-  assign ie0_1_e_48_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_48_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_48_wd = reg_wdata[16];
 
-  assign ie0_1_e_49_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_49_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_49_wd = reg_wdata[17];
 
-  assign ie0_1_e_50_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_50_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_50_wd = reg_wdata[18];
 
-  assign ie0_1_e_51_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_51_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_51_wd = reg_wdata[19];
 
-  assign ie0_1_e_52_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_52_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_52_wd = reg_wdata[20];
 
-  assign ie0_1_e_53_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_53_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_53_wd = reg_wdata[21];
 
-  assign ie0_1_e_54_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_54_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_54_wd = reg_wdata[22];
 
-  assign ie0_1_e_55_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_55_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_55_wd = reg_wdata[23];
 
-  assign ie0_1_e_56_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_56_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_56_wd = reg_wdata[24];
 
-  assign ie0_1_e_57_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_57_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_57_wd = reg_wdata[25];
 
-  assign ie0_1_e_58_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_58_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_58_wd = reg_wdata[26];
 
-  assign ie0_1_e_59_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_59_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_59_wd = reg_wdata[27];
 
-  assign ie0_1_e_60_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_60_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_60_wd = reg_wdata[28];
 
-  assign ie0_1_e_61_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_61_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_61_wd = reg_wdata[29];
 
-  assign ie0_1_e_62_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_62_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_62_wd = reg_wdata[30];
 
-  assign ie0_1_e_63_we = addr_hit[184] & reg_we & !reg_error;
+  assign ie0_1_e_63_we = addr_hit[189] & reg_we & !reg_error;
   assign ie0_1_e_63_wd = reg_wdata[31];
 
-  assign ie0_2_e_64_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_64_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_64_wd = reg_wdata[0];
 
-  assign ie0_2_e_65_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_65_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_65_wd = reg_wdata[1];
 
-  assign ie0_2_e_66_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_66_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_66_wd = reg_wdata[2];
 
-  assign ie0_2_e_67_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_67_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_67_wd = reg_wdata[3];
 
-  assign ie0_2_e_68_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_68_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_68_wd = reg_wdata[4];
 
-  assign ie0_2_e_69_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_69_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_69_wd = reg_wdata[5];
 
-  assign ie0_2_e_70_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_70_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_70_wd = reg_wdata[6];
 
-  assign ie0_2_e_71_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_71_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_71_wd = reg_wdata[7];
 
-  assign ie0_2_e_72_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_72_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_72_wd = reg_wdata[8];
 
-  assign ie0_2_e_73_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_73_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_73_wd = reg_wdata[9];
 
-  assign ie0_2_e_74_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_74_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_74_wd = reg_wdata[10];
 
-  assign ie0_2_e_75_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_75_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_75_wd = reg_wdata[11];
 
-  assign ie0_2_e_76_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_76_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_76_wd = reg_wdata[12];
 
-  assign ie0_2_e_77_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_77_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_77_wd = reg_wdata[13];
 
-  assign ie0_2_e_78_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_78_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_78_wd = reg_wdata[14];
 
-  assign ie0_2_e_79_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_79_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_79_wd = reg_wdata[15];
 
-  assign ie0_2_e_80_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_80_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_80_wd = reg_wdata[16];
 
-  assign ie0_2_e_81_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_81_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_81_wd = reg_wdata[17];
 
-  assign ie0_2_e_82_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_82_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_82_wd = reg_wdata[18];
 
-  assign ie0_2_e_83_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_83_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_83_wd = reg_wdata[19];
 
-  assign ie0_2_e_84_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_84_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_84_wd = reg_wdata[20];
 
-  assign ie0_2_e_85_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_85_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_85_wd = reg_wdata[21];
 
-  assign ie0_2_e_86_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_86_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_86_wd = reg_wdata[22];
 
-  assign ie0_2_e_87_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_87_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_87_wd = reg_wdata[23];
 
-  assign ie0_2_e_88_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_88_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_88_wd = reg_wdata[24];
 
-  assign ie0_2_e_89_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_89_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_89_wd = reg_wdata[25];
 
-  assign ie0_2_e_90_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_90_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_90_wd = reg_wdata[26];
 
-  assign ie0_2_e_91_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_91_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_91_wd = reg_wdata[27];
 
-  assign ie0_2_e_92_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_92_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_92_wd = reg_wdata[28];
 
-  assign ie0_2_e_93_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_93_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_93_wd = reg_wdata[29];
 
-  assign ie0_2_e_94_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_94_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_94_wd = reg_wdata[30];
 
-  assign ie0_2_e_95_we = addr_hit[185] & reg_we & !reg_error;
+  assign ie0_2_e_95_we = addr_hit[190] & reg_we & !reg_error;
   assign ie0_2_e_95_wd = reg_wdata[31];
 
-  assign ie0_3_e_96_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_96_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_96_wd = reg_wdata[0];
 
-  assign ie0_3_e_97_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_97_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_97_wd = reg_wdata[1];
 
-  assign ie0_3_e_98_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_98_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_98_wd = reg_wdata[2];
 
-  assign ie0_3_e_99_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_99_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_99_wd = reg_wdata[3];
 
-  assign ie0_3_e_100_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_100_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_100_wd = reg_wdata[4];
 
-  assign ie0_3_e_101_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_101_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_101_wd = reg_wdata[5];
 
-  assign ie0_3_e_102_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_102_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_102_wd = reg_wdata[6];
 
-  assign ie0_3_e_103_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_103_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_103_wd = reg_wdata[7];
 
-  assign ie0_3_e_104_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_104_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_104_wd = reg_wdata[8];
 
-  assign ie0_3_e_105_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_105_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_105_wd = reg_wdata[9];
 
-  assign ie0_3_e_106_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_106_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_106_wd = reg_wdata[10];
 
-  assign ie0_3_e_107_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_107_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_107_wd = reg_wdata[11];
 
-  assign ie0_3_e_108_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_108_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_108_wd = reg_wdata[12];
 
-  assign ie0_3_e_109_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_109_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_109_wd = reg_wdata[13];
 
-  assign ie0_3_e_110_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_110_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_110_wd = reg_wdata[14];
 
-  assign ie0_3_e_111_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_111_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_111_wd = reg_wdata[15];
 
-  assign ie0_3_e_112_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_112_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_112_wd = reg_wdata[16];
 
-  assign ie0_3_e_113_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_113_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_113_wd = reg_wdata[17];
 
-  assign ie0_3_e_114_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_114_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_114_wd = reg_wdata[18];
 
-  assign ie0_3_e_115_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_115_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_115_wd = reg_wdata[19];
 
-  assign ie0_3_e_116_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_116_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_116_wd = reg_wdata[20];
 
-  assign ie0_3_e_117_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_117_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_117_wd = reg_wdata[21];
 
-  assign ie0_3_e_118_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_118_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_118_wd = reg_wdata[22];
 
-  assign ie0_3_e_119_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_119_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_119_wd = reg_wdata[23];
 
-  assign ie0_3_e_120_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_120_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_120_wd = reg_wdata[24];
 
-  assign ie0_3_e_121_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_121_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_121_wd = reg_wdata[25];
 
-  assign ie0_3_e_122_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_122_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_122_wd = reg_wdata[26];
 
-  assign ie0_3_e_123_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_123_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_123_wd = reg_wdata[27];
 
-  assign ie0_3_e_124_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_124_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_124_wd = reg_wdata[28];
 
-  assign ie0_3_e_125_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_125_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_125_wd = reg_wdata[29];
 
-  assign ie0_3_e_126_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_126_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_126_wd = reg_wdata[30];
 
-  assign ie0_3_e_127_we = addr_hit[186] & reg_we & !reg_error;
+  assign ie0_3_e_127_we = addr_hit[191] & reg_we & !reg_error;
   assign ie0_3_e_127_wd = reg_wdata[31];
 
-  assign ie0_4_e_128_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_128_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_128_wd = reg_wdata[0];
 
-  assign ie0_4_e_129_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_129_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_129_wd = reg_wdata[1];
 
-  assign ie0_4_e_130_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_130_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_130_wd = reg_wdata[2];
 
-  assign ie0_4_e_131_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_131_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_131_wd = reg_wdata[3];
 
-  assign ie0_4_e_132_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_132_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_132_wd = reg_wdata[4];
 
-  assign ie0_4_e_133_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_133_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_133_wd = reg_wdata[5];
 
-  assign ie0_4_e_134_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_134_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_134_wd = reg_wdata[6];
 
-  assign ie0_4_e_135_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_135_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_135_wd = reg_wdata[7];
 
-  assign ie0_4_e_136_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_136_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_136_wd = reg_wdata[8];
 
-  assign ie0_4_e_137_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_137_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_137_wd = reg_wdata[9];
 
-  assign ie0_4_e_138_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_138_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_138_wd = reg_wdata[10];
 
-  assign ie0_4_e_139_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_139_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_139_wd = reg_wdata[11];
 
-  assign ie0_4_e_140_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_140_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_140_wd = reg_wdata[12];
 
-  assign ie0_4_e_141_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_141_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_141_wd = reg_wdata[13];
 
-  assign ie0_4_e_142_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_142_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_142_wd = reg_wdata[14];
 
-  assign ie0_4_e_143_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_143_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_143_wd = reg_wdata[15];
 
-  assign ie0_4_e_144_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_144_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_144_wd = reg_wdata[16];
 
-  assign ie0_4_e_145_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_145_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_145_wd = reg_wdata[17];
 
-  assign ie0_4_e_146_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_146_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_146_wd = reg_wdata[18];
 
-  assign ie0_4_e_147_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_147_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_147_wd = reg_wdata[19];
 
-  assign ie0_4_e_148_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_148_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_148_wd = reg_wdata[20];
 
-  assign ie0_4_e_149_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_149_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_149_wd = reg_wdata[21];
 
-  assign ie0_4_e_150_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_150_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_150_wd = reg_wdata[22];
 
-  assign ie0_4_e_151_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_151_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_151_wd = reg_wdata[23];
 
-  assign ie0_4_e_152_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_152_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_152_wd = reg_wdata[24];
 
-  assign ie0_4_e_153_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_153_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_153_wd = reg_wdata[25];
 
-  assign ie0_4_e_154_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_154_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_154_wd = reg_wdata[26];
 
-  assign ie0_4_e_155_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_155_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_155_wd = reg_wdata[27];
 
-  assign ie0_4_e_156_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_156_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_156_wd = reg_wdata[28];
 
-  assign ie0_4_e_157_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_157_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_157_wd = reg_wdata[29];
 
-  assign ie0_4_e_158_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_158_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_158_wd = reg_wdata[30];
 
-  assign ie0_4_e_159_we = addr_hit[187] & reg_we & !reg_error;
+  assign ie0_4_e_159_we = addr_hit[192] & reg_we & !reg_error;
   assign ie0_4_e_159_wd = reg_wdata[31];
 
-  assign ie0_5_e_160_we = addr_hit[188] & reg_we & !reg_error;
+  assign ie0_5_e_160_we = addr_hit[193] & reg_we & !reg_error;
   assign ie0_5_e_160_wd = reg_wdata[0];
 
-  assign ie0_5_e_161_we = addr_hit[188] & reg_we & !reg_error;
+  assign ie0_5_e_161_we = addr_hit[193] & reg_we & !reg_error;
   assign ie0_5_e_161_wd = reg_wdata[1];
 
-  assign ie0_5_e_162_we = addr_hit[188] & reg_we & !reg_error;
+  assign ie0_5_e_162_we = addr_hit[193] & reg_we & !reg_error;
   assign ie0_5_e_162_wd = reg_wdata[2];
 
-  assign ie0_5_e_163_we = addr_hit[188] & reg_we & !reg_error;
+  assign ie0_5_e_163_we = addr_hit[193] & reg_we & !reg_error;
   assign ie0_5_e_163_wd = reg_wdata[3];
 
-  assign ie0_5_e_164_we = addr_hit[188] & reg_we & !reg_error;
+  assign ie0_5_e_164_we = addr_hit[193] & reg_we & !reg_error;
   assign ie0_5_e_164_wd = reg_wdata[4];
 
-  assign ie0_5_e_165_we = addr_hit[188] & reg_we & !reg_error;
+  assign ie0_5_e_165_we = addr_hit[193] & reg_we & !reg_error;
   assign ie0_5_e_165_wd = reg_wdata[5];
 
-  assign ie0_5_e_166_we = addr_hit[188] & reg_we & !reg_error;
+  assign ie0_5_e_166_we = addr_hit[193] & reg_we & !reg_error;
   assign ie0_5_e_166_wd = reg_wdata[6];
 
-  assign ie0_5_e_167_we = addr_hit[188] & reg_we & !reg_error;
+  assign ie0_5_e_167_we = addr_hit[193] & reg_we & !reg_error;
   assign ie0_5_e_167_wd = reg_wdata[7];
 
-  assign ie0_5_e_168_we = addr_hit[188] & reg_we & !reg_error;
+  assign ie0_5_e_168_we = addr_hit[193] & reg_we & !reg_error;
   assign ie0_5_e_168_wd = reg_wdata[8];
 
-  assign ie0_5_e_169_we = addr_hit[188] & reg_we & !reg_error;
+  assign ie0_5_e_169_we = addr_hit[193] & reg_we & !reg_error;
   assign ie0_5_e_169_wd = reg_wdata[9];
 
-  assign ie0_5_e_170_we = addr_hit[188] & reg_we & !reg_error;
+  assign ie0_5_e_170_we = addr_hit[193] & reg_we & !reg_error;
   assign ie0_5_e_170_wd = reg_wdata[10];
 
-  assign threshold0_we = addr_hit[189] & reg_we & !reg_error;
+  assign ie0_5_e_171_we = addr_hit[193] & reg_we & !reg_error;
+  assign ie0_5_e_171_wd = reg_wdata[11];
+
+  assign ie0_5_e_172_we = addr_hit[193] & reg_we & !reg_error;
+  assign ie0_5_e_172_wd = reg_wdata[12];
+
+  assign ie0_5_e_173_we = addr_hit[193] & reg_we & !reg_error;
+  assign ie0_5_e_173_wd = reg_wdata[13];
+
+  assign ie0_5_e_174_we = addr_hit[193] & reg_we & !reg_error;
+  assign ie0_5_e_174_wd = reg_wdata[14];
+
+  assign ie0_5_e_175_we = addr_hit[193] & reg_we & !reg_error;
+  assign ie0_5_e_175_wd = reg_wdata[15];
+
+  assign threshold0_we = addr_hit[194] & reg_we & !reg_error;
   assign threshold0_wd = reg_wdata[1:0];
 
-  assign cc0_we = addr_hit[190] & reg_we & !reg_error;
+  assign cc0_we = addr_hit[195] & reg_we & !reg_error;
   assign cc0_wd = reg_wdata[7:0];
-  assign cc0_re = addr_hit[190] & reg_re & !reg_error;
+  assign cc0_re = addr_hit[195] & reg_re & !reg_error;
 
-  assign msip0_we = addr_hit[191] & reg_we & !reg_error;
+  assign msip0_we = addr_hit[196] & reg_we & !reg_error;
   assign msip0_wd = reg_wdata[0];
 
   // Read data return
@@ -22046,6 +22676,11 @@
         reg_rdata_next[8] = ip_5_p_168_qs;
         reg_rdata_next[9] = ip_5_p_169_qs;
         reg_rdata_next[10] = ip_5_p_170_qs;
+        reg_rdata_next[11] = ip_5_p_171_qs;
+        reg_rdata_next[12] = ip_5_p_172_qs;
+        reg_rdata_next[13] = ip_5_p_173_qs;
+        reg_rdata_next[14] = ip_5_p_174_qs;
+        reg_rdata_next[15] = ip_5_p_175_qs;
       end
 
       addr_hit[6]: begin
@@ -22235,6 +22870,11 @@
         reg_rdata_next[8] = le_5_le_168_qs;
         reg_rdata_next[9] = le_5_le_169_qs;
         reg_rdata_next[10] = le_5_le_170_qs;
+        reg_rdata_next[11] = le_5_le_171_qs;
+        reg_rdata_next[12] = le_5_le_172_qs;
+        reg_rdata_next[13] = le_5_le_173_qs;
+        reg_rdata_next[14] = le_5_le_174_qs;
+        reg_rdata_next[15] = le_5_le_175_qs;
       end
 
       addr_hit[12]: begin
@@ -22922,6 +23562,26 @@
       end
 
       addr_hit[183]: begin
+        reg_rdata_next[1:0] = prio171_qs;
+      end
+
+      addr_hit[184]: begin
+        reg_rdata_next[1:0] = prio172_qs;
+      end
+
+      addr_hit[185]: begin
+        reg_rdata_next[1:0] = prio173_qs;
+      end
+
+      addr_hit[186]: begin
+        reg_rdata_next[1:0] = prio174_qs;
+      end
+
+      addr_hit[187]: begin
+        reg_rdata_next[1:0] = prio175_qs;
+      end
+
+      addr_hit[188]: begin
         reg_rdata_next[0] = ie0_0_e_0_qs;
         reg_rdata_next[1] = ie0_0_e_1_qs;
         reg_rdata_next[2] = ie0_0_e_2_qs;
@@ -22956,7 +23616,7 @@
         reg_rdata_next[31] = ie0_0_e_31_qs;
       end
 
-      addr_hit[184]: begin
+      addr_hit[189]: begin
         reg_rdata_next[0] = ie0_1_e_32_qs;
         reg_rdata_next[1] = ie0_1_e_33_qs;
         reg_rdata_next[2] = ie0_1_e_34_qs;
@@ -22991,7 +23651,7 @@
         reg_rdata_next[31] = ie0_1_e_63_qs;
       end
 
-      addr_hit[185]: begin
+      addr_hit[190]: begin
         reg_rdata_next[0] = ie0_2_e_64_qs;
         reg_rdata_next[1] = ie0_2_e_65_qs;
         reg_rdata_next[2] = ie0_2_e_66_qs;
@@ -23026,7 +23686,7 @@
         reg_rdata_next[31] = ie0_2_e_95_qs;
       end
 
-      addr_hit[186]: begin
+      addr_hit[191]: begin
         reg_rdata_next[0] = ie0_3_e_96_qs;
         reg_rdata_next[1] = ie0_3_e_97_qs;
         reg_rdata_next[2] = ie0_3_e_98_qs;
@@ -23061,7 +23721,7 @@
         reg_rdata_next[31] = ie0_3_e_127_qs;
       end
 
-      addr_hit[187]: begin
+      addr_hit[192]: begin
         reg_rdata_next[0] = ie0_4_e_128_qs;
         reg_rdata_next[1] = ie0_4_e_129_qs;
         reg_rdata_next[2] = ie0_4_e_130_qs;
@@ -23096,7 +23756,7 @@
         reg_rdata_next[31] = ie0_4_e_159_qs;
       end
 
-      addr_hit[188]: begin
+      addr_hit[193]: begin
         reg_rdata_next[0] = ie0_5_e_160_qs;
         reg_rdata_next[1] = ie0_5_e_161_qs;
         reg_rdata_next[2] = ie0_5_e_162_qs;
@@ -23108,17 +23768,22 @@
         reg_rdata_next[8] = ie0_5_e_168_qs;
         reg_rdata_next[9] = ie0_5_e_169_qs;
         reg_rdata_next[10] = ie0_5_e_170_qs;
+        reg_rdata_next[11] = ie0_5_e_171_qs;
+        reg_rdata_next[12] = ie0_5_e_172_qs;
+        reg_rdata_next[13] = ie0_5_e_173_qs;
+        reg_rdata_next[14] = ie0_5_e_174_qs;
+        reg_rdata_next[15] = ie0_5_e_175_qs;
       end
 
-      addr_hit[189]: begin
+      addr_hit[194]: begin
         reg_rdata_next[1:0] = threshold0_qs;
       end
 
-      addr_hit[190]: begin
+      addr_hit[195]: begin
         reg_rdata_next[7:0] = cc0_qs;
       end
 
-      addr_hit[191]: begin
+      addr_hit[196]: begin
         reg_rdata_next[0] = msip0_qs;
       end
 
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 72611d1..bb11bb9 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -234,7 +234,7 @@
   // otbn
 
 
-  logic [170:0]  intr_vector;
+  logic [175:0]  intr_vector;
   // Interrupt source list
   logic intr_uart0_tx_watermark;
   logic intr_uart0_rx_watermark;
@@ -2112,106 +2112,111 @@
 
   // interrupt assignments
   assign intr_vector = {
+      intr_otbn_done, // ID 144
+      intr_edn1_edn_fatal_err, // ID 143
+      intr_edn1_edn_cmd_req_done, // ID 142
+      intr_edn0_edn_fatal_err, // ID 141
+      intr_edn0_edn_cmd_req_done, // ID 140
       intr_entropy_src_es_fatal_err, // ID 139
       intr_entropy_src_es_health_test_failed, // ID 138
       intr_entropy_src_es_entropy_valid, // ID 137
-      intr_aon_timer_aon_wdog_timer_bark, // ID 136
-      intr_aon_timer_aon_wkup_timer_expired, // ID 135
-      intr_edn1_edn_fatal_err, // ID 134
-      intr_edn1_edn_cmd_req_done, // ID 133
-      intr_edn0_edn_fatal_err, // ID 132
-      intr_edn0_edn_cmd_req_done, // ID 131
-      intr_csrng_cs_fatal_err, // ID 130
-      intr_csrng_cs_hw_inst_exc, // ID 129
-      intr_csrng_cs_entropy_req, // ID 128
-      intr_csrng_cs_cmd_req_done, // ID 127
-      intr_otp_ctrl_otp_error, // ID 126
-      intr_otp_ctrl_otp_operation_done, // ID 125
-      intr_kmac_kmac_err, // ID 124
-      intr_kmac_fifo_empty, // ID 123
-      intr_kmac_kmac_done, // ID 122
-      intr_keymgr_op_done, // ID 121
-      intr_otbn_done, // ID 120
-      intr_pwrmgr_aon_wakeup, // ID 119
-      intr_usbdev_link_out_err, // ID 118
-      intr_usbdev_connected, // ID 117
-      intr_usbdev_frame, // ID 116
-      intr_usbdev_rx_bitstuff_err, // ID 115
-      intr_usbdev_rx_pid_err, // ID 114
-      intr_usbdev_rx_crc_err, // ID 113
-      intr_usbdev_link_in_err, // ID 112
-      intr_usbdev_av_overflow, // ID 111
-      intr_usbdev_rx_full, // ID 110
-      intr_usbdev_av_empty, // ID 109
-      intr_usbdev_link_resume, // ID 108
-      intr_usbdev_link_suspend, // ID 107
-      intr_usbdev_link_reset, // ID 106
-      intr_usbdev_host_lost, // ID 105
-      intr_usbdev_disconnected, // ID 104
-      intr_usbdev_pkt_sent, // ID 103
-      intr_usbdev_pkt_received, // ID 102
-      intr_alert_handler_classd, // ID 101
-      intr_alert_handler_classc, // ID 100
-      intr_alert_handler_classb, // ID 99
-      intr_alert_handler_classa, // ID 98
-      intr_hmac_hmac_err, // ID 97
-      intr_hmac_fifo_empty, // ID 96
-      intr_hmac_hmac_done, // ID 95
-      intr_flash_ctrl_op_done, // ID 94
-      intr_flash_ctrl_rd_lvl, // ID 93
-      intr_flash_ctrl_rd_full, // ID 92
-      intr_flash_ctrl_prog_lvl, // ID 91
-      intr_flash_ctrl_prog_empty, // ID 90
-      intr_pattgen_done_ch1, // ID 89
-      intr_pattgen_done_ch0, // ID 88
-      intr_i2c2_host_timeout, // ID 87
-      intr_i2c2_ack_stop, // ID 86
-      intr_i2c2_acq_overflow, // ID 85
-      intr_i2c2_tx_overflow, // ID 84
-      intr_i2c2_tx_nonempty, // ID 83
-      intr_i2c2_tx_empty, // ID 82
-      intr_i2c2_trans_complete, // ID 81
-      intr_i2c2_sda_unstable, // ID 80
-      intr_i2c2_stretch_timeout, // ID 79
-      intr_i2c2_sda_interference, // ID 78
-      intr_i2c2_scl_interference, // ID 77
-      intr_i2c2_nak, // ID 76
-      intr_i2c2_rx_overflow, // ID 75
-      intr_i2c2_fmt_overflow, // ID 74
-      intr_i2c2_rx_watermark, // ID 73
-      intr_i2c2_fmt_watermark, // ID 72
-      intr_i2c1_host_timeout, // ID 71
-      intr_i2c1_ack_stop, // ID 70
-      intr_i2c1_acq_overflow, // ID 69
-      intr_i2c1_tx_overflow, // ID 68
-      intr_i2c1_tx_nonempty, // ID 67
-      intr_i2c1_tx_empty, // ID 66
-      intr_i2c1_trans_complete, // ID 65
-      intr_i2c1_sda_unstable, // ID 64
-      intr_i2c1_stretch_timeout, // ID 63
-      intr_i2c1_sda_interference, // ID 62
-      intr_i2c1_scl_interference, // ID 61
-      intr_i2c1_nak, // ID 60
-      intr_i2c1_rx_overflow, // ID 59
-      intr_i2c1_fmt_overflow, // ID 58
-      intr_i2c1_rx_watermark, // ID 57
-      intr_i2c1_fmt_watermark, // ID 56
-      intr_i2c0_host_timeout, // ID 55
-      intr_i2c0_ack_stop, // ID 54
-      intr_i2c0_acq_overflow, // ID 53
-      intr_i2c0_tx_overflow, // ID 52
-      intr_i2c0_tx_nonempty, // ID 51
-      intr_i2c0_tx_empty, // ID 50
-      intr_i2c0_trans_complete, // ID 49
-      intr_i2c0_sda_unstable, // ID 48
-      intr_i2c0_stretch_timeout, // ID 47
-      intr_i2c0_sda_interference, // ID 46
-      intr_i2c0_scl_interference, // ID 45
-      intr_i2c0_nak, // ID 44
-      intr_i2c0_rx_overflow, // ID 43
-      intr_i2c0_fmt_overflow, // ID 42
-      intr_i2c0_rx_watermark, // ID 41
-      intr_i2c0_fmt_watermark, // ID 40
+      intr_csrng_cs_fatal_err, // ID 136
+      intr_csrng_cs_hw_inst_exc, // ID 135
+      intr_csrng_cs_entropy_req, // ID 134
+      intr_csrng_cs_cmd_req_done, // ID 133
+      intr_keymgr_op_done, // ID 132
+      intr_kmac_kmac_err, // ID 131
+      intr_kmac_fifo_empty, // ID 130
+      intr_kmac_kmac_done, // ID 129
+      intr_hmac_hmac_err, // ID 128
+      intr_hmac_fifo_empty, // ID 127
+      intr_hmac_hmac_done, // ID 126
+      intr_flash_ctrl_op_done, // ID 125
+      intr_flash_ctrl_rd_lvl, // ID 124
+      intr_flash_ctrl_rd_full, // ID 123
+      intr_flash_ctrl_prog_lvl, // ID 122
+      intr_flash_ctrl_prog_empty, // ID 121
+      intr_aon_timer_aon_wdog_timer_bark, // ID 120
+      intr_aon_timer_aon_wkup_timer_expired, // ID 119
+      intr_pwrmgr_aon_wakeup, // ID 118
+      intr_alert_handler_classd, // ID 117
+      intr_alert_handler_classc, // ID 116
+      intr_alert_handler_classb, // ID 115
+      intr_alert_handler_classa, // ID 114
+      intr_otp_ctrl_otp_error, // ID 113
+      intr_otp_ctrl_otp_operation_done, // ID 112
+      intr_usbdev_link_out_err, // ID 111
+      intr_usbdev_connected, // ID 110
+      intr_usbdev_frame, // ID 109
+      intr_usbdev_rx_bitstuff_err, // ID 108
+      intr_usbdev_rx_pid_err, // ID 107
+      intr_usbdev_rx_crc_err, // ID 106
+      intr_usbdev_link_in_err, // ID 105
+      intr_usbdev_av_overflow, // ID 104
+      intr_usbdev_rx_full, // ID 103
+      intr_usbdev_av_empty, // ID 102
+      intr_usbdev_link_resume, // ID 101
+      intr_usbdev_link_suspend, // ID 100
+      intr_usbdev_link_reset, // ID 99
+      intr_usbdev_host_lost, // ID 98
+      intr_usbdev_disconnected, // ID 97
+      intr_usbdev_pkt_sent, // ID 96
+      intr_usbdev_pkt_received, // ID 95
+      intr_rv_timer_timer_expired_0_0, // ID 94
+      intr_pattgen_done_ch1, // ID 93
+      intr_pattgen_done_ch0, // ID 92
+      intr_i2c2_host_timeout, // ID 91
+      intr_i2c2_ack_stop, // ID 90
+      intr_i2c2_acq_overflow, // ID 89
+      intr_i2c2_tx_overflow, // ID 88
+      intr_i2c2_tx_nonempty, // ID 87
+      intr_i2c2_tx_empty, // ID 86
+      intr_i2c2_trans_complete, // ID 85
+      intr_i2c2_sda_unstable, // ID 84
+      intr_i2c2_stretch_timeout, // ID 83
+      intr_i2c2_sda_interference, // ID 82
+      intr_i2c2_scl_interference, // ID 81
+      intr_i2c2_nak, // ID 80
+      intr_i2c2_rx_overflow, // ID 79
+      intr_i2c2_fmt_overflow, // ID 78
+      intr_i2c2_rx_watermark, // ID 77
+      intr_i2c2_fmt_watermark, // ID 76
+      intr_i2c1_host_timeout, // ID 75
+      intr_i2c1_ack_stop, // ID 74
+      intr_i2c1_acq_overflow, // ID 73
+      intr_i2c1_tx_overflow, // ID 72
+      intr_i2c1_tx_nonempty, // ID 71
+      intr_i2c1_tx_empty, // ID 70
+      intr_i2c1_trans_complete, // ID 69
+      intr_i2c1_sda_unstable, // ID 68
+      intr_i2c1_stretch_timeout, // ID 67
+      intr_i2c1_sda_interference, // ID 66
+      intr_i2c1_scl_interference, // ID 65
+      intr_i2c1_nak, // ID 64
+      intr_i2c1_rx_overflow, // ID 63
+      intr_i2c1_fmt_overflow, // ID 62
+      intr_i2c1_rx_watermark, // ID 61
+      intr_i2c1_fmt_watermark, // ID 60
+      intr_i2c0_host_timeout, // ID 59
+      intr_i2c0_ack_stop, // ID 58
+      intr_i2c0_acq_overflow, // ID 57
+      intr_i2c0_tx_overflow, // ID 56
+      intr_i2c0_tx_nonempty, // ID 55
+      intr_i2c0_tx_empty, // ID 54
+      intr_i2c0_trans_complete, // ID 53
+      intr_i2c0_sda_unstable, // ID 52
+      intr_i2c0_stretch_timeout, // ID 51
+      intr_i2c0_sda_interference, // ID 50
+      intr_i2c0_scl_interference, // ID 49
+      intr_i2c0_nak, // ID 48
+      intr_i2c0_rx_overflow, // ID 47
+      intr_i2c0_fmt_overflow, // ID 46
+      intr_i2c0_rx_watermark, // ID 45
+      intr_i2c0_fmt_watermark, // ID 44
+      intr_spi_host1_spi_event, // ID 43
+      intr_spi_host1_error, // ID 42
+      intr_spi_host0_spi_event, // ID 41
+      intr_spi_host0_error, // ID 40
       intr_spi_device_txunderflow, // ID 39
       intr_spi_device_rxoverflow, // ID 38
       intr_spi_device_rxerr, // ID 37
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index 56a3614..64aa951 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -11,7 +11,7 @@
  * `top_earlgrey_plic_peripheral_t`.
  */
 const top_earlgrey_plic_peripheral_t
-    top_earlgrey_plic_interrupt_for_peripheral[171] = {
+    top_earlgrey_plic_interrupt_for_peripheral[176] = {
   [kTopEarlgreyPlicIrqIdNone] = kTopEarlgreyPlicPeripheralUnknown,
   [kTopEarlgreyPlicIrqIdUart0TxWatermark] = kTopEarlgreyPlicPeripheralUart0,
   [kTopEarlgreyPlicIrqIdUart0RxWatermark] = kTopEarlgreyPlicPeripheralUart0,
@@ -83,6 +83,10 @@
   [kTopEarlgreyPlicIrqIdSpiDeviceRxerr] = kTopEarlgreyPlicPeripheralSpiDevice,
   [kTopEarlgreyPlicIrqIdSpiDeviceRxoverflow] = kTopEarlgreyPlicPeripheralSpiDevice,
   [kTopEarlgreyPlicIrqIdSpiDeviceTxunderflow] = kTopEarlgreyPlicPeripheralSpiDevice,
+  [kTopEarlgreyPlicIrqIdSpiHost0Error] = kTopEarlgreyPlicPeripheralSpiHost0,
+  [kTopEarlgreyPlicIrqIdSpiHost0SpiEvent] = kTopEarlgreyPlicPeripheralSpiHost0,
+  [kTopEarlgreyPlicIrqIdSpiHost1Error] = kTopEarlgreyPlicPeripheralSpiHost1,
+  [kTopEarlgreyPlicIrqIdSpiHost1SpiEvent] = kTopEarlgreyPlicPeripheralSpiHost1,
   [kTopEarlgreyPlicIrqIdI2c0FmtWatermark] = kTopEarlgreyPlicPeripheralI2c0,
   [kTopEarlgreyPlicIrqIdI2c0RxWatermark] = kTopEarlgreyPlicPeripheralI2c0,
   [kTopEarlgreyPlicIrqIdI2c0FmtOverflow] = kTopEarlgreyPlicPeripheralI2c0,
@@ -133,18 +137,7 @@
   [kTopEarlgreyPlicIrqIdI2c2HostTimeout] = kTopEarlgreyPlicPeripheralI2c2,
   [kTopEarlgreyPlicIrqIdPattgenDoneCh0] = kTopEarlgreyPlicPeripheralPattgen,
   [kTopEarlgreyPlicIrqIdPattgenDoneCh1] = kTopEarlgreyPlicPeripheralPattgen,
-  [kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty] = kTopEarlgreyPlicPeripheralFlashCtrl,
-  [kTopEarlgreyPlicIrqIdFlashCtrlProgLvl] = kTopEarlgreyPlicPeripheralFlashCtrl,
-  [kTopEarlgreyPlicIrqIdFlashCtrlRdFull] = kTopEarlgreyPlicPeripheralFlashCtrl,
-  [kTopEarlgreyPlicIrqIdFlashCtrlRdLvl] = kTopEarlgreyPlicPeripheralFlashCtrl,
-  [kTopEarlgreyPlicIrqIdFlashCtrlOpDone] = kTopEarlgreyPlicPeripheralFlashCtrl,
-  [kTopEarlgreyPlicIrqIdHmacHmacDone] = kTopEarlgreyPlicPeripheralHmac,
-  [kTopEarlgreyPlicIrqIdHmacFifoEmpty] = kTopEarlgreyPlicPeripheralHmac,
-  [kTopEarlgreyPlicIrqIdHmacHmacErr] = kTopEarlgreyPlicPeripheralHmac,
-  [kTopEarlgreyPlicIrqIdAlertHandlerClassa] = kTopEarlgreyPlicPeripheralAlertHandler,
-  [kTopEarlgreyPlicIrqIdAlertHandlerClassb] = kTopEarlgreyPlicPeripheralAlertHandler,
-  [kTopEarlgreyPlicIrqIdAlertHandlerClassc] = kTopEarlgreyPlicPeripheralAlertHandler,
-  [kTopEarlgreyPlicIrqIdAlertHandlerClassd] = kTopEarlgreyPlicPeripheralAlertHandler,
+  [kTopEarlgreyPlicIrqIdRvTimerTimerExpired0_0] = kTopEarlgreyPlicPeripheralRvTimer,
   [kTopEarlgreyPlicIrqIdUsbdevPktReceived] = kTopEarlgreyPlicPeripheralUsbdev,
   [kTopEarlgreyPlicIrqIdUsbdevPktSent] = kTopEarlgreyPlicPeripheralUsbdev,
   [kTopEarlgreyPlicIrqIdUsbdevDisconnected] = kTopEarlgreyPlicPeripheralUsbdev,
@@ -162,27 +155,39 @@
   [kTopEarlgreyPlicIrqIdUsbdevFrame] = kTopEarlgreyPlicPeripheralUsbdev,
   [kTopEarlgreyPlicIrqIdUsbdevConnected] = kTopEarlgreyPlicPeripheralUsbdev,
   [kTopEarlgreyPlicIrqIdUsbdevLinkOutErr] = kTopEarlgreyPlicPeripheralUsbdev,
+  [kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone] = kTopEarlgreyPlicPeripheralOtpCtrl,
+  [kTopEarlgreyPlicIrqIdOtpCtrlOtpError] = kTopEarlgreyPlicPeripheralOtpCtrl,
+  [kTopEarlgreyPlicIrqIdAlertHandlerClassa] = kTopEarlgreyPlicPeripheralAlertHandler,
+  [kTopEarlgreyPlicIrqIdAlertHandlerClassb] = kTopEarlgreyPlicPeripheralAlertHandler,
+  [kTopEarlgreyPlicIrqIdAlertHandlerClassc] = kTopEarlgreyPlicPeripheralAlertHandler,
+  [kTopEarlgreyPlicIrqIdAlertHandlerClassd] = kTopEarlgreyPlicPeripheralAlertHandler,
   [kTopEarlgreyPlicIrqIdPwrmgrAonWakeup] = kTopEarlgreyPlicPeripheralPwrmgrAon,
-  [kTopEarlgreyPlicIrqIdOtbnDone] = kTopEarlgreyPlicPeripheralOtbn,
-  [kTopEarlgreyPlicIrqIdKeymgrOpDone] = kTopEarlgreyPlicPeripheralKeymgr,
+  [kTopEarlgreyPlicIrqIdAonTimerAonWkupTimerExpired] = kTopEarlgreyPlicPeripheralAonTimerAon,
+  [kTopEarlgreyPlicIrqIdAonTimerAonWdogTimerBark] = kTopEarlgreyPlicPeripheralAonTimerAon,
+  [kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty] = kTopEarlgreyPlicPeripheralFlashCtrl,
+  [kTopEarlgreyPlicIrqIdFlashCtrlProgLvl] = kTopEarlgreyPlicPeripheralFlashCtrl,
+  [kTopEarlgreyPlicIrqIdFlashCtrlRdFull] = kTopEarlgreyPlicPeripheralFlashCtrl,
+  [kTopEarlgreyPlicIrqIdFlashCtrlRdLvl] = kTopEarlgreyPlicPeripheralFlashCtrl,
+  [kTopEarlgreyPlicIrqIdFlashCtrlOpDone] = kTopEarlgreyPlicPeripheralFlashCtrl,
+  [kTopEarlgreyPlicIrqIdHmacHmacDone] = kTopEarlgreyPlicPeripheralHmac,
+  [kTopEarlgreyPlicIrqIdHmacFifoEmpty] = kTopEarlgreyPlicPeripheralHmac,
+  [kTopEarlgreyPlicIrqIdHmacHmacErr] = kTopEarlgreyPlicPeripheralHmac,
   [kTopEarlgreyPlicIrqIdKmacKmacDone] = kTopEarlgreyPlicPeripheralKmac,
   [kTopEarlgreyPlicIrqIdKmacFifoEmpty] = kTopEarlgreyPlicPeripheralKmac,
   [kTopEarlgreyPlicIrqIdKmacKmacErr] = kTopEarlgreyPlicPeripheralKmac,
-  [kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone] = kTopEarlgreyPlicPeripheralOtpCtrl,
-  [kTopEarlgreyPlicIrqIdOtpCtrlOtpError] = kTopEarlgreyPlicPeripheralOtpCtrl,
+  [kTopEarlgreyPlicIrqIdKeymgrOpDone] = kTopEarlgreyPlicPeripheralKeymgr,
   [kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone] = kTopEarlgreyPlicPeripheralCsrng,
   [kTopEarlgreyPlicIrqIdCsrngCsEntropyReq] = kTopEarlgreyPlicPeripheralCsrng,
   [kTopEarlgreyPlicIrqIdCsrngCsHwInstExc] = kTopEarlgreyPlicPeripheralCsrng,
   [kTopEarlgreyPlicIrqIdCsrngCsFatalErr] = kTopEarlgreyPlicPeripheralCsrng,
+  [kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid] = kTopEarlgreyPlicPeripheralEntropySrc,
+  [kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed] = kTopEarlgreyPlicPeripheralEntropySrc,
+  [kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr] = kTopEarlgreyPlicPeripheralEntropySrc,
   [kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone] = kTopEarlgreyPlicPeripheralEdn0,
   [kTopEarlgreyPlicIrqIdEdn0EdnFatalErr] = kTopEarlgreyPlicPeripheralEdn0,
   [kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone] = kTopEarlgreyPlicPeripheralEdn1,
   [kTopEarlgreyPlicIrqIdEdn1EdnFatalErr] = kTopEarlgreyPlicPeripheralEdn1,
-  [kTopEarlgreyPlicIrqIdAonTimerAonWkupTimerExpired] = kTopEarlgreyPlicPeripheralAonTimerAon,
-  [kTopEarlgreyPlicIrqIdAonTimerAonWdogTimerBark] = kTopEarlgreyPlicPeripheralAonTimerAon,
-  [kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid] = kTopEarlgreyPlicPeripheralEntropySrc,
-  [kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed] = kTopEarlgreyPlicPeripheralEntropySrc,
-  [kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr] = kTopEarlgreyPlicPeripheralEntropySrc,
+  [kTopEarlgreyPlicIrqIdOtbnDone] = kTopEarlgreyPlicPeripheralOtbn,
 };
 
 
@@ -194,10 +199,10 @@
  */
 const top_earlgrey_alert_peripheral_t
     top_earlgrey_alert_for_peripheral[29] = {
-  [kTopEarlgreyAlertIdAesRecovCtrlUpdateErr] = kTopEarlgreyAlertPeripheralAes,
-  [kTopEarlgreyAlertIdAesFatalFault] = kTopEarlgreyAlertPeripheralAes,
-  [kTopEarlgreyAlertIdOtbnFatal] = kTopEarlgreyAlertPeripheralOtbn,
-  [kTopEarlgreyAlertIdOtbnRecov] = kTopEarlgreyAlertPeripheralOtbn,
+  [kTopEarlgreyAlertIdOtpCtrlFatalMacroError] = kTopEarlgreyAlertPeripheralOtpCtrl,
+  [kTopEarlgreyAlertIdOtpCtrlFatalCheckError] = kTopEarlgreyAlertPeripheralOtpCtrl,
+  [kTopEarlgreyAlertIdLcCtrlFatalProgError] = kTopEarlgreyAlertPeripheralLcCtrl,
+  [kTopEarlgreyAlertIdLcCtrlFatalStateError] = kTopEarlgreyAlertPeripheralLcCtrl,
   [kTopEarlgreyAlertIdSensorCtrlAonRecovAs] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
   [kTopEarlgreyAlertIdSensorCtrlAonRecovCg] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
   [kTopEarlgreyAlertIdSensorCtrlAonRecovGd] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
@@ -205,23 +210,23 @@
   [kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
   [kTopEarlgreyAlertIdSensorCtrlAonRecovLs] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
   [kTopEarlgreyAlertIdSensorCtrlAonRecovOt] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
-  [kTopEarlgreyAlertIdKeymgrFatalFaultErr] = kTopEarlgreyAlertPeripheralKeymgr,
-  [kTopEarlgreyAlertIdKeymgrRecovOperationErr] = kTopEarlgreyAlertPeripheralKeymgr,
-  [kTopEarlgreyAlertIdOtpCtrlFatalMacroError] = kTopEarlgreyAlertPeripheralOtpCtrl,
-  [kTopEarlgreyAlertIdOtpCtrlFatalCheckError] = kTopEarlgreyAlertPeripheralOtpCtrl,
-  [kTopEarlgreyAlertIdLcCtrlFatalProgError] = kTopEarlgreyAlertPeripheralLcCtrl,
-  [kTopEarlgreyAlertIdLcCtrlFatalStateError] = kTopEarlgreyAlertPeripheralLcCtrl,
-  [kTopEarlgreyAlertIdEntropySrcRecovAlert] = kTopEarlgreyAlertPeripheralEntropySrc,
-  [kTopEarlgreyAlertIdEntropySrcFatalAlert] = kTopEarlgreyAlertPeripheralEntropySrc,
-  [kTopEarlgreyAlertIdCsrngFatalAlert] = kTopEarlgreyAlertPeripheralCsrng,
-  [kTopEarlgreyAlertIdEdn0FatalAlert] = kTopEarlgreyAlertPeripheralEdn0,
-  [kTopEarlgreyAlertIdEdn1FatalAlert] = kTopEarlgreyAlertPeripheralEdn1,
-  [kTopEarlgreyAlertIdSramCtrlMainFatalIntgError] = kTopEarlgreyAlertPeripheralSramCtrlMain,
-  [kTopEarlgreyAlertIdSramCtrlMainFatalParityError] = kTopEarlgreyAlertPeripheralSramCtrlMain,
   [kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError] = kTopEarlgreyAlertPeripheralSramCtrlRetAon,
   [kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError] = kTopEarlgreyAlertPeripheralSramCtrlRetAon,
   [kTopEarlgreyAlertIdFlashCtrlRecovErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
   [kTopEarlgreyAlertIdFlashCtrlRecovMpErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
   [kTopEarlgreyAlertIdFlashCtrlRecovEccErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
+  [kTopEarlgreyAlertIdAesRecovCtrlUpdateErr] = kTopEarlgreyAlertPeripheralAes,
+  [kTopEarlgreyAlertIdAesFatalFault] = kTopEarlgreyAlertPeripheralAes,
+  [kTopEarlgreyAlertIdKeymgrFatalFaultErr] = kTopEarlgreyAlertPeripheralKeymgr,
+  [kTopEarlgreyAlertIdKeymgrRecovOperationErr] = kTopEarlgreyAlertPeripheralKeymgr,
+  [kTopEarlgreyAlertIdCsrngFatalAlert] = kTopEarlgreyAlertPeripheralCsrng,
+  [kTopEarlgreyAlertIdEntropySrcRecovAlert] = kTopEarlgreyAlertPeripheralEntropySrc,
+  [kTopEarlgreyAlertIdEntropySrcFatalAlert] = kTopEarlgreyAlertPeripheralEntropySrc,
+  [kTopEarlgreyAlertIdEdn0FatalAlert] = kTopEarlgreyAlertPeripheralEdn0,
+  [kTopEarlgreyAlertIdEdn1FatalAlert] = kTopEarlgreyAlertPeripheralEdn1,
+  [kTopEarlgreyAlertIdSramCtrlMainFatalIntgError] = kTopEarlgreyAlertPeripheralSramCtrlMain,
+  [kTopEarlgreyAlertIdSramCtrlMainFatalParityError] = kTopEarlgreyAlertPeripheralSramCtrlMain,
+  [kTopEarlgreyAlertIdOtbnFatal] = kTopEarlgreyAlertPeripheralOtbn,
+  [kTopEarlgreyAlertIdOtbnRecov] = kTopEarlgreyAlertPeripheralOtbn,
 };
 
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index be92a98..069ba70 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -747,25 +747,28 @@
   kTopEarlgreyPlicPeripheralUart3 = 4, /**< uart3 */
   kTopEarlgreyPlicPeripheralGpio = 5, /**< gpio */
   kTopEarlgreyPlicPeripheralSpiDevice = 6, /**< spi_device */
-  kTopEarlgreyPlicPeripheralI2c0 = 7, /**< i2c0 */
-  kTopEarlgreyPlicPeripheralI2c1 = 8, /**< i2c1 */
-  kTopEarlgreyPlicPeripheralI2c2 = 9, /**< i2c2 */
-  kTopEarlgreyPlicPeripheralPattgen = 10, /**< pattgen */
-  kTopEarlgreyPlicPeripheralFlashCtrl = 11, /**< flash_ctrl */
-  kTopEarlgreyPlicPeripheralHmac = 12, /**< hmac */
-  kTopEarlgreyPlicPeripheralAlertHandler = 13, /**< alert_handler */
+  kTopEarlgreyPlicPeripheralSpiHost0 = 7, /**< spi_host0 */
+  kTopEarlgreyPlicPeripheralSpiHost1 = 8, /**< spi_host1 */
+  kTopEarlgreyPlicPeripheralI2c0 = 9, /**< i2c0 */
+  kTopEarlgreyPlicPeripheralI2c1 = 10, /**< i2c1 */
+  kTopEarlgreyPlicPeripheralI2c2 = 11, /**< i2c2 */
+  kTopEarlgreyPlicPeripheralPattgen = 12, /**< pattgen */
+  kTopEarlgreyPlicPeripheralRvTimer = 13, /**< rv_timer */
   kTopEarlgreyPlicPeripheralUsbdev = 14, /**< usbdev */
-  kTopEarlgreyPlicPeripheralPwrmgrAon = 15, /**< pwrmgr_aon */
-  kTopEarlgreyPlicPeripheralOtbn = 16, /**< otbn */
-  kTopEarlgreyPlicPeripheralKeymgr = 17, /**< keymgr */
-  kTopEarlgreyPlicPeripheralKmac = 18, /**< kmac */
-  kTopEarlgreyPlicPeripheralOtpCtrl = 19, /**< otp_ctrl */
-  kTopEarlgreyPlicPeripheralCsrng = 20, /**< csrng */
-  kTopEarlgreyPlicPeripheralEdn0 = 21, /**< edn0 */
-  kTopEarlgreyPlicPeripheralEdn1 = 22, /**< edn1 */
-  kTopEarlgreyPlicPeripheralAonTimerAon = 23, /**< aon_timer_aon */
+  kTopEarlgreyPlicPeripheralOtpCtrl = 15, /**< otp_ctrl */
+  kTopEarlgreyPlicPeripheralAlertHandler = 16, /**< alert_handler */
+  kTopEarlgreyPlicPeripheralPwrmgrAon = 17, /**< pwrmgr_aon */
+  kTopEarlgreyPlicPeripheralAonTimerAon = 18, /**< aon_timer_aon */
+  kTopEarlgreyPlicPeripheralFlashCtrl = 19, /**< flash_ctrl */
+  kTopEarlgreyPlicPeripheralHmac = 20, /**< hmac */
+  kTopEarlgreyPlicPeripheralKmac = 21, /**< kmac */
+  kTopEarlgreyPlicPeripheralKeymgr = 22, /**< keymgr */
+  kTopEarlgreyPlicPeripheralCsrng = 23, /**< csrng */
   kTopEarlgreyPlicPeripheralEntropySrc = 24, /**< entropy_src */
-  kTopEarlgreyPlicPeripheralLast = 24, /**< \internal Final PLIC peripheral */
+  kTopEarlgreyPlicPeripheralEdn0 = 25, /**< edn0 */
+  kTopEarlgreyPlicPeripheralEdn1 = 26, /**< edn1 */
+  kTopEarlgreyPlicPeripheralOtbn = 27, /**< otbn */
+  kTopEarlgreyPlicPeripheralLast = 27, /**< \internal Final PLIC peripheral */
 } top_earlgrey_plic_peripheral_t;
 
 /**
@@ -846,107 +849,112 @@
   kTopEarlgreyPlicIrqIdSpiDeviceRxerr = 68, /**< spi_device_rxerr */
   kTopEarlgreyPlicIrqIdSpiDeviceRxoverflow = 69, /**< spi_device_rxoverflow */
   kTopEarlgreyPlicIrqIdSpiDeviceTxunderflow = 70, /**< spi_device_txunderflow */
-  kTopEarlgreyPlicIrqIdI2c0FmtWatermark = 71, /**< i2c0_fmt_watermark */
-  kTopEarlgreyPlicIrqIdI2c0RxWatermark = 72, /**< i2c0_rx_watermark */
-  kTopEarlgreyPlicIrqIdI2c0FmtOverflow = 73, /**< i2c0_fmt_overflow */
-  kTopEarlgreyPlicIrqIdI2c0RxOverflow = 74, /**< i2c0_rx_overflow */
-  kTopEarlgreyPlicIrqIdI2c0Nak = 75, /**< i2c0_nak */
-  kTopEarlgreyPlicIrqIdI2c0SclInterference = 76, /**< i2c0_scl_interference */
-  kTopEarlgreyPlicIrqIdI2c0SdaInterference = 77, /**< i2c0_sda_interference */
-  kTopEarlgreyPlicIrqIdI2c0StretchTimeout = 78, /**< i2c0_stretch_timeout */
-  kTopEarlgreyPlicIrqIdI2c0SdaUnstable = 79, /**< i2c0_sda_unstable */
-  kTopEarlgreyPlicIrqIdI2c0TransComplete = 80, /**< i2c0_trans_complete */
-  kTopEarlgreyPlicIrqIdI2c0TxEmpty = 81, /**< i2c0_tx_empty */
-  kTopEarlgreyPlicIrqIdI2c0TxNonempty = 82, /**< i2c0_tx_nonempty */
-  kTopEarlgreyPlicIrqIdI2c0TxOverflow = 83, /**< i2c0_tx_overflow */
-  kTopEarlgreyPlicIrqIdI2c0AcqOverflow = 84, /**< i2c0_acq_overflow */
-  kTopEarlgreyPlicIrqIdI2c0AckStop = 85, /**< i2c0_ack_stop */
-  kTopEarlgreyPlicIrqIdI2c0HostTimeout = 86, /**< i2c0_host_timeout */
-  kTopEarlgreyPlicIrqIdI2c1FmtWatermark = 87, /**< i2c1_fmt_watermark */
-  kTopEarlgreyPlicIrqIdI2c1RxWatermark = 88, /**< i2c1_rx_watermark */
-  kTopEarlgreyPlicIrqIdI2c1FmtOverflow = 89, /**< i2c1_fmt_overflow */
-  kTopEarlgreyPlicIrqIdI2c1RxOverflow = 90, /**< i2c1_rx_overflow */
-  kTopEarlgreyPlicIrqIdI2c1Nak = 91, /**< i2c1_nak */
-  kTopEarlgreyPlicIrqIdI2c1SclInterference = 92, /**< i2c1_scl_interference */
-  kTopEarlgreyPlicIrqIdI2c1SdaInterference = 93, /**< i2c1_sda_interference */
-  kTopEarlgreyPlicIrqIdI2c1StretchTimeout = 94, /**< i2c1_stretch_timeout */
-  kTopEarlgreyPlicIrqIdI2c1SdaUnstable = 95, /**< i2c1_sda_unstable */
-  kTopEarlgreyPlicIrqIdI2c1TransComplete = 96, /**< i2c1_trans_complete */
-  kTopEarlgreyPlicIrqIdI2c1TxEmpty = 97, /**< i2c1_tx_empty */
-  kTopEarlgreyPlicIrqIdI2c1TxNonempty = 98, /**< i2c1_tx_nonempty */
-  kTopEarlgreyPlicIrqIdI2c1TxOverflow = 99, /**< i2c1_tx_overflow */
-  kTopEarlgreyPlicIrqIdI2c1AcqOverflow = 100, /**< i2c1_acq_overflow */
-  kTopEarlgreyPlicIrqIdI2c1AckStop = 101, /**< i2c1_ack_stop */
-  kTopEarlgreyPlicIrqIdI2c1HostTimeout = 102, /**< i2c1_host_timeout */
-  kTopEarlgreyPlicIrqIdI2c2FmtWatermark = 103, /**< i2c2_fmt_watermark */
-  kTopEarlgreyPlicIrqIdI2c2RxWatermark = 104, /**< i2c2_rx_watermark */
-  kTopEarlgreyPlicIrqIdI2c2FmtOverflow = 105, /**< i2c2_fmt_overflow */
-  kTopEarlgreyPlicIrqIdI2c2RxOverflow = 106, /**< i2c2_rx_overflow */
-  kTopEarlgreyPlicIrqIdI2c2Nak = 107, /**< i2c2_nak */
-  kTopEarlgreyPlicIrqIdI2c2SclInterference = 108, /**< i2c2_scl_interference */
-  kTopEarlgreyPlicIrqIdI2c2SdaInterference = 109, /**< i2c2_sda_interference */
-  kTopEarlgreyPlicIrqIdI2c2StretchTimeout = 110, /**< i2c2_stretch_timeout */
-  kTopEarlgreyPlicIrqIdI2c2SdaUnstable = 111, /**< i2c2_sda_unstable */
-  kTopEarlgreyPlicIrqIdI2c2TransComplete = 112, /**< i2c2_trans_complete */
-  kTopEarlgreyPlicIrqIdI2c2TxEmpty = 113, /**< i2c2_tx_empty */
-  kTopEarlgreyPlicIrqIdI2c2TxNonempty = 114, /**< i2c2_tx_nonempty */
-  kTopEarlgreyPlicIrqIdI2c2TxOverflow = 115, /**< i2c2_tx_overflow */
-  kTopEarlgreyPlicIrqIdI2c2AcqOverflow = 116, /**< i2c2_acq_overflow */
-  kTopEarlgreyPlicIrqIdI2c2AckStop = 117, /**< i2c2_ack_stop */
-  kTopEarlgreyPlicIrqIdI2c2HostTimeout = 118, /**< i2c2_host_timeout */
-  kTopEarlgreyPlicIrqIdPattgenDoneCh0 = 119, /**< pattgen_done_ch0 */
-  kTopEarlgreyPlicIrqIdPattgenDoneCh1 = 120, /**< pattgen_done_ch1 */
-  kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty = 121, /**< flash_ctrl_prog_empty */
-  kTopEarlgreyPlicIrqIdFlashCtrlProgLvl = 122, /**< flash_ctrl_prog_lvl */
-  kTopEarlgreyPlicIrqIdFlashCtrlRdFull = 123, /**< flash_ctrl_rd_full */
-  kTopEarlgreyPlicIrqIdFlashCtrlRdLvl = 124, /**< flash_ctrl_rd_lvl */
-  kTopEarlgreyPlicIrqIdFlashCtrlOpDone = 125, /**< flash_ctrl_op_done */
-  kTopEarlgreyPlicIrqIdHmacHmacDone = 126, /**< hmac_hmac_done */
-  kTopEarlgreyPlicIrqIdHmacFifoEmpty = 127, /**< hmac_fifo_empty */
-  kTopEarlgreyPlicIrqIdHmacHmacErr = 128, /**< hmac_hmac_err */
-  kTopEarlgreyPlicIrqIdAlertHandlerClassa = 129, /**< alert_handler_classa */
-  kTopEarlgreyPlicIrqIdAlertHandlerClassb = 130, /**< alert_handler_classb */
-  kTopEarlgreyPlicIrqIdAlertHandlerClassc = 131, /**< alert_handler_classc */
-  kTopEarlgreyPlicIrqIdAlertHandlerClassd = 132, /**< alert_handler_classd */
-  kTopEarlgreyPlicIrqIdUsbdevPktReceived = 133, /**< usbdev_pkt_received */
-  kTopEarlgreyPlicIrqIdUsbdevPktSent = 134, /**< usbdev_pkt_sent */
-  kTopEarlgreyPlicIrqIdUsbdevDisconnected = 135, /**< usbdev_disconnected */
-  kTopEarlgreyPlicIrqIdUsbdevHostLost = 136, /**< usbdev_host_lost */
-  kTopEarlgreyPlicIrqIdUsbdevLinkReset = 137, /**< usbdev_link_reset */
-  kTopEarlgreyPlicIrqIdUsbdevLinkSuspend = 138, /**< usbdev_link_suspend */
-  kTopEarlgreyPlicIrqIdUsbdevLinkResume = 139, /**< usbdev_link_resume */
-  kTopEarlgreyPlicIrqIdUsbdevAvEmpty = 140, /**< usbdev_av_empty */
-  kTopEarlgreyPlicIrqIdUsbdevRxFull = 141, /**< usbdev_rx_full */
-  kTopEarlgreyPlicIrqIdUsbdevAvOverflow = 142, /**< usbdev_av_overflow */
-  kTopEarlgreyPlicIrqIdUsbdevLinkInErr = 143, /**< usbdev_link_in_err */
-  kTopEarlgreyPlicIrqIdUsbdevRxCrcErr = 144, /**< usbdev_rx_crc_err */
-  kTopEarlgreyPlicIrqIdUsbdevRxPidErr = 145, /**< usbdev_rx_pid_err */
-  kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr = 146, /**< usbdev_rx_bitstuff_err */
-  kTopEarlgreyPlicIrqIdUsbdevFrame = 147, /**< usbdev_frame */
-  kTopEarlgreyPlicIrqIdUsbdevConnected = 148, /**< usbdev_connected */
-  kTopEarlgreyPlicIrqIdUsbdevLinkOutErr = 149, /**< usbdev_link_out_err */
-  kTopEarlgreyPlicIrqIdPwrmgrAonWakeup = 150, /**< pwrmgr_aon_wakeup */
-  kTopEarlgreyPlicIrqIdOtbnDone = 151, /**< otbn_done */
-  kTopEarlgreyPlicIrqIdKeymgrOpDone = 152, /**< keymgr_op_done */
-  kTopEarlgreyPlicIrqIdKmacKmacDone = 153, /**< kmac_kmac_done */
-  kTopEarlgreyPlicIrqIdKmacFifoEmpty = 154, /**< kmac_fifo_empty */
-  kTopEarlgreyPlicIrqIdKmacKmacErr = 155, /**< kmac_kmac_err */
-  kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone = 156, /**< otp_ctrl_otp_operation_done */
-  kTopEarlgreyPlicIrqIdOtpCtrlOtpError = 157, /**< otp_ctrl_otp_error */
-  kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 158, /**< csrng_cs_cmd_req_done */
-  kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 159, /**< csrng_cs_entropy_req */
-  kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 160, /**< csrng_cs_hw_inst_exc */
-  kTopEarlgreyPlicIrqIdCsrngCsFatalErr = 161, /**< csrng_cs_fatal_err */
-  kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 162, /**< edn0_edn_cmd_req_done */
-  kTopEarlgreyPlicIrqIdEdn0EdnFatalErr = 163, /**< edn0_edn_fatal_err */
-  kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 164, /**< edn1_edn_cmd_req_done */
-  kTopEarlgreyPlicIrqIdEdn1EdnFatalErr = 165, /**< edn1_edn_fatal_err */
-  kTopEarlgreyPlicIrqIdAonTimerAonWkupTimerExpired = 166, /**< aon_timer_aon_wkup_timer_expired */
-  kTopEarlgreyPlicIrqIdAonTimerAonWdogTimerBark = 167, /**< aon_timer_aon_wdog_timer_bark */
+  kTopEarlgreyPlicIrqIdSpiHost0Error = 71, /**< spi_host0_error */
+  kTopEarlgreyPlicIrqIdSpiHost0SpiEvent = 72, /**< spi_host0_spi_event */
+  kTopEarlgreyPlicIrqIdSpiHost1Error = 73, /**< spi_host1_error */
+  kTopEarlgreyPlicIrqIdSpiHost1SpiEvent = 74, /**< spi_host1_spi_event */
+  kTopEarlgreyPlicIrqIdI2c0FmtWatermark = 75, /**< i2c0_fmt_watermark */
+  kTopEarlgreyPlicIrqIdI2c0RxWatermark = 76, /**< i2c0_rx_watermark */
+  kTopEarlgreyPlicIrqIdI2c0FmtOverflow = 77, /**< i2c0_fmt_overflow */
+  kTopEarlgreyPlicIrqIdI2c0RxOverflow = 78, /**< i2c0_rx_overflow */
+  kTopEarlgreyPlicIrqIdI2c0Nak = 79, /**< i2c0_nak */
+  kTopEarlgreyPlicIrqIdI2c0SclInterference = 80, /**< i2c0_scl_interference */
+  kTopEarlgreyPlicIrqIdI2c0SdaInterference = 81, /**< i2c0_sda_interference */
+  kTopEarlgreyPlicIrqIdI2c0StretchTimeout = 82, /**< i2c0_stretch_timeout */
+  kTopEarlgreyPlicIrqIdI2c0SdaUnstable = 83, /**< i2c0_sda_unstable */
+  kTopEarlgreyPlicIrqIdI2c0TransComplete = 84, /**< i2c0_trans_complete */
+  kTopEarlgreyPlicIrqIdI2c0TxEmpty = 85, /**< i2c0_tx_empty */
+  kTopEarlgreyPlicIrqIdI2c0TxNonempty = 86, /**< i2c0_tx_nonempty */
+  kTopEarlgreyPlicIrqIdI2c0TxOverflow = 87, /**< i2c0_tx_overflow */
+  kTopEarlgreyPlicIrqIdI2c0AcqOverflow = 88, /**< i2c0_acq_overflow */
+  kTopEarlgreyPlicIrqIdI2c0AckStop = 89, /**< i2c0_ack_stop */
+  kTopEarlgreyPlicIrqIdI2c0HostTimeout = 90, /**< i2c0_host_timeout */
+  kTopEarlgreyPlicIrqIdI2c1FmtWatermark = 91, /**< i2c1_fmt_watermark */
+  kTopEarlgreyPlicIrqIdI2c1RxWatermark = 92, /**< i2c1_rx_watermark */
+  kTopEarlgreyPlicIrqIdI2c1FmtOverflow = 93, /**< i2c1_fmt_overflow */
+  kTopEarlgreyPlicIrqIdI2c1RxOverflow = 94, /**< i2c1_rx_overflow */
+  kTopEarlgreyPlicIrqIdI2c1Nak = 95, /**< i2c1_nak */
+  kTopEarlgreyPlicIrqIdI2c1SclInterference = 96, /**< i2c1_scl_interference */
+  kTopEarlgreyPlicIrqIdI2c1SdaInterference = 97, /**< i2c1_sda_interference */
+  kTopEarlgreyPlicIrqIdI2c1StretchTimeout = 98, /**< i2c1_stretch_timeout */
+  kTopEarlgreyPlicIrqIdI2c1SdaUnstable = 99, /**< i2c1_sda_unstable */
+  kTopEarlgreyPlicIrqIdI2c1TransComplete = 100, /**< i2c1_trans_complete */
+  kTopEarlgreyPlicIrqIdI2c1TxEmpty = 101, /**< i2c1_tx_empty */
+  kTopEarlgreyPlicIrqIdI2c1TxNonempty = 102, /**< i2c1_tx_nonempty */
+  kTopEarlgreyPlicIrqIdI2c1TxOverflow = 103, /**< i2c1_tx_overflow */
+  kTopEarlgreyPlicIrqIdI2c1AcqOverflow = 104, /**< i2c1_acq_overflow */
+  kTopEarlgreyPlicIrqIdI2c1AckStop = 105, /**< i2c1_ack_stop */
+  kTopEarlgreyPlicIrqIdI2c1HostTimeout = 106, /**< i2c1_host_timeout */
+  kTopEarlgreyPlicIrqIdI2c2FmtWatermark = 107, /**< i2c2_fmt_watermark */
+  kTopEarlgreyPlicIrqIdI2c2RxWatermark = 108, /**< i2c2_rx_watermark */
+  kTopEarlgreyPlicIrqIdI2c2FmtOverflow = 109, /**< i2c2_fmt_overflow */
+  kTopEarlgreyPlicIrqIdI2c2RxOverflow = 110, /**< i2c2_rx_overflow */
+  kTopEarlgreyPlicIrqIdI2c2Nak = 111, /**< i2c2_nak */
+  kTopEarlgreyPlicIrqIdI2c2SclInterference = 112, /**< i2c2_scl_interference */
+  kTopEarlgreyPlicIrqIdI2c2SdaInterference = 113, /**< i2c2_sda_interference */
+  kTopEarlgreyPlicIrqIdI2c2StretchTimeout = 114, /**< i2c2_stretch_timeout */
+  kTopEarlgreyPlicIrqIdI2c2SdaUnstable = 115, /**< i2c2_sda_unstable */
+  kTopEarlgreyPlicIrqIdI2c2TransComplete = 116, /**< i2c2_trans_complete */
+  kTopEarlgreyPlicIrqIdI2c2TxEmpty = 117, /**< i2c2_tx_empty */
+  kTopEarlgreyPlicIrqIdI2c2TxNonempty = 118, /**< i2c2_tx_nonempty */
+  kTopEarlgreyPlicIrqIdI2c2TxOverflow = 119, /**< i2c2_tx_overflow */
+  kTopEarlgreyPlicIrqIdI2c2AcqOverflow = 120, /**< i2c2_acq_overflow */
+  kTopEarlgreyPlicIrqIdI2c2AckStop = 121, /**< i2c2_ack_stop */
+  kTopEarlgreyPlicIrqIdI2c2HostTimeout = 122, /**< i2c2_host_timeout */
+  kTopEarlgreyPlicIrqIdPattgenDoneCh0 = 123, /**< pattgen_done_ch0 */
+  kTopEarlgreyPlicIrqIdPattgenDoneCh1 = 124, /**< pattgen_done_ch1 */
+  kTopEarlgreyPlicIrqIdRvTimerTimerExpired0_0 = 125, /**< rv_timer_timer_expired_0_0 */
+  kTopEarlgreyPlicIrqIdUsbdevPktReceived = 126, /**< usbdev_pkt_received */
+  kTopEarlgreyPlicIrqIdUsbdevPktSent = 127, /**< usbdev_pkt_sent */
+  kTopEarlgreyPlicIrqIdUsbdevDisconnected = 128, /**< usbdev_disconnected */
+  kTopEarlgreyPlicIrqIdUsbdevHostLost = 129, /**< usbdev_host_lost */
+  kTopEarlgreyPlicIrqIdUsbdevLinkReset = 130, /**< usbdev_link_reset */
+  kTopEarlgreyPlicIrqIdUsbdevLinkSuspend = 131, /**< usbdev_link_suspend */
+  kTopEarlgreyPlicIrqIdUsbdevLinkResume = 132, /**< usbdev_link_resume */
+  kTopEarlgreyPlicIrqIdUsbdevAvEmpty = 133, /**< usbdev_av_empty */
+  kTopEarlgreyPlicIrqIdUsbdevRxFull = 134, /**< usbdev_rx_full */
+  kTopEarlgreyPlicIrqIdUsbdevAvOverflow = 135, /**< usbdev_av_overflow */
+  kTopEarlgreyPlicIrqIdUsbdevLinkInErr = 136, /**< usbdev_link_in_err */
+  kTopEarlgreyPlicIrqIdUsbdevRxCrcErr = 137, /**< usbdev_rx_crc_err */
+  kTopEarlgreyPlicIrqIdUsbdevRxPidErr = 138, /**< usbdev_rx_pid_err */
+  kTopEarlgreyPlicIrqIdUsbdevRxBitstuffErr = 139, /**< usbdev_rx_bitstuff_err */
+  kTopEarlgreyPlicIrqIdUsbdevFrame = 140, /**< usbdev_frame */
+  kTopEarlgreyPlicIrqIdUsbdevConnected = 141, /**< usbdev_connected */
+  kTopEarlgreyPlicIrqIdUsbdevLinkOutErr = 142, /**< usbdev_link_out_err */
+  kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone = 143, /**< otp_ctrl_otp_operation_done */
+  kTopEarlgreyPlicIrqIdOtpCtrlOtpError = 144, /**< otp_ctrl_otp_error */
+  kTopEarlgreyPlicIrqIdAlertHandlerClassa = 145, /**< alert_handler_classa */
+  kTopEarlgreyPlicIrqIdAlertHandlerClassb = 146, /**< alert_handler_classb */
+  kTopEarlgreyPlicIrqIdAlertHandlerClassc = 147, /**< alert_handler_classc */
+  kTopEarlgreyPlicIrqIdAlertHandlerClassd = 148, /**< alert_handler_classd */
+  kTopEarlgreyPlicIrqIdPwrmgrAonWakeup = 149, /**< pwrmgr_aon_wakeup */
+  kTopEarlgreyPlicIrqIdAonTimerAonWkupTimerExpired = 150, /**< aon_timer_aon_wkup_timer_expired */
+  kTopEarlgreyPlicIrqIdAonTimerAonWdogTimerBark = 151, /**< aon_timer_aon_wdog_timer_bark */
+  kTopEarlgreyPlicIrqIdFlashCtrlProgEmpty = 152, /**< flash_ctrl_prog_empty */
+  kTopEarlgreyPlicIrqIdFlashCtrlProgLvl = 153, /**< flash_ctrl_prog_lvl */
+  kTopEarlgreyPlicIrqIdFlashCtrlRdFull = 154, /**< flash_ctrl_rd_full */
+  kTopEarlgreyPlicIrqIdFlashCtrlRdLvl = 155, /**< flash_ctrl_rd_lvl */
+  kTopEarlgreyPlicIrqIdFlashCtrlOpDone = 156, /**< flash_ctrl_op_done */
+  kTopEarlgreyPlicIrqIdHmacHmacDone = 157, /**< hmac_hmac_done */
+  kTopEarlgreyPlicIrqIdHmacFifoEmpty = 158, /**< hmac_fifo_empty */
+  kTopEarlgreyPlicIrqIdHmacHmacErr = 159, /**< hmac_hmac_err */
+  kTopEarlgreyPlicIrqIdKmacKmacDone = 160, /**< kmac_kmac_done */
+  kTopEarlgreyPlicIrqIdKmacFifoEmpty = 161, /**< kmac_fifo_empty */
+  kTopEarlgreyPlicIrqIdKmacKmacErr = 162, /**< kmac_kmac_err */
+  kTopEarlgreyPlicIrqIdKeymgrOpDone = 163, /**< keymgr_op_done */
+  kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 164, /**< csrng_cs_cmd_req_done */
+  kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 165, /**< csrng_cs_entropy_req */
+  kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 166, /**< csrng_cs_hw_inst_exc */
+  kTopEarlgreyPlicIrqIdCsrngCsFatalErr = 167, /**< csrng_cs_fatal_err */
   kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 168, /**< entropy_src_es_entropy_valid */
   kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 169, /**< entropy_src_es_health_test_failed */
   kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 170, /**< entropy_src_es_fatal_err */
-  kTopEarlgreyPlicIrqIdLast = 170, /**< \internal The Last Valid Interrupt ID. */
+  kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 171, /**< edn0_edn_cmd_req_done */
+  kTopEarlgreyPlicIrqIdEdn0EdnFatalErr = 172, /**< edn0_edn_fatal_err */
+  kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 173, /**< edn1_edn_cmd_req_done */
+  kTopEarlgreyPlicIrqIdEdn1EdnFatalErr = 174, /**< edn1_edn_fatal_err */
+  kTopEarlgreyPlicIrqIdOtbnDone = 175, /**< otbn_done */
+  kTopEarlgreyPlicIrqIdLast = 175, /**< \internal The Last Valid Interrupt ID. */
 } top_earlgrey_plic_irq_id_t;
 
 /**
@@ -956,7 +964,7 @@
  * `top_earlgrey_plic_peripheral_t`.
  */
 extern const top_earlgrey_plic_peripheral_t
-    top_earlgrey_plic_interrupt_for_peripheral[171];
+    top_earlgrey_plic_interrupt_for_peripheral[176];
 
 /**
  * PLIC Interrupt Target.
@@ -976,19 +984,19 @@
  * alert.
  */
 typedef enum top_earlgrey_alert_peripheral {
-  kTopEarlgreyAlertPeripheralAes = 0, /**< aes */
-  kTopEarlgreyAlertPeripheralOtbn = 1, /**< otbn */
+  kTopEarlgreyAlertPeripheralOtpCtrl = 0, /**< otp_ctrl */
+  kTopEarlgreyAlertPeripheralLcCtrl = 1, /**< lc_ctrl */
   kTopEarlgreyAlertPeripheralSensorCtrlAon = 2, /**< sensor_ctrl_aon */
-  kTopEarlgreyAlertPeripheralKeymgr = 3, /**< keymgr */
-  kTopEarlgreyAlertPeripheralOtpCtrl = 4, /**< otp_ctrl */
-  kTopEarlgreyAlertPeripheralLcCtrl = 5, /**< lc_ctrl */
-  kTopEarlgreyAlertPeripheralEntropySrc = 6, /**< entropy_src */
+  kTopEarlgreyAlertPeripheralSramCtrlRetAon = 3, /**< sram_ctrl_ret_aon */
+  kTopEarlgreyAlertPeripheralFlashCtrl = 4, /**< flash_ctrl */
+  kTopEarlgreyAlertPeripheralAes = 5, /**< aes */
+  kTopEarlgreyAlertPeripheralKeymgr = 6, /**< keymgr */
   kTopEarlgreyAlertPeripheralCsrng = 7, /**< csrng */
-  kTopEarlgreyAlertPeripheralEdn0 = 8, /**< edn0 */
-  kTopEarlgreyAlertPeripheralEdn1 = 9, /**< edn1 */
-  kTopEarlgreyAlertPeripheralSramCtrlMain = 10, /**< sram_ctrl_main */
-  kTopEarlgreyAlertPeripheralSramCtrlRetAon = 11, /**< sram_ctrl_ret_aon */
-  kTopEarlgreyAlertPeripheralFlashCtrl = 12, /**< flash_ctrl */
+  kTopEarlgreyAlertPeripheralEntropySrc = 8, /**< entropy_src */
+  kTopEarlgreyAlertPeripheralEdn0 = 9, /**< edn0 */
+  kTopEarlgreyAlertPeripheralEdn1 = 10, /**< edn1 */
+  kTopEarlgreyAlertPeripheralSramCtrlMain = 11, /**< sram_ctrl_main */
+  kTopEarlgreyAlertPeripheralOtbn = 12, /**< otbn */
   kTopEarlgreyAlertPeripheralLast = 12, /**< \internal Final Alert peripheral */
 } top_earlgrey_alert_peripheral_t;
 
@@ -999,10 +1007,10 @@
  * the same peripheral are guaranteed to be consecutive.
  */
 typedef enum top_earlgrey_alert_id {
-  kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 0, /**< aes_recov_ctrl_update_err */
-  kTopEarlgreyAlertIdAesFatalFault = 1, /**< aes_fatal_fault */
-  kTopEarlgreyAlertIdOtbnFatal = 2, /**< otbn_fatal */
-  kTopEarlgreyAlertIdOtbnRecov = 3, /**< otbn_recov */
+  kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 0, /**< otp_ctrl_fatal_macro_error */
+  kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 1, /**< otp_ctrl_fatal_check_error */
+  kTopEarlgreyAlertIdLcCtrlFatalProgError = 2, /**< lc_ctrl_fatal_prog_error */
+  kTopEarlgreyAlertIdLcCtrlFatalStateError = 3, /**< lc_ctrl_fatal_state_error */
   kTopEarlgreyAlertIdSensorCtrlAonRecovAs = 4, /**< sensor_ctrl_aon_recov_as */
   kTopEarlgreyAlertIdSensorCtrlAonRecovCg = 5, /**< sensor_ctrl_aon_recov_cg */
   kTopEarlgreyAlertIdSensorCtrlAonRecovGd = 6, /**< sensor_ctrl_aon_recov_gd */
@@ -1010,24 +1018,24 @@
   kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo = 8, /**< sensor_ctrl_aon_recov_ts_lo */
   kTopEarlgreyAlertIdSensorCtrlAonRecovLs = 9, /**< sensor_ctrl_aon_recov_ls */
   kTopEarlgreyAlertIdSensorCtrlAonRecovOt = 10, /**< sensor_ctrl_aon_recov_ot */
-  kTopEarlgreyAlertIdKeymgrFatalFaultErr = 11, /**< keymgr_fatal_fault_err */
-  kTopEarlgreyAlertIdKeymgrRecovOperationErr = 12, /**< keymgr_recov_operation_err */
-  kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 13, /**< otp_ctrl_fatal_macro_error */
-  kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 14, /**< otp_ctrl_fatal_check_error */
-  kTopEarlgreyAlertIdLcCtrlFatalProgError = 15, /**< lc_ctrl_fatal_prog_error */
-  kTopEarlgreyAlertIdLcCtrlFatalStateError = 16, /**< lc_ctrl_fatal_state_error */
-  kTopEarlgreyAlertIdEntropySrcRecovAlert = 17, /**< entropy_src_recov_alert */
-  kTopEarlgreyAlertIdEntropySrcFatalAlert = 18, /**< entropy_src_fatal_alert */
-  kTopEarlgreyAlertIdCsrngFatalAlert = 19, /**< csrng_fatal_alert */
-  kTopEarlgreyAlertIdEdn0FatalAlert = 20, /**< edn0_fatal_alert */
-  kTopEarlgreyAlertIdEdn1FatalAlert = 21, /**< edn1_fatal_alert */
-  kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 22, /**< sram_ctrl_main_fatal_intg_error */
-  kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 23, /**< sram_ctrl_main_fatal_parity_error */
-  kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 24, /**< sram_ctrl_ret_aon_fatal_intg_error */
-  kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 25, /**< sram_ctrl_ret_aon_fatal_parity_error */
-  kTopEarlgreyAlertIdFlashCtrlRecovErr = 26, /**< flash_ctrl_recov_err */
-  kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 27, /**< flash_ctrl_recov_mp_err */
-  kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 28, /**< flash_ctrl_recov_ecc_err */
+  kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 11, /**< sram_ctrl_ret_aon_fatal_intg_error */
+  kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 12, /**< sram_ctrl_ret_aon_fatal_parity_error */
+  kTopEarlgreyAlertIdFlashCtrlRecovErr = 13, /**< flash_ctrl_recov_err */
+  kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 14, /**< flash_ctrl_recov_mp_err */
+  kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 15, /**< flash_ctrl_recov_ecc_err */
+  kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 16, /**< aes_recov_ctrl_update_err */
+  kTopEarlgreyAlertIdAesFatalFault = 17, /**< aes_fatal_fault */
+  kTopEarlgreyAlertIdKeymgrFatalFaultErr = 18, /**< keymgr_fatal_fault_err */
+  kTopEarlgreyAlertIdKeymgrRecovOperationErr = 19, /**< keymgr_recov_operation_err */
+  kTopEarlgreyAlertIdCsrngFatalAlert = 20, /**< csrng_fatal_alert */
+  kTopEarlgreyAlertIdEntropySrcRecovAlert = 21, /**< entropy_src_recov_alert */
+  kTopEarlgreyAlertIdEntropySrcFatalAlert = 22, /**< entropy_src_fatal_alert */
+  kTopEarlgreyAlertIdEdn0FatalAlert = 23, /**< edn0_fatal_alert */
+  kTopEarlgreyAlertIdEdn1FatalAlert = 24, /**< edn1_fatal_alert */
+  kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 25, /**< sram_ctrl_main_fatal_intg_error */
+  kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 26, /**< sram_ctrl_main_fatal_parity_error */
+  kTopEarlgreyAlertIdOtbnFatal = 27, /**< otbn_fatal */
+  kTopEarlgreyAlertIdOtbnRecov = 28, /**< otbn_recov */
   kTopEarlgreyAlertIdLast = 28, /**< \internal The Last Valid Alert ID. */
 } top_earlgrey_alert_id_t;
 
diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
index e93bbef..815e8fb 100644
--- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
+++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -694,14 +694,6 @@
   ],
 
   // ===== INTERRUPT CTRL =====================================================
-  // `rv_plic`  will be instantiate (need to be defined in `module` field
-  // If interrupt is not defined, it uses the order from the module list
-  // and include every modules.
-  // first item goes to LSB of the interrupt source
-  interrupt_module: ["uart0",
-                     "gpio", "spi_device",
-                     "flash_ctrl", "hmac", "alert_handler", "nmi_gen", "usbdev", "pwrmgr_aon"]
-
   // RV_PLIC has two searching algorithm internally to pick the most highest priority interrupt
   // source. "sequential" is smaller but slower, "matrix" is larger but faster.
   // Choose depends on the criteria. Currently it is set to "matrix" to meet FPGA timing @ 50MHz
@@ -711,14 +703,6 @@
   ]
 
   // ===== ALERT HANDLER ======================================================
-  // list all modules that expose alerts
-  // first item goes to LSB of the alert source
-  alert_module: [ "aes", "sensor_ctrl_aon", "lc_ctrl",
-                  "sram_ctrl_main", "sram_ctrl_ret_aon", "flash_ctrl"]
-
-  // generated list of alerts:
-  alert: [
-  ]
 
   // TODO: need to overhaul this datastructure.
   pinmux: {