tree ca18ebf1df9da3501639950836ca0b064957c2bf
parent e5c765423b0dd29a1df919cf44c604d0805d9f83
author Joshua Park <jeoong@google.com> 1659396373 -0700
committer tjaychen <timothytim@google.com> 1662747041 -0700

[pwrmgrr/|rstmgr] Moved fault_status regs into LC domain

Addresses #12284

Signed-off-by: Joshua Park <jeoong@google.com>

[PWRMGR/RSTMGR/REG_TOP] This PR is a fix to resolve the issue in PR #12284.

Fault status registers, error detection logics, and alert propagation logics are moved to LC domain.

pwrmgr : clk_esc_i and rst_esc_ni are renamed to clk_lc_i and rst_lc_ni
rstmgr : clk_i and rst_ni on por domain are changed to lc domain except scanmode sync logic, LC rstmgr_ctrl, and sys rstmgr_ctrl
reg_top : 1. err_q generation logic is moved to LC domain
          2. sync clock/reset are connected to corresponding registers

     sync:
            1. indicates the register needs to be on another
               clock/reset domain. The value shown here should
               correspond to one of the module's clocks.
            2. It can be configured in hjson in the same way as 'async'

DV files : clk_esc_i/rst_esc_ni are renamed to clk_lc_i and rst_lc_ni

Signed-off-by: Joshua Park <jeoong@google.com>

Moved alert_info back to POR domain

Moved alert_sender back to POR domain