tree 36c183ef66b22de9b4fea961c6c156e0de40f6c5
parent 990761c13c0c33cee77c20cd2330cc181daa75f4
author Michael Schaffner <msf@opentitan.org> 1579294656 -0800
committer Michael Schaffner <msf@google.com> 1579304610 -0800

[rv_plic] Work around sim/synth mismatch in Vivado

This works around a simulation synthesis mismatch that can be observed
in Vivado 2018.3 and 2019.2 (other versions have not been tested).

In particular, Vivado optimizes away the rv_plic_target module if the
ternary statements are present within the two generate loops. The
workaround consists of rewriting these MUX statements with bitwise ops
and assign statements.

The issue has been reported to Xilinx:
https://forums.xilinx.com/t5/Synthesis/Simulation-Synthesis-Mismatch-with-Vivado-2018-3/m-p/1065923#M33849

Signed-off-by: Michael Schaffner <msf@opentitan.org>