tree 501b4f6e8bd81797cc2d262effe7a6b0bca94433
parent cc159e919757a96b2ece03b1099139978e248380
author Rupert Swarbrick <rswarbrick@lowrisc.org> 1643874761 +0000
committer Rupert Swarbrick <rswarbrick@gmail.com> 1644325398 +0000

[otbn,dv] Fix assertion in RND FSM checking

If we are prefetching and a response comes in from the
EDN (edn_rnd_ack_i) at the same time as an instruction reads from
RND (rnd_req_i), we go to the "full" state, not the "reading" state.

The FSM I'd sketched out in the assertions was bogus: when both of
those signals are asserted at the same time, we can't go into both
READING and FULL states!

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>