diff --git a/hw/dv/sv/cip_lib/cip_base_env_cov.sv b/hw/dv/sv/cip_lib/cip_base_env_cov.sv
index c4f7768..0e33e9c 100644
--- a/hw/dv/sv/cip_lib/cip_base_env_cov.sv
+++ b/hw/dv/sv/cip_lib/cip_base_env_cov.sv
@@ -34,7 +34,8 @@
   }
 endgroup
 
-covergroup intr_pins_cg (uint num_interrupts) with function sample(uint intr_pin, bit intr_pin_value);
+covergroup intr_pins_cg (uint num_interrupts) with function sample(uint intr_pin,
+                                                                   bit  intr_pin_value);
   cp_intr_pin: coverpoint intr_pin {
     bins all_pins[] = {[0:num_interrupts-1]};
   }
@@ -59,8 +60,8 @@
   intr_pins_cg   intr_pins_cg;
   alert_cg       alert_cg;
   // Coverage for sticky interrupt functionality described in CIP specification
-  // As some interrupts are non-sticky, this covergroup should be populated on "as and when needed" basis
-  // in extended <ip>_env_cov class for interrupt types that are sticky
+  // As some interrupts are non-sticky, this covergroup should be populated on "as and when needed"
+  // basis in extended <ip>_env_cov class for interrupt types that are sticky
   dv_base_generic_cov_obj sticky_intr_cov[string];
 
   `uvm_component_new
diff --git a/hw/dv/sv/sw_msg_monitor_if/sw_msg_monitor_if.sv b/hw/dv/sv/sw_msg_monitor_if/sw_msg_monitor_if.sv
index ae397b9..7eef541 100644
--- a/hw/dv/sv/sw_msg_monitor_if/sw_msg_monitor_if.sv
+++ b/hw/dv/sv/sw_msg_monitor_if/sw_msg_monitor_if.sv
@@ -435,7 +435,7 @@
 
     case (msg_type.tolower())
       "i", "info":            `uvm_info(msg_header, msg, level)
-      "w", "warn", "warning": `uvm_warning(msg_header, msg)
+      "w", "warn", "warning": `uvm_error(msg_header, msg)
       "e", "err", "error":    `uvm_error(msg_header, msg)
       "f", "fatal":           `uvm_fatal(msg_header, msg)
       default:                `uvm_info(msg_header, msg, level)
diff --git a/hw/dv/sv/test_vectors/test_vectors_pkg.sv b/hw/dv/sv/test_vectors/test_vectors_pkg.sv
index 9af0cf9..324961b 100644
--- a/hw/dv/sv/test_vectors/test_vectors_pkg.sv
+++ b/hw/dv/sv/test_vectors/test_vectors_pkg.sv
@@ -56,7 +56,8 @@
 
   // parse sha/hmac msg, key (if hmac_en), msg length, and exp_digest from a test vectors file
   // support test vectors files with a nist vector format
-  function automatic void parse_sha_hmac(bit hmac_en, input int index, ref test_vectors_t parsed_vectors[]);
+  function automatic void parse_sha_hmac(bit hmac_en, int index,
+                                         ref test_vectors_t parsed_vectors[]);
     int        fd;
     bit [7:0]  bytes[];
     string     name, str_data, test_vectors_path;
diff --git a/hw/ip/aes/dv/env/aes_env_cfg.sv b/hw/ip/aes/dv/env/aes_env_cfg.sv
index 9cfe7aa..3b8a393 100644
--- a/hw/ip/aes/dv/env/aes_env_cfg.sv
+++ b/hw/ip/aes/dv/env/aes_env_cfg.sv
@@ -12,7 +12,7 @@
   virtual function void initialize_csr_addr_map_size();
     this.csr_addr_map_size = AES_ADDR_MAP_SIZE;
   endfunction : initialize_csr_addr_map_size
-  
+
   virtual   function void initialize(bit [TL_AW-1:0] csr_base_addr = '1);
     super.initialize(csr_base_addr);
   endfunction
diff --git a/hw/ip/aes/dv/env/aes_env_pkg.sv b/hw/ip/aes/dv/env/aes_env_pkg.sv
index 6e55942..e0c8ece 100644
--- a/hw/ip/aes/dv/env/aes_env_pkg.sv
+++ b/hw/ip/aes/dv/env/aes_env_pkg.sv
@@ -11,9 +11,9 @@
   import tl_agent_pkg::*;
   import dv_lib_pkg::*;
   import cip_base_pkg::*;
-  import aes_reg_pkg::*;  
+  import aes_reg_pkg::*;
   import aes_ral_pkg::*;
-  
+
   // macro includes
   `include "uvm_macros.svh"
   `include "dv_macros.svh"
@@ -32,7 +32,7 @@
 // `include "aes_reg_block.sv"
  `include "aes_env_cfg.sv"
  `include "aes_env_cov.sv"
- `include "aes_virtual_sequencer.sv"  
+ `include "aes_virtual_sequencer.sv"
  `include "aes_scoreboard.sv"
  `include "aes_env.sv"
  `include "aes_vseq_list.sv"
diff --git a/hw/ip/aes/dv/env/seq_lib/aes_base_vseq.sv b/hw/ip/aes/dv/env/seq_lib/aes_base_vseq.sv
index 24b07c4..af07820 100644
--- a/hw/ip/aes/dv/env/seq_lib/aes_base_vseq.sv
+++ b/hw/ip/aes/dv/env/seq_lib/aes_base_vseq.sv
@@ -9,12 +9,12 @@
   .COV_T               (aes_env_cov),
   .VIRTUAL_SEQUENCER_T (aes_virtual_sequencer)
 );
-  
+
   `uvm_object_utils(aes_base_vseq)
   `uvm_object_new
-  parameter ENCRYPT = 1'b0;
-  parameter DECRYPT = 1'b1;
-  
+  parameter bit ENCRYPT = 1'b0;
+  parameter bit DECRYPT = 1'b1;
+
   aes_reg2hw_t aes_reg;
 
   // various knobs to enable certain routines
@@ -28,19 +28,19 @@
   virtual task dut_shutdown();
     // check for pending aes operations and wait for them to complete
     // TODO
-    
+
   endtask
-  
-  // setup basic aes features 
+
+  // setup basic aes features
   virtual task aes_init();
-    bit [31:0] aes_ctrl = '0;    
+    bit [31:0] aes_ctrl = '0;
 
     // initialize control register
     aes_ctrl[0]   = 0;        // set to encryption
     aes_ctrl[3:1] = 3'b001;   // set to 128b key
     aes_ctrl[4]   = 0;        // start encryption automaticaly
     aes_ctrl[5]   = 0;        // don't overwrite output reg.
-    csr_wr(.csr(ral.ctrl), .value(aes_ctrl));       
+    csr_wr(.csr(ral.ctrl), .value(aes_ctrl));
   endtask
 
   virtual      task set_mode(bit mode);
@@ -48,9 +48,9 @@
 
     ral.ctrl.mode.set(mode);
     csr_update(.csr(ral.ctrl));
-    
+
   endtask
-  
+
   virtual task write_key(aes_reg2hw_key_mreg_t [7:0] key);
     csr_wr(.csr(ral.key0), .value(key[0]));
     csr_wr(.csr(ral.key1), .value(key[1]));
@@ -59,8 +59,8 @@
     csr_wr(.csr(ral.key4), .value(key[4]));
     csr_wr(.csr(ral.key5), .value(key[5]));
     csr_wr(.csr(ral.key6), .value(key[6]));
-    csr_wr(.csr(ral.key7), .value(key[7]));         
-  endtask  
+    csr_wr(.csr(ral.key7), .value(key[7]));
+  endtask
 
   virtual task add_data(logic [127:0] data);
     `uvm_info(`gfn, $sformatf("\n\t ---| Write data word 0: %02h", data[31:0]), UVM_DEBUG)
@@ -70,7 +70,7 @@
     `uvm_info(`gfn, $sformatf("\n\t ---| Write data word 2: %02h", data[95:64]), UVM_DEBUG)
     csr_wr(.csr(ral.data_in2), .value(data[95:64]));
     `uvm_info(`gfn, $sformatf("\n\t ---| Write data word 0: %02h", data[127:96]), UVM_DEBUG)
-    csr_wr(.csr(ral.data_in3), .value(data[127:96]));    
+    csr_wr(.csr(ral.data_in3), .value(data[127:96]));
   endtask
 
   virtual task read_data(output logic [127:0] cypher_txt);
@@ -79,7 +79,8 @@
     csr_spinwait(.ptr(ral.status.output_valid) , .exp_data(1'b1));    // poll for data valid
     csr_rd(.ptr(ral.data_out3), .value(rd_data));
     cypher_txt[127:96] = rd_data;
-    `uvm_info(`gfn, $sformatf("\n\t ---| Read encrypted text from dataout3 %02h", rd_data), UVM_DEBUG)
+    `uvm_info(`gfn, $sformatf("\n\t ---| Read encrypted text from dataout3 %02h", rd_data),
+              UVM_DEBUG)
     csr_rd(.ptr(ral.data_out2), .value(rd_data));
     cypher_txt[95:64] = rd_data;
     `uvm_info(`gfn, $sformatf("\n\t ---| Read encrypted text dataout2 %02h", rd_data), UVM_DEBUG)
diff --git a/hw/ip/aes/dv/env/seq_lib/aes_sanity_vseq.sv b/hw/ip/aes/dv/env/seq_lib/aes_sanity_vseq.sv
index 3903dc0..6fc0cf1 100644
--- a/hw/ip/aes/dv/env/seq_lib/aes_sanity_vseq.sv
+++ b/hw/ip/aes/dv/env/seq_lib/aes_sanity_vseq.sv
@@ -9,12 +9,12 @@
   `uvm_object_new
 
   task body();
-    
+
     `uvm_info(`gfn, $sformatf("STARTING AES SEQUENCE"), UVM_LOW);
     `DV_CHECK_RANDOMIZE_FATAL(this)
     `uvm_info(`gfn, $sformatf("running aes sanity sequence"), UVM_LOW);
-      
-  endtask : body  
+
+  endtask : body
 
 endclass : aes_sanity_vseq
 
diff --git a/hw/ip/aes/dv/env/seq_lib/aes_wake_up_vseq.sv b/hw/ip/aes/dv/env/seq_lib/aes_wake_up_vseq.sv
index 5727fff..8805995 100644
--- a/hw/ip/aes/dv/env/seq_lib/aes_wake_up_vseq.sv
+++ b/hw/ip/aes/dv/env/seq_lib/aes_wake_up_vseq.sv
@@ -9,35 +9,36 @@
 
   `uvm_object_new
 
-  logic [127:0] plain_text   = 128'hDEADBEEFEEDDBBAABAADBEEFDEAFBEAD;
-  logic [255:0] init_key     = 256'h0000111122223333444455556666777788889999AAAABBBBCCCCDDDDEEEEFFFF;
+  logic [127:0] plain_text = 128'hDEADBEEFEEDDBBAABAADBEEFDEAFBEAD;
+  logic [255:0] init_key   = 256'h0000111122223333444455556666777788889999AAAABBBBCCCCDDDDEEEEFFFF;
   logic [127:0] cypher_text, decrypted_text;
 
   task body();
-    
+
     `uvm_info(`gfn, $sformatf("STARTING AES SEQUENCE"), UVM_DEBUG)
     `DV_CHECK_RANDOMIZE_FATAL(this)
     `uvm_info(`gfn, $sformatf("running aes sanity sequence"), UVM_DEBUG)
 
     `uvm_info(`gfn, $sformatf(" \n\t ---|setting mode to encrypt"), UVM_DEBUG)
     // set mode to encrypt
-    set_mode(ENCRYPT);    
-    
+    set_mode(ENCRYPT);
+
     `uvm_info(`gfn, $sformatf(" \n\t ---| WRITING INIT KEY"), UVM_DEBUG)
     // add init key
-    write_key(init_key);    
+    write_key(init_key);
     cfg.clk_rst_vif.wait_clks(20);
-    
+
     `uvm_info(`gfn, $sformatf(" \n\t ---| ADDING PLAIN TEXT"), UVM_DEBUG)
     add_data(plain_text);
-    
+
     cfg.clk_rst_vif.wait_clks(20);
     // poll status register
-    `uvm_info(`gfn, $sformatf("\n\t ---| Polling for data register %s", ral.status.convert2string()), UVM_DEBUG)
+    `uvm_info(`gfn, $sformatf("\n\t ---| Polling for data register %s",
+        ral.status.convert2string()), UVM_DEBUG)
     read_data(cypher_text);
     `uvm_info(`gfn, $sformatf("\n\t ---|cypher text : %02h", cypher_text), UVM_DEBUG)
 
-    // read output    
+    // read output
     `uvm_info(`gfn, $sformatf("\n\t ------|WAIT 0 |-------"), UVM_LOW)
     cfg.clk_rst_vif.wait_clks(20);
 
@@ -49,15 +50,20 @@
 
     `uvm_info(`gfn, $sformatf("\n\t ---| WRITING CYPHER TEXT %02h", cypher_text), UVM_DEBUG)
     add_data(cypher_text);
-    `uvm_info(`gfn, $sformatf("\n\t ---| Polling for data %s", ral.status.convert2string()), UVM_DEBUG)
+    `uvm_info(`gfn, $sformatf("\n\t ---| Polling for data %s", ral.status.convert2string()),
+        UVM_DEBUG)
     read_data(decrypted_text);
 
     if(decrypted_text == plain_text) begin
-      `uvm_info(`gfn, $sformatf(" \n\t ---| YAY TEST PASSED |--- \n \t DECRYPTED: \t %02h \n\t Plaintext: \t %02h ", decrypted_text, plain_text), UVM_NONE)
+      `uvm_info(`gfn, $sformatf(
+          " \n\t ---| YAY TEST PASSED |--- \n \t DECRYPTED: \t %02h \n\t Plaintext: \t %02h ",
+          decrypted_text, plain_text), UVM_NONE)
     end else begin
-      `uvm_fatal(`gfn, $sformatf(" \n\t ---| NOO TEST FAILED |--- \n \t DECRYPTED: \t %02h \n\t Plaintext: \t %02h ", decrypted_text, plain_text))
-    end    
-    
+      `uvm_fatal(`gfn, $sformatf(
+          " \n\t ---| NOO TEST FAILED |--- \n \t DECRYPTED: \t %02h \n\t Plaintext: \t %02h ",
+          decrypted_text, plain_text))
+    end
+
     `uvm_info(`gfn, $sformatf("DATA ADDED "), UVM_DEBUG)
   endtask : body
 endclass : aes_wake_up_vseq
diff --git a/hw/ip/aes/dv/tests/aes_base_test.sv b/hw/ip/aes/dv/tests/aes_base_test.sv
index 2249c6f..8c41bb5 100644
--- a/hw/ip/aes/dv/tests/aes_base_test.sv
+++ b/hw/ip/aes/dv/tests/aes_base_test.sv
@@ -18,7 +18,7 @@
 
 //    function configure_knobs()
 //      endfunction // configure_knobs
-  
+
 
 endclass : aes_base_test
 
diff --git a/hw/ip/gpio/dv/env/seq_lib/gpio_stress_all_vseq.sv b/hw/ip/gpio/dv/env/seq_lib/gpio_stress_all_vseq.sv
index 01ffa1e..2482538 100644
--- a/hw/ip/gpio/dv/env/seq_lib/gpio_stress_all_vseq.sv
+++ b/hw/ip/gpio/dv/env/seq_lib/gpio_stress_all_vseq.sv
@@ -37,10 +37,12 @@
         `downcast(common_vseq, gpio_vseq);
         common_vseq.common_seq_type = "intr_test";
       end
-      `uvm_info(`gfn, $sformatf("seq_idx = %0d, sequence is %0s", seq_idx, gpio_vseq.get_name()), UVM_HIGH)
+      `uvm_info(`gfn, $sformatf("seq_idx = %0d, sequence is %0s", seq_idx, gpio_vseq.get_name()),
+                UVM_HIGH)
 
       gpio_vseq.start(p_sequencer);
-      `uvm_info(`gfn, $sformatf("End of sequence %0s with seq_idx = %0d", gpio_vseq.get_name(), seq_idx), UVM_HIGH)
+      `uvm_info(`gfn, $sformatf("End of sequence %0s with seq_idx = %0d", gpio_vseq.get_name(),
+          seq_idx), UVM_HIGH)
     end
   endtask : body
 
diff --git a/hw/ip/prim/dv/tb/prim_lfsr_tb.sv b/hw/ip/prim/dv/tb/prim_lfsr_tb.sv
index b0e3522..e75a16c 100644
--- a/hw/ip/prim/dv/tb/prim_lfsr_tb.sv
+++ b/hw/ip/prim/dv/tb/prim_lfsr_tb.sv
@@ -14,9 +14,9 @@
 // this can be overriden on the command line
 // supported types are GAL_XOR, FIB_XNOR
 `ifdef LFSR_TYPE
-  localparam                  LfsrType   = `LFSR_TYPE;
+  localparam string           LfsrType   = `LFSR_TYPE;
 `else
-  localparam                  LfsrType   = "GAL_XOR";
+  localparam string           LfsrType   = "GAL_XOR";
 `endif
 `ifdef MIN_LFSR_DW
   localparam int unsigned     MinLfsrDw  = `MIN_LFSR_DW;
@@ -32,7 +32,7 @@
   // leave this constant
   localparam logic SEED       = 1'b1;
 
-  localparam time  CLK_PERIOD = 10000;
+  localparam time  ClkPeriod  = 10000;
 
 //////////////////////////////////////////////////////
 // clock
@@ -88,7 +88,7 @@
     lfsr_en = '0;
     err     = '0;
 
-    main_clk.set_period_ns(CLK_PERIOD);
+    main_clk.set_period_ns(ClkPeriod);
     main_clk.set_active();
     main_clk.apply_reset();
 
diff --git a/hw/ip/rv_dm/dv/env/rv_dm_env.sv b/hw/ip/rv_dm/dv/env/rv_dm_env.sv
index f35cfab..b7a2384 100644
--- a/hw/ip/rv_dm/dv/env/rv_dm_env.sv
+++ b/hw/ip/rv_dm/dv/env/rv_dm_env.sv
@@ -60,19 +60,19 @@
     super.connect_phase(phase);
     if (cfg.en_scb) begin
       m_jtag_agent.monitor.analysis_port.connect(scoreboard.jtag_fifo.analysis_export);
-      m_tl_host_agent.mon.a_chan_port.connect(scoreboard.tl_host_a_chan_fifo.analysis_export);
-      m_tl_host_agent.mon.d_chan_port.connect(scoreboard.tl_host_d_chan_fifo.analysis_export);
-      m_tl_device_agent.mon.a_chan_port.connect(scoreboard.tl_host_a_chan_fifo.analysis_export);
-      m_tl_device_agent.mon.d_chan_port.connect(scoreboard.tl_host_d_chan_fifo.analysis_export);
+      m_tl_host_agent.monitor.a_chan_port.connect(scoreboard.tl_host_a_chan_fifo.analysis_export);
+      m_tl_host_agent.monitor.d_chan_port.connect(scoreboard.tl_host_d_chan_fifo.analysis_export);
+      m_tl_device_agent.monitor.a_chan_port.connect(scoreboard.tl_host_a_chan_fifo.analysis_export);
+      m_tl_device_agent.monitor.d_chan_port.connect(scoreboard.tl_host_d_chan_fifo.analysis_export);
     end
     if (cfg.is_active && cfg.m_jtag_agent_cfg.is_active) begin
       virtual_sequencer.jtag_sequencer_h = m_jtag_agent.sequencer;
     end
     if (cfg.is_active && cfg.m_tl_host_agent_cfg.is_active) begin
-      virtual_sequencer.tl_host_sequencer_h = m_tl_host_agent.seqr;
+      virtual_sequencer.tl_host_sequencer_h = m_tl_host_agent.sequencer;
     end
     if (cfg.is_active && cfg.m_tl_device_agent_cfg.is_active) begin
-      virtual_sequencer.tl_device_sequencer_h = m_tl_device_agent.seqr;
+      virtual_sequencer.tl_device_sequencer_h = m_tl_device_agent.sequencer;
     end
   endfunction
 
diff --git a/hw/ip/rv_dm/dv/env/rv_dm_env_cfg.sv b/hw/ip/rv_dm/dv/env/rv_dm_env_cfg.sv
index c7c0e32..f0f2be0 100644
--- a/hw/ip/rv_dm/dv/env/rv_dm_env_cfg.sv
+++ b/hw/ip/rv_dm/dv/env/rv_dm_env_cfg.sv
@@ -29,11 +29,11 @@
     m_jtag_agent_cfg = jtag_agent_cfg::type_id::create("m_jtag_agent_cfg");
     // create tl_host agent config obj
     m_tl_host_agent_cfg = tl_agent_cfg::type_id::create("m_tl_host_agent_cfg");
-    m_tl_host_agent_cfg.is_host = 1'b1;
+    m_tl_host_agent_cfg.if_mode = dv_utils_pkg::Host;
     m_tl_host_agent_cfg.is_active = 1'b1;
     // create tl_device agent config obj
     m_tl_device_agent_cfg = tl_agent_cfg::type_id::create("m_tl_device_agent_cfg");
-    m_tl_device_agent_cfg.is_host = 1'b0;
+    m_tl_device_agent_cfg.if_mode = dv_utils_pkg::Device;
     m_tl_device_agent_cfg.is_active = 1'b1;
   endfunction
 
diff --git a/hw/ip/rv_dm/dv/tb.sv b/hw/ip/rv_dm/dv/tb.sv
index f6c8d29..a978458 100644
--- a/hw/ip/rv_dm/dv/tb.sv
+++ b/hw/ip/rv_dm/dv/tb.sv
@@ -73,12 +73,14 @@
     .AxiUserWidth ( 16)
   ) u_dm_top (
     .clk_i         (clk),         // in clock
-    .rst_ni        (rst_n),       // in asynchronous reset active low, connect PoR here, not the system reset
+    // in asynchronous reset active low, connect PoR here, not the system reset
+    .rst_ni        (rst_n),
     .testmode_i    (1'b0),        // in
     .ndmreset_o    (ndmrst),      // out               non-debug module reset
     .dmactive_o    (dmactive),    // out               debug module is active
     .debug_req_o   (debug_req),   // out [NrHarts-1:0] async debug request
-    .unavailable_i (unavailable), // in  [NrHarts-1:0] communicate whether the hart is unavailable (e.g.: power down)
+    // in  [NrHarts-1:0] communicate whether the hart is unavailable (e.g.: power down)
+    .unavailable_i (unavailable),
 
     // bus device, for an execution based technique
     //.tl_d_i        (tlul_mem_if.device.h2d),
@@ -122,11 +124,11 @@
     .tdo_oe_o         (jtag.dut.tdo_oe)
   );
 
-  localparam JTCK_PERIOD = 27.3ns;
+  localparam time JtckPeriod = 27.3ns;
   initial begin
     jtag.tb.tck = 0;
     forever begin
-      #(JTCK_PERIOD/2) jtag.tb.tck = ~jtag.tb.tck;
+      #(JtckPeriod/2) jtag.tb.tck = ~jtag.tb.tck;
     end
   end
   initial begin
diff --git a/hw/ip/spi_device/dv/env/spi_device_scoreboard.sv b/hw/ip/spi_device/dv/env/spi_device_scoreboard.sv
index f03e2e9..1ac7114 100644
--- a/hw/ip/spi_device/dv/env/spi_device_scoreboard.sv
+++ b/hw/ip/spi_device/dv/env/spi_device_scoreboard.sv
@@ -174,7 +174,8 @@
       update_rx_mem_fifo_and_wptr();
     end
     else begin
-      `uvm_info(`gfn, $sformatf("RX overflow data: 0x%0h ptr: 0x%0h", data, rx_wptr_exp), UVM_MEDIUM)
+      `uvm_info(`gfn, $sformatf("RX overflow data: 0x%0h ptr: 0x%0h", data, rx_wptr_exp),
+                UVM_MEDIUM)
     end
   endfunction
 
diff --git a/hw/ip/trial1/dv/tb.sv b/hw/ip/trial1/dv/tb.sv
index ed8ddec..7cce200 100644
--- a/hw/ip/trial1/dv/tb.sv
+++ b/hw/ip/trial1/dv/tb.sv
@@ -9,7 +9,7 @@
 
   // Clock gen
   logic clk, rst_n;
-  parameter CLK_PERIOD = 10ns;
+  parameter time CLK_PERIOD = 10ns;
   initial begin
     clk = 0;
     forever begin
diff --git a/hw/ip/trial1/dv/trial1_test.sv b/hw/ip/trial1/dv/trial1_test.sv
index 9b67c3f..c5dbc10 100644
--- a/hw/ip/trial1/dv/trial1_test.sv
+++ b/hw/ip/trial1/dv/trial1_test.sv
@@ -21,9 +21,9 @@
   // for now always accept read responses
   assign  tl_h2d.d_ready = 1'b1;
 
-  task send_wr (
-    input [11:0] waddr,
-    input [31:0] wdata
+  task automatic send_wr (
+    input bit [11:0] waddr,
+    input bit [31:0] wdata
   );
     begin
       tl_h2d.a_address = waddr;
@@ -43,9 +43,9 @@
     end
   endtask
 
-  task send_rd (
-    input  [11:0] raddr,
-    output [31:0] rdata
+  task automatic send_rd (
+    input  bit [11:0] raddr,
+    output bit [31:0] rdata
   );
     begin
       tl_h2d.a_address  = raddr;
@@ -65,10 +65,10 @@
     end
   endtask
 
-  task test_q (
+  task automatic test_q (
     string regname,
-    input [31:0] gotval,
-    input [31:0] expval
+    input bit [31:0] gotval,
+    input bit [31:0] expval
   );
     begin
       if (gotval !== expval) begin
@@ -110,24 +110,25 @@
   // externalized register
   assign hw2reg.rotype1.d = rotype1_capture;
 
-  task test_capture (
+  task automatic test_capture (
     string regname,
-    input [31:0] gotval,
-    input [31:0] expval
+    input bit [31:0] gotval,
+    input bit [31:0] expval
   );
     begin
       if (gotval !== expval) begin
-        $display("ERROR: expected hwqe captured value for %s is %x got %x", regname, expval, gotval);
+        $display("ERROR: expected hwqe captured value for %s is %x got %x", regname, expval,
+                 gotval);
         errorcount++;
       end else if (DEBUG)
         $display("INFO: got expected hwqe captured value for %s of %x", regname, expval);
     end
   endtask
 
-  task test_reg (
+  task automatic test_reg (
     string regname,
-    input [11:0] addr,
-    input [31:0] expval
+    input bit [11:0] addr,
+    input bit [31:0] expval
   );
     begin
       logic [31:0] gotval;
@@ -140,7 +141,7 @@
     end
   endtask
 
-  task test_rwtype0(input [31:0] expdata);
+  task automatic test_rwtype0(input bit [31:0] expdata);
     // test register read
     test_reg("RWTYPE0", 12'h0, expdata);
     // test q
@@ -153,9 +154,9 @@
     test_q("RWTYPE0", reg2hw.rwtype0.q, expdata);
   endtask
 
-  task test_rwtype1(input [31:0] expdata);
+  task automatic test_rwtype1(input bit [31:0] expdata);
     logic [31:0] maskexp;
-    assign maskexp = expdata & 32'h0000ff13;
+    maskexp = expdata & 32'h0000ff13;
     test_reg("RWTYPE1", 12'h4, maskexp);
     // test q's
     test_q("RWTYPE1.field0", reg2hw.rwtype1.field0.q, maskexp[0]);
@@ -172,7 +173,7 @@
     test_q("RWTYPE1.field15_8", reg2hw.rwtype1.field15_8.q, maskexp[15:8]);
   endtask
 
-  task test_rwtype2(input [31:0] expdata);
+  task automatic test_rwtype2(input bit [31:0] expdata);
     // test register read
     test_reg("RWTYPE2", 12'h8, expdata);
     // test q
@@ -185,7 +186,7 @@
     test_q("RWTYPE2", reg2hw.rwtype2.q, expdata);
   endtask
 
-  task test_rwtype3(input [31:0] expdata);
+  task automatic test_rwtype3(input bit [31:0] expdata);
     test_reg("RWTYPE3", 12'hc, expdata);
     // test q's
     test_q("RWTYPE3.field0", reg2hw.rwtype3.field0.q, expdata[15:0]);
@@ -198,7 +199,7 @@
     test_q("RWTYPE3.field1", reg2hw.rwtype3.field1.q, expdata[31:16]);
   endtask
 
-  task test_rwtype4(input [31:0] expdata);
+  task automatic test_rwtype4(input bit [31:0] expdata);
     test_reg("RWTYPE4", 12'h200, expdata);
     // test q's
     test_q("RWTYPE4.field0", reg2hw.rwtype4.field0.q, expdata[15:0]);
@@ -211,7 +212,7 @@
     test_q("RWTYPE4.field1", reg2hw.rwtype4.field1.q, expdata[31:16]);
   endtask
 
-  task test_rotype0(input [31:0] expdata);
+  task automatic test_rotype0(input bit [31:0] expdata);
     // test register read
     test_reg("ROTYPE0", 12'h204, expdata);
     // test q
@@ -224,7 +225,7 @@
     test_q("ROTYPE0", reg2hw.rotype0.q, expdata);
   endtask
 
-  task test_w1ctype0(input [31:0] expdata);
+  task automatic test_w1ctype0(input bit [31:0] expdata);
     // test register read
     test_reg("W1CTYPE0", 12'h208, expdata);
     // test q
@@ -237,7 +238,7 @@
     test_q("W1CTYPE0", reg2hw.w1ctype0.q, expdata);
   endtask
 
-  task test_w1ctype1(input [31:0] expdata);
+  task automatic test_w1ctype1(input bit [31:0] expdata);
     test_reg("W1CTYPE1", 12'h20c, expdata);
     // test q's
     test_q("W1CTYPE1.field0", reg2hw.w1ctype1.field0.q, expdata[15:0]);
@@ -250,7 +251,7 @@
     test_q("W1CTYPE1.field1", reg2hw.w1ctype1.field1.q, expdata[31:16]);
   endtask
 
-  task test_w1ctype2(input [31:0] expdata);
+  task automatic test_w1ctype2(input bit [31:0] expdata);
     // test register read
     test_reg("W1CTYPE2", 12'h210, expdata);
     // test q
@@ -263,7 +264,7 @@
     test_q("W1CTYPE2", reg2hw.w1ctype2.q, expdata);
   endtask
 
-  task test_w1stype2(input [31:0] expdata);
+  task automatic test_w1stype2(input bit [31:0] expdata);
     // test register read
     test_reg("W1STYPE2", 12'h214, expdata);
     // test q
@@ -276,7 +277,7 @@
     test_q("W1STYPE2", reg2hw.w1stype2.q, expdata);
   endtask
 
-  task test_w0ctype2(input [31:0] expdata);
+  task automatic test_w0ctype2(input bit [31:0] expdata);
     // test register read
     test_reg("W0CTYPE2", 12'h218, expdata);
     // test q
@@ -289,7 +290,7 @@
     test_q("W0CTYPE2", reg2hw.w0ctype2.q, expdata);
   endtask
 
-  task test_r0w1ctype2(input [31:0] expdata);
+  task automatic test_r0w1ctype2(input bit [31:0] expdata);
     // test register read
     test_reg("R0W1CTYPE2", 12'h21c, 0);
     // test q
@@ -302,7 +303,7 @@
     test_q("R0W1CTYPE2", reg2hw.r0w1ctype2.q, expdata);
   endtask
 
-  task test_rctype0(input [31:0] expdata);
+  task automatic test_rctype0(input bit [31:0] expdata);
     // test q
     test_q("RCTYPE0", reg2hw.rctype0.q, expdata);
     // test register read
@@ -315,7 +316,7 @@
     test_q("RCTYPE0", reg2hw.rctype0.q, 32'h0);
   endtask
 
-  task test_wotype0(input [31:0] expdata);
+  task automatic test_wotype0(input bit [31:0] expdata);
     // test register read, always returns zero
     test_reg("WOTYPE0", 12'h224, 0);
     // test q
@@ -328,7 +329,7 @@
     test_q("WOTYPE0", reg2hw.wotype0.q, expdata);
   endtask
 
-  task test_mixtype0(input [31:0] expdata);
+  task automatic test_mixtype0(input bit [31:0] expdata);
     // test q's
     test_q("MIXTYPE0.field0", reg2hw.mixtype0.field0.q, expdata[3:0]);
     test_q("MIXTYPE0.field1", reg2hw.mixtype0.field1.q, expdata[7:4]);
@@ -342,7 +343,8 @@
     test_reg("MIXTYPE0", 12'h228, expdata & 32'h0fffffff);  // [31:28] is write-only
     // hold value
     repeat(5) @(posedge clk);
-    test_reg("MIXTYPE0", 12'h228, expdata & 32'h00ffffff);  // [31:28] is write-only, [27:24] is read-clear
+    // [31:28] is write-only, [27:24] is read-clear
+    test_reg("MIXTYPE0", 12'h228, expdata & 32'h00ffffff);
     // test q
     test_q("MIXTYPE0.field0", reg2hw.mixtype0.field0.q, expdata[3:0]);
     test_q("MIXTYPE0.field1", reg2hw.mixtype0.field1.q, expdata[7:4]);
@@ -354,7 +356,7 @@
     test_q("MIXTYPE0.field7", reg2hw.mixtype0.field7.q, expdata[31:28]);
   endtask
 
-  task test_rwtype5(input [31:0] expdata);
+  task automatic test_rwtype5(input bit [31:0] expdata);
     // test register read
     test_reg("RWTYPE5", 12'h22c, expdata);
     // test q
@@ -367,12 +369,12 @@
     test_q("RWTYPE5", reg2hw.rwtype5.q, expdata);
   endtask
 
-  task test_rwtype5_capture(input [31:0] expdata);
+  task automatic test_rwtype5_capture(input bit [31:0] expdata);
     // test captured value
     test_capture("RWTYPE5", rwtype5_capture, expdata);
   endtask
 
-  task test_rwtype6(input [31:0] expdata);
+  task automatic test_rwtype6(input bit [31:0] expdata);
     // test register read
     test_reg("RWTYPE6", 12'h230, expdata);
     // holds value
@@ -381,12 +383,12 @@
     test_reg("RWTYPE6", 12'h230, expdata);
   endtask
 
-  task test_rwtype6_capture(input [31:0] expdata);
+  task automatic test_rwtype6_capture(input bit [31:0] expdata);
     // test captured value
     test_capture("RWTYPE6", rwtype6_capture, expdata);
   endtask
 
-  task test_rwtype7(input [31:0] expdata);
+  task automatic test_rwtype7(input bit [31:0] expdata);
     // test register read
     test_reg("RWTYPE7", 12'h23c, expdata);
     // holds value
@@ -395,7 +397,7 @@
     test_reg("RWTYPE7", 12'h23c, expdata);
   endtask
 
-  task test_rotype1(input [31:0] expdata);
+  task automatic test_rotype1(input bit [31:0] expdata);
     // test register read
     test_reg("ROTYPE1", 12'h234, expdata);
     // holds value
@@ -404,12 +406,12 @@
     test_reg("ROTYPE1", 12'h234, expdata);
   endtask
 
-  task test_rotype1_capture(input [31:0] expdata);
+  task automatic test_rotype1_capture(input bit [31:0] expdata);
     // test captured value
     test_capture("ROTYPE1", rotype1_capture, expdata);
   endtask
 
-  task test_rotype2(input [31:0] expdata);
+  task automatic test_rotype2(input bit [31:0] expdata);
     // test register read
     test_reg("ROTYPE2", 12'h238, expdata);
     // holds value