diff --git a/hw/Makefile b/hw/Makefile
index 6d79654..3f434d1 100644
--- a/hw/Makefile
+++ b/hw/Makefile
@@ -30,6 +30,7 @@
        pattgen       \
        pinmux        \
        pwrmgr        \
+       rbox          \
        rstmgr        \
        rv_plic       \
        rv_timer      \
diff --git a/hw/ip/rbox/data/rbox.hjson b/hw/ip/rbox/data/rbox.hjson
new file mode 100644
index 0000000..83e4754
--- /dev/null
+++ b/hw/ip/rbox/data/rbox.hjson
@@ -0,0 +1,573 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{ name: "rbox",
+  clock_primary: "clk_i",
+  other_clock_list: [
+    "clk_aon_i"
+  ]
+  bus_device: "tlul",
+  bus_host: "none",
+  reset_primary: "rst_ni",
+  other_reset_list: [
+    "rst_slow_ni"
+  ],
+  interrupt_list: [
+    { name: "rbox_intr_o",
+      desc: "combo or keyboard triggered interrupt",
+    }
+  ],
+  param_list: [
+    { name:    "NumCombo",
+      type:    "int",
+      default: "4",
+      desc:    "Number of keyboard combos",
+      local:   "true",
+    }
+  ],
+  available_input_list: [
+    { name: "ac_present", desc: "A/C power is present" }
+    { name: "ec_rst_l_i", desc: "ec_rst_l as an input from the open drain IO" }
+    { name: "key0_in", desc: "VolUp button in tablet; column output from the EC in a laptop" }
+    { name: "key1_in", desc: "VolDown button in tablet; row input from keyboard matrix in a laptop" }
+    { name: "key2_in", desc: "TBD button in tablet; row input from keyboard matrix in a laptop" }
+    { name: "pwrb_in", desc: "Power button in both tablet and laptop" }
+  ],
+  available_output_list: [
+    { name: "bat_disable", desc: "Battery is disconnected" }
+    { name: "ec_rst_l_o", desc: "ec_rst_l as an output to the open drain IO" }
+    { name: "key0_out", desc: "Passthrough from key0_in, can be configured to invert" }
+    { name: "key1_out", desc: "Passthrough from key1_in, can be configured to invert" }
+    { name: "key2_out", desc: "Passthrough from key2_in, can be configured to invert" }
+    { name: "pwrb_out", desc: "Passthrough from pwrb_in, can be configured to invert" }
+  ],
+  regwidth: "32",
+  registers: [
+    { name: "REGWEN",
+      desc: "Configuration write enable control register",
+      swaccess: "rw0c",
+      hwaccess: "none",
+      resval: "1",
+      fields: [
+        { bits: "0",
+          name: "write_en",
+          desc: '''config write enable.
+                0: cfg is locked(not writable); 1: cfg is not locked(writable)
+                ''',
+        }
+      ]
+    }
+    { name: "ec_rst_ctl",
+      desc: "EC reset control register",
+      swaccess: "rw",
+      hwaccess: "hro",
+      hwqe: "true",
+      regwen: "REGWEN",
+      resval: "2000",
+      fields: [
+        { bits: "15:0",
+          name: "ec_rst_pulse",
+          desc: "Configure the pulse width of ec_rst_l. 10-200ms, each step is 5us(200KHz clock)",
+        }
+      ],
+    }
+    { name: "key_invert_ctl",
+      desc: "configure key input output invert property",
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen: "REGWEN",
+      resval: "0",
+      fields: [
+        { bits: "0",
+	  name: "key0_in",
+	  desc: "0: don’t invert; 1: invert",
+	}
+        { bits: "1",
+	  name: "key0_out",
+	  desc: "0: don’t invert; 1: invert",
+	}
+        { bits: "2",
+	  name: "key1_in",
+	  desc: "0: don’t invert; 1: invert",
+	}
+        { bits: "3",
+	  name: "key1_out",
+	  desc: "0: don’t invert; 1: invert",
+	}
+        { bits: "4",
+	  name: "key2_in",
+	  desc: "0: don’t invert; 1: invert",
+	}
+        { bits: "5",
+	  name: "key2_out",
+	  desc: "0: don’t invert; 1: invert",
+	}
+        { bits: "6",
+	  name: "pwrb_in",
+	  desc: "0: don’t invert; 1: invert",
+	}
+        { bits: "7",
+	  name: "pwrb_out",
+	  desc: "0: don’t invert; 1: invert",
+	}
+        { bits: "8",
+	  name: "ac_present",
+	  desc: "0: don’t invert; 1: invert",
+	}
+        { bits: "9",
+	  name: "bat_disable",
+	  desc: "0: don’t invert; 1: invert",
+	}
+      ]
+    }
+    { name: "pin_allowed_ctl",
+      desc: "configure the allowed pinout override value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen: "REGWEN",
+      resval: "2",
+      fields: [
+        { bits: "0",
+	  name: "bat_disable_0",
+	  desc: "0: disable ;1: enable ",
+	}
+        { bits: "1",
+	  name: "ec_rst_l_0",
+	  desc: "0: disable ;1: enable ",
+	}
+        { bits: "2",
+	  name: "pwrb_out_0",
+	  desc: "0: disable ;1: enable ",
+	}
+        { bits: "3",
+	  name: "key0_out_0",
+	  desc: "0: disable ;1: enable ",
+	}
+        { bits: "4",
+	  name: "key1_out_0",
+	  desc: "0: disable ;1: enable ",
+	}
+        { bits: "5",
+	  name: "key2_out_0",
+	  desc: "0: disable ;1: enable ",
+	}
+        { bits: "6",
+	  name: "bat_disable_1",
+	  desc: "0: disable ;1: enable ",
+	}
+        { bits: "7",
+	  name: "ec_rst_l_1",
+	  desc: "0: disable ;1: enable ",
+	}
+        { bits: "8",
+	  name: "pwrb_out_1",
+	  desc: "0: disable ;1: enable ",
+	}
+        { bits: "9",
+	  name: "key0_out_1",
+	  desc: "0: disable ;1: enable ",
+	}
+        { bits: "10",
+	  name: "key1_out_1",
+	  desc: "0: disable ;1: enable ",
+	}
+        { bits: "11",
+	  name: "key2_out_1",
+	  desc: "0: disable ;1: enable ",
+	}
+      ]
+    }
+    { name: "pin_out_ctl",
+      desc: "configure the pin out directly to override the function",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "2",
+      fields: [
+        { bits: "0",
+	  name: "bat_disable",
+	  desc: "0: disable override;1: enable override",
+	}
+        { bits: "1",
+	  name: "ec_rst_l",
+	  desc: "0: disable override;1: enable override",
+	}
+        { bits: "2",
+	  name: "pwrb_out",
+	  desc: "0: disable override;1: enable override",
+	}
+        { bits: "3",
+	  name: "key0_out",
+	  desc: "0: disable override;1: enable override",
+	}
+        { bits: "4",
+	  name: "key1_out",
+	  desc: "0: disable override;1: enable override",
+	}
+        { bits: "5",
+	  name: "key2_out",
+	  desc: "0: disable override;1: enable override",
+	}
+      ]
+    }
+    { name: "pin_out_value",
+      desc: "confiure the pin out value directly to override the function",
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval: "0",
+      fields: [
+        { bits: "0",
+	  name: "bat_disable",
+	  desc: "0: override to 1b0; 1: override to 1b1",
+	}
+        { bits: "1",
+	  name: "ec_rst_l",
+	  desc: "0: override to 1b0; 1: override to 1b1",
+	}
+        { bits: "2",
+	  name: "pwrb_out",
+	  desc: "0: override to 1b0; 1: override to 1b1",
+	}
+        { bits: "3",
+	  name: "key0_out",
+	  desc: "0: override to 1b0; 1: override to 1b1",
+	}
+        { bits: "4",
+	  name: "key1_out",
+	  desc: "0: override to 1b0; 1: override to 1b1",
+	}
+        { bits: "5",
+	  name: "key2_out",
+	  desc: "0: override to 1b0; 1: override to 1b1",
+	}
+      ]
+    }
+    { name: "pin_in_value",
+      desc: "For SW to read the rbox inputs like GPIO",
+      swaccess: "ro",
+      hwaccess: "hwo",
+      resval: "0",
+      fields: [
+        { bits: "0",
+	  name: "ac_present",
+	  desc: "raw ac_present value; before the invert logic",
+	}
+        { bits: "1",
+	  name: "ec_rst_l",
+	  desc: "raw ac_present value; before the invert logic",
+	}
+        { bits: "2",
+	  name: "pwrb_in",
+	  desc: "raw ac_present value; before the invert logic",
+	}
+        { bits: "3",
+	  name: "key0_in",
+	  desc: "raw ac_present value; before the invert logic",
+	}
+        { bits: "4",
+	  name: "key1_in",
+	  desc: "raw ac_present value; before the invert logic",
+	}
+        { bits: "5",
+	  name: "key2_in",
+	  desc: "raw ac_present value; before the invert logic",
+	}
+      ]
+    }
+    { name: "key_intr_ctl",
+      desc: "Define the keys or inputs that can trigger the interrupt ",
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen: "REGWEN",
+      resval: "0",
+      fields: [
+        { bits: "0",
+	  name: "pwrb_in_H2L",
+	  desc: "0: disable, 1: enable",
+	}
+        { bits: "1",
+	  name: "key0_in_H2L",
+	  desc: "0: disable, 1: enable",
+	}
+        { bits: "2",
+	  name: "key1_in_H2L",
+	  desc: "0: disable, 1: enable",
+	}
+        { bits: "3",
+	  name: "key2_in_H2L",
+	  desc: "0: disable, 1: enable",
+	}
+        { bits: "4",
+	  name: "ac_present_H2L",
+	  desc: "0: disable, 1: enable",
+	}
+        { bits: "5",
+	  name: "ec_rst_l_H2L",
+	  desc: "0: disable, 1: enable",
+	}
+        { bits: "8",
+	  name: "pwrb_in_L2H",
+	  desc: "0: disable, 1: enable",
+	}
+        { bits: "9",
+	  name: "key0_in_L2H",
+	  desc: "0: disable, 1: enable",
+	}
+        { bits: "10",
+	  name: "key1_in_L2H",
+	  desc: "0: disable, 1: enable",
+	}
+        { bits: "11",
+	  name: "key2_in_L2H",
+	  desc: "0: disable, 1: enable",
+	}
+        { bits: "12",
+	  name: "ac_present_L2H",
+	  desc: "0: disable, 1: enable",
+	}
+        { bits: "13",
+	  name: "ec_rst_l_L2H",
+	  desc: "0: disable, 1: enable",
+	}
+      ]
+    }
+    { name: "key_intr_debounce_ctl",
+      desc: "Debounce timer control register for key-triggered interrupt",
+      swaccess: "rw",
+      hwaccess: "hro",
+      hwqe:  "true",
+      regwen: "REGWEN",
+      resval: "0",
+      fields: [
+        { bits: "15:0",
+          name: "debounce_timer",
+          desc: "Define the timer valure so that the key or input is not oscillating for 0-200ms, each step is 5us(200KHz clock)",
+        }
+      ],
+    }
+    { name: "auto_block_debounce_ctl",
+      desc: "Debounce timer control register for pwrb_in H2L transition",
+      swaccess: "rw",
+      hwaccess: "hro",
+      hwqe:  "true",
+      regwen: "REGWEN",
+      resval: "0",
+      fields: [
+        { bits: "15:0",
+          name: "debounce_timer",
+          desc: "Define the timer valure so that pwrb_in is not oscillating for 0-200ms, each step is 5us(200KHz clock)",
+        }
+	{ bits: "16",
+	  name: "auto_block_enable",
+	  desc: "0: disable, 1: enable",
+	}
+      ],
+    }
+    { name: "auto_block_out_ctl",
+      desc: "confiure the key outputs to auto-override and their value",
+      swaccess: "rw",
+      hwaccess: "hro",
+      regwen: "REGWEN",
+      resval: "0",
+      fields: [
+        { bits: "0",
+	  name: "key0_out_sel",
+	  desc: "0: disable auto-block; 1: enable auto-block",
+	}
+        { bits: "1",
+	  name: "key1_out_sel",
+	  desc: "0: disable auto-block; 1: enable auto-block",
+	}
+        { bits: "2",
+	  name: "key2_out_sel",
+	  desc: "0: disable auto-block; 1: enable auto-block",
+	}
+        { bits: "4",
+	  name: "key0_out_value",
+	  desc: "0: override to 1’b0; 1: override to 1’b1",
+	}
+        { bits: "5",
+	  name: "key1_out_value",
+	  desc: "0: override to 1’b0; 1: override to 1’b1",
+	}
+        { bits: "6",
+	  name: "key2_out_value",
+	  desc: "0: override to 1’b0; 1: override to 1’b1",
+	}
+      ]
+    }
+    { multireg: {
+        name: "com_sel_ctl",
+	desc: '''To define the keys that trigger the combo
+	      [0]: key0_in_sel
+              [1]: key1_in_sel
+              [2]: key2_in_sel
+              [3]: pwrb_in_sel
+              [4]: ac_present_sel
+	      HW will detect H2L transition in the combo use case
+              ''',
+        count: "NumCombo",
+        cname: "rbox",
+	swaccess: "rw",
+	hwaccess: "hro",
+        regwen:   "REGWEN",
+	resval:   "0",
+	fields: [
+	  { bits: "0",
+	    name: "key0_in_sel",
+	    desc: "0: disable, 1: enable",
+	  }
+	  { bits: "1",
+	    name: "key1_in_sel",
+	    desc: "0: disable, 1: enable",
+	  }
+	  { bits: "2",
+	    name: "key2_in_sel",
+	    desc: "0: disable, 1: enable",
+	  }
+	  { bits: "3",
+	    name: "pwrb_in_sel",
+	    desc: "0: disable, 1: enable",
+	  }
+	  { bits: "4",
+	    name: "ac_present_sel",
+	    desc: "0: disable, 1: enable",
+	  }
+        ],
+      }
+    }
+    { multireg: {
+        name: "com_det_ctl",
+	desc: '''To define the duration that the combo should be pressed
+	      0-60s, each step is 5us(200KHz clock)
+              ''',
+        count: "NumCombo",
+        cname: "rbox",
+	hwqe:  "true",
+	swaccess: "rw",
+	hwaccess: "hro",
+        regwen:   "REGWEN",
+	resval:   "0",
+	fields: [
+	  { bits: "31:0",
+	    name: "detection_timer",
+	    desc: "0-60s, each step is 5us(200KHz clock)",
+	  }
+        ],
+      }
+    }
+    { multireg: {
+        name: "com_out_ctl",
+	desc: '''To define the actions once the combo is detected
+	      [0]: bat_disable
+              [1]: interrupt
+              [2]: ec_rst
+              [3]: gsc_rst
+              ''',
+        count: "NumCombo",
+        cname: "rbox",
+	swaccess: "rw",
+	hwaccess: "hro",
+        regwen:   "REGWEN",
+	resval:   "0",
+	fields: [
+	  { bits: "0",
+	    name: "bat_disable",
+	    desc: "0: disable, 1: enable",
+	  }
+	  { bits: "1",
+	    name: "interrupt",
+	    desc: "0: disable, 1: enable",
+	  }
+	  { bits: "2",
+	    name: "ec_rst",
+	    desc: "0: disable, 1: enable",
+	  }
+	  { bits: "3",
+	    name: "gsc_rst",
+	    desc: "0: disable, 1: enable",
+	  }
+        ],
+      }
+    }
+    { name: "combo_intr_status",
+      desc: "combo interrupt source",
+      swaccess: "rw1c",
+      hwaccess: "hwo",
+      resval: "0",
+      fields: [
+        { bits: "0",
+	  name: "combo0_H2L",
+	  desc: "0: case not detected;1: case detected",
+	}
+        { bits: "1",
+	  name: "combo1_H2L",
+	  desc: "0: case not detected;1: case detected",
+	}
+        { bits: "2",
+	  name: "combo2_H2L",
+	  desc: "0: case not detected;1: case detected",
+	}
+        { bits: "3",
+	  name: "combo3_H2L",
+	  desc: "0: case not detected;1: case detected",
+	}
+      ]
+    }
+    { name: "key_intr_status",
+      desc: "key interrupt source",
+      swaccess: "rw1c",
+      hwaccess: "hwo",
+      resval: "0",
+      fields: [
+        { bits: "0",
+	  name: "pwrb_H2L",
+	  desc: "0: case not detected;1: case detected",
+	}
+        { bits: "1",
+	  name: "key0_in_H2L",
+	  desc: "0: case not detected;1: case detected",
+	}
+        { bits: "2",
+	  name: "key1_in_H2L",
+	  desc: "0: case not detected;1: case detected",
+	}
+        { bits: "3",
+	  name: "key2_in_H2L",
+	  desc: "0: case not detected;1: case detected",
+	}
+        { bits: "4",
+	  name: "ac_present_H2L",
+	  desc: "0: case not detected;1: case detected",
+	}
+        { bits: "5",
+	  name: "ec_rst_l_H2L",
+	  desc: "0: case not detected;1: case detected",
+	}
+        { bits: "6",
+	  name: "pwrb_L2H",
+	  desc: "0: case not detected;1: case detected",
+	}
+        { bits: "7",
+	  name: "key0_in_L2H",
+	  desc: "0: case not detected;1: case detected",
+	}
+        { bits: "8",
+	  name: "key1_in_L2H",
+	  desc: "0: case not detected;1: case detected",
+	}
+        { bits: "9",
+	  name: "key2_in_L2H",
+	  desc: "0: case not detected;1: case detected",
+	}
+        { bits: "10",
+	  name: "ac_present_L2H",
+	  desc: "0: case not detected;1: case detected",
+	}
+        { bits: "11",
+	  name: "ec_rst_l_L2H",
+	  desc: "0: case not detected;1: case detected",
+	}
+      ]
+    }
+  ],
+}
diff --git a/hw/ip/rbox/data/rbox.prj.hjson b/hw/ip/rbox/data/rbox.prj.hjson
new file mode 100644
index 0000000..b229752
--- /dev/null
+++ b/hw/ip/rbox/data/rbox.prj.hjson
@@ -0,0 +1,15 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+{
+    name:               "rbox",
+    design_spec:        "hw/ip/rbox/doc",
+    dv_doc:             "hw/ip/rbox/doc/dv",
+    hw_checklist:       "hw/ip/rbox/doc/checklist",
+    version:            "1.0",
+    life_stage:         "L1",
+    design_stage:       "D0",
+    verification_stage: "V0",
+    notes:              "",
+}
diff --git a/hw/ip/rbox/rbox.core b/hw/ip/rbox/rbox.core
new file mode 100644
index 0000000..5efb614
--- /dev/null
+++ b/hw/ip/rbox/rbox.core
@@ -0,0 +1,65 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:ip:rbox:1.0"
+description: "rbox"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:constants:top_pkg
+      - lowrisc:prim:all
+      - lowrisc:ip:tlul
+    files:
+      - rtl/rbox_reg_pkg.sv
+      - rtl/rbox_reg_top.sv
+      - rtl/rbox_autoblock.sv
+      - rtl/rbox_comboact.sv
+      - rtl/rbox_combotrg.sv
+      - rtl/rbox_intr.sv
+      - rtl/rbox_inv.sv
+      - rtl/rbox_pin.sv
+      - rtl/rbox_keyintr.sv
+      - rtl/rbox_timerfsm.sv
+      - rtl/rbox_keyfsm.sv
+      - rtl/rbox_combofsm.sv
+      - rtl/rbox_combo.sv
+      - rtl/rbox.sv
+    file_type: systemVerilogSource
+
+  files_ascentlint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    file_type: waiver
+
+  files_veriblelint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+      - lowrisc:lint:comportable
+
+parameters:
+  SYNTHESIS:
+    datatype: bool
+    paramtype: vlogdefine
+
+targets:
+  default: &default_target
+    filesets:
+      - tool_ascentlint  ? (files_ascentlint_waiver)
+      - files_rtl
+    toplevel: rbox
+
+
+  lint:
+    <<: *default_target
+    default_tool: verilator
+    parameters:
+      - SYNTHESIS=true
+    tools:
+      verilator:
+        mode: lint-only
+        verilator_options:
+          - "-Wall"
+