tree c8fe90154891fcd8c28446e31c3e9cf8f8b9747f
parent ded9da4c4c58d00ef990f7f9463cfeaa9f5cbc4f
author Arnon Sharlin <arnon.sharlin@opentitan.org> 1595875548 +0300
committer tjaychen <timothytim@google.com> 1597162378 -0700

[top / ast] Adding generic AST files

modified file headers, and added the ast_reg hjson files
RTL updates

Also:
1) Removed defparams + other coding style compliance.
2) Added translate_off/on pragmas so synthesis won't break
3) Added *_osc.sv files:
     In DV they generate the clocks.
     In FPGA They should be replaced with fpga PLLs.
4) updated comments

Signed-off-by: Arnon Sharlin <arnon.sharlin@opentitan.org>