diff --git a/hw/ip/otp_ctrl/dv/otp_ctrl_sim_cfg.hjson b/hw/ip/otp_ctrl/dv/otp_ctrl_sim_cfg.hjson
index 3a2807c..8d0772e 100644
--- a/hw/ip/otp_ctrl/dv/otp_ctrl_sim_cfg.hjson
+++ b/hw/ip/otp_ctrl/dv/otp_ctrl_sim_cfg.hjson
@@ -39,6 +39,16 @@
 
   en_build_modes: ["{tool}_crypto_dpi_prince_build_opts"]
 
+  build_modes: [
+    // Sim mode that enables build randomization. See the `build_seed` mode
+    // defined in `hw/dv/tools/dvsim/common_modes.hjson` for more details.
+    {
+      name: build_seed
+      pre_build_cmds: ["cd /${proj_root} && ./util/design/gen-otp-mmap.py --seed ${seed}"]
+      is_sim_mode: 1
+    }
+  ]
+
   // Add additional tops for simulation.
   sim_tops: ["otp_ctrl_bind", "otp_ctrl_cov_bind",
              "sec_cm_prim_sparse_fsm_flop_bind",
diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index c2a4e0b..99f0214 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -113,6 +113,18 @@
       name: en_ibex_tracer
       build_opts: ["+define+RVFI=1"]
     }
+    // Sim mode that enables build randomization. See the `build_seed` mode
+    // defined in `hw/dv/tools/dvsim/common_modes.hjson` for more details.
+    {
+      name: build_seed
+      pre_build_cmds: [
+        '''cd {proj_root} && ./util/topgen.py -t {ral_spec} \
+               -o hw/top_earlgrey --rnd_cnst_seed {seed}
+        ''',
+        "cd /${proj_root} && ./util/design/gen-otp-mmap.py --seed ${seed}"
+      ]
+      is_sim_mode: 1
+    }
   ]
 
   // Add options needed to compile against otbn_memutil, otbn_tracer, and
@@ -405,7 +417,7 @@
       sw_images: ["sw/device/tests/otbn_ecdsa_op_irq_test:1"]
       en_run_modes: ["sw_test_mode_test_rom"]
       run_opts: ["+sw_test_timeout_ns=28000000"]
-    }  
+    }
     {
       name: chip_sw_otbn_mem_scramble
       uvm_test_seq: chip_sw_base_vseq